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Design Features |
Dynamically reconfigurable logic—designs whose function can be customized to a particular system or application on the fly—brings possibilities with hairy challenges.
The phrases "reconfigurable hardware" and "stretch-resistant socks" mean different things to different people. As those of us who are older, wiser, and a little sadder know, stretch-resistant actually refers to socks that will stretch—they just do their best to resist it for a while. Similarly, the term reconfigurable is subject to myriad interpretations, depending on the observer's point of view.
As a starting point, the term "reconfigurable" refers to electronic products whose function can be customized to a particular system or application. There are obvious benefits to making one product (that can be customized) many times, as opposed to making many application-specific products once.
Unfortunately, what is implied by reconfigurable is a moving target that is evolving over time as new technologies and techniques become available. Throughout most of the 1980s, the most sophisticated level of customization was displayed by products based on programmable logic devices (PLDs). Products of this type were usually targeted at a particular application and then focused toward a specific implementation. By comparison, the advent of field-programmable gate arrays (FPGAs) in the late 1980s opened the door to products which could be almost totally customized for radically diverse applications. To permit the presentation of a consistent view, we will adopt the following terminology:
A classic example of a
product whose function may only be customized once is a car
radio, of which there may be a variety of low-end, mid-range, and
high-end versions. It is not unusual for all of these variations
to be constructed on identical circuit boards, which can be configured
by adding or removing components and modifying switches or
jumpers (Figure 1
).
In fact, it is common for a number of competing automotive manufacturers to use the same basic circuit board. The major differences between models is often the quality of their cases and the number of buttons and dials that they support. Of course, the circuit boards used in these radios are only configurable from the viewpoint of the manufacturer—from the user's perspective, their function is cast in stone.
A similar example that may be a little closer to home is digital wrist watches. It's possible to purchase very inexpensive watches with very limited functionality. It's also possible to purchase extremely expensive watches that can simultaneously display the current time in Tokyo, Paris, London, New York, and Moscow, play 16 immediately annoying tunes, and have calculators rivaling the control panel of the space shuttle thrown in for good measure. But it's not beyond the bounds of possibility that both models contain identical integrated circuits! In the case of the simpler model, a hard-wired voltage level applied to one of the device's pins instructs it to pretend to be "cheap and cheerful." Once again, the major difference between the two models is the quality of their cases…and the price tag.
Hardware that is
simply configurable is obviously limited, because everything that
the product can do has to be designed into its base configuration,
which has to encompass all possible variants. One technique for
producing a product whose function may be extended beyond its
original design objectives is to base that product on devices
that can be programmed. For example, employ PLDs to act as hardware
truth tables, Boolean equations, or state machines (Figure 2
). In all of
these cases, the functions of the truth tables, Boolean equations,
and state machines can be modified by simply exchanging the
programmable device for an upgraded version.
Another, similar technique is to use nonvolatile memory devices to store firmware programs for use by a microprocessor or microcontroller. An example could be a set of instructions used by a microprocessor to play a tune such as the National Anthem on a musical door chime. Different countries could use different versions of the PROM.
The above examples could employ PLD, EPLD, EEPLD, or flash-PLD components, and from a board-level perspective, the board itself would be classified as reconfigurable. However, from a device-level viewpoint, PLDs would fall into the category of configurable, and their more sophisticated cousins, EPLDs, EEPLDs, and flash PLDs, would be categorized as reconfigurable. Additionally, you can refer to EE-based and flash-based components as "in-system programmable" (ISP), because you can reprogram them while they're resident on the circuit board.
The advent of
SRAM-based FPGAs presented a new capability to the electronics
community: dynamically reconfigurable hardware, or designs that
you can reconfigure on the fly. As devices, FPGAs can be
difficult to characterize, because each FPGA vendor fields a proprietary
architecture. However, a generic architecture illustrates the sophistication
of FPGAs as compared to traditional PLDs (Figure 3
).
The device consists of programmable logic blocks, each connected to programmable connection matrices, which are in turn connected to programmable switching matrices. Each programmable logic block may contain a selection of primitive logic gates and register elements. By programming the appropriate links, each logic block can be individually configured to provide a variety of combinational and/or sequential functions. The programmable connection matrices establish links to the inputs and outputs of the relevant logic blocks, and the programmable switch matrices route signals between the various connection matrices. In short, by programming the appropriate links in the connection and switch matrices, the inputs and outputs of any logic block can be connected to the inputs and outputs of any other logic block.
FPGAs can contain a
large number of logic gates and registers, which can be connected
in widely different ways to achieve a desired function.
SRAM-based variants augment the capabilities of standard FPGAs by
allowing new configuration data to be downloaded into the device
by the main system in a fraction of a second. In the case of
these devices, a few of the external pins are dedicated to
loading the data; they include the enable, clock, and data
inputs. When the enable input is placed in its active state,
edges on the clock are used to load the device's SRAM with a
stream of 0s and 1s, which are presented to the serial data
input. Although all of the logic gates and SRAM cells are created
on the surface of a single piece of silicon substrate, it may be
useful to visualize the device as comprising two distinct strata:
the logic gates and the programmable SRAM "switches" (Figure 4
).
The versatility of these in-circuit-reconfigurable devices opens the floodgates to a wealth of possibilities. For example, when a system is first turned on, it might configure all of the FPGAs to perform diagnostic functions on themselves and on the circuit board. After the system finishes the diagnostic checks, it can dynamically reconfigure the FPGAs to fulfill the main function of the design.
Another example is the Tomahawk cruise missile, which uses one technique to control itself while flying over water and another while soaring over land. When the Tomahawk crosses the boundary from water to land, or vice versa, its FPGAs become dynamically reconfigured, changing from water-navigation mode to land-navigation mode in a fraction of a second. (Of course, some of us might take the view that it is inherently unwise to have an armed missile flying around in a mindless state while it reprograms its own brain, but philosophical questions such as these are beyond the scope of this article.)
The main limitation with the majority of SRAM-based FPGAs is that it is necessary to load the whole device. Apart from anything else, it is usually necessary to halt the operation of the entire circuit board while these devices are being reconfigured. Additionally, the contents of any registers in the FPGAs are irretrievably lost during the process.
To address these issues, manufacturers developed a new generation of FPGAs several years ago. In addition to supporting the dynamic reconfiguration of selected portions of the internal logic, these devices also feature
The latter point is of particular interest, because it allows one instantiation of a function to hand over data to a new instantiation of a function. For example, a group of registers may be initially configured to act as a binary counter. Then, at some time determined by the main system, the same registers may be reconfigured to operate as a linear feedback shift register (LFSR), whose seed value is determined by the final contents of the counter before it was reconfigured.
Although these devices are evolutionary in terms of technology, they are revolutionary in terms of the potential they offer. To reflect their new capabilities, appellations such as "virtual hardware," "adaptive hardware," and "Cache Logic" are beginning to emerge (Cache Logic is a trademark of Atmel Corp).
The phrase "virtual hardware" is derived from its software equivalent, "virtual memory," and both are used to imply something that is not really there. In the case of virtual memory, the computer's operating system pretends that it has access to more memory than is actually available. For example, a program running on the computer may require 10 Mbytes to store its data, but the computer may have only 5 Mbytes of memory available. To get around this problem, whenever the program attempts to access a memory location that does not physically exist, the operating system performs a sleight of hand and exchanges some of the contents in the memory with data on the hard disk. This practice, known as swapping, allows the program to perform its task without having to wait while someone runs down to the store to buy some more memory chips.
Similarly, the phrase "Cache Logic" is derived from its similarity to the concept of cache memory, in which high-speed, expensive SRAM stores active data, while the bulk of the data resides in slower, lower-cost memory devices, such as DRAM (in this context, active data refers to data or instructions that a program is currently using, or which the operating system believes that the program will want to use soon).
In fact, the concepts behind virtual hardware are actually quite easy to understand. Each large macrofunction in a device is usually formed by the combination of a number of smaller microfunctions, such as counters, shift registers, and multiplexers. Two things become apparent when a group of macrofunctions is divided into its respective microfunctions. First, there is functional redundancy, in which an element such as a counter may be used several times in different places. Second, there is functional latency: during any given clock cycle, only a portion of the microfunctions are active. Thus, the ability to dynamically reconfigure individual portions of a virtual hardware device means that a relatively small amount of logic can be used to implement different macrofunctions.
By tracking the
occurrence and use of each microfunction—then consolidating
functionality and eliminating redundancy—virtual hardware devices
can perform far more complex tasks than they would appear to have
logic gates available for. In a complex function requiring 10,000
equivalent gates, for instance, only 2000 gates may be active at
any one time. Thus, proponents of this technology claim that by storing,
or caching, the functions implemented by the extra 8000 gates in
a separate memory device, a smaller, faster 2000-gate device can
be used to replace a larger, slower 10,000-gate component (Figure 5
).
In fact, it is even potentially possible to "compile" new design variations in real time, which may be thought of as dynamically creating subroutines in hardware! Hence the phrase "adaptive hardware."
A sample application
of dynamically reconfigurable logic was proposed by Pilkington
Microelectronics (PMEL) in 1995. PMEL's idea is to construct a
device containing an array of DSP cores. Each of these cores
would be dynamically reconfigurable, as would the interconnect between
them. Perhaps the most interesting point about this proposed
device is that the configuration data would not be loaded
serially through special pins, but would instead be appended to
the front end of the data stream and loaded in parallel (Figure 6
). If you
wanted to view a video using this device, then irrespective of
the compression scheme, the operating system would simply append the
appropriate configuration data to the front of the data stream
and the device would reconfigure itself accordingly. This
technique accommodates evolutionary changes to existing
compression algorithms and has the potential to handle completely
new compression techniques when they become available. The end
result is that a computer based on this technology might actually
survive more than three months before becoming obsolete.
One of the major problems in the electronics industry today is managing designs with multiple variants, each of which may have a number of versions, each of which, in turn, may have a number of revisions. Another problem is in accurately representing sophisticated interconnect delay effects, particularly in the case of deep-submicron technologies. These problems are only exacerbated in the case of dynamically reconfigurable systems.
Today's designers are armed with an impressive arsenal of tools that offer a wealth of capabilities, such as graphical representations (including state diagrams and flowcharts), automatic HDL generation from these graphical representations, and synthesis technology to move the designs to the implementation level. The problem is that today's tools are predominantly focused on static design views whose function does not change. Additionally, the current method of communicating design data at the implementation-level between tools, such as design capture and design layout, is usually in the form of netlists.
The limitations of the tools dictate that each permutation of a design must be verified in isolation, which results in extremely cumbersome methodologies. Also, in the case of dynamically reconfigurable hardware, the designer loses access to anything that is happening during the process of reconfiguration.
Today's methodologies and tools can be used for designs that have a limited number of permutations; for example, designs with a self-test mode and an operating mode as discussed above. But the problems may well become untenable in the case of virtual hardware, in which there may be hundreds or thousands of different configurations. Even worse is the possibility that, within the foreseeable future, some of these configurations may be determined by the hardware itself. If this scenario seems unlikely, consider the somewhat equivalent case of neural networks, which can make decisions without their designers being fully cognizant of the process by which these decisions are arrived at. Thus, although the wave of new devices introduced above offers almost unbounded possibilities, current methodologies and design tools are ill-equipped to adequately manage dynamically reconfigurable designs. Addressing these methodologies and creating these tools will likely be one of the major tasks facing the EDA industry in the coming years.
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Author's
biography Clive "Max" Maxfield, member of the technical staff (MTS) at Intergraph Electronics (Huntsville, AL), helps specify Intergraph's electronic-design-automation (EDA) products (phone (800) 837-4237). In addition to numerous technical articles and papers, Max is also the author of Bebop to the Boolean Boogie: An Unconventional Guide to Electronics (ISBN 1-878707-22-1). To order, phone (800) 247-6553. |
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