Design Features November 21, 1996

Closed-loop flow control manages ATM channel bandwidth

David Copeland, Texas Instruments Inc

Today's designers, in an effort to meet the demands of increasing chip densities and quality requirements, are employing automatic test-pattern generation, augmented by scan techniques, to achieve high, predictable fault coverage and minimize test times.

  Design for test (DFT) achieves high-quality test patterns and ensures low defect levels. As memory and gate densities increase, you find that adequately testing one chip can require combinations of different test approaches, from partial-scan techniques to built-in self-test (BIST) circuitry. The IEEE 1149.1 Test Access Port and Boundary-Scan Architecture standard (Reference 1) facilitates the smooth integration of various test techniques and eliminates much of the overhead associated with DFT.

  Chip designers aren't the only beneficiaries—scan techniques are also gaining acceptance for testing highly complex pc boards, in which traditional in-circuit testing and bed-of-nails techniques are insufficient for probing all board interconnections. In fact, IEEE 1149.1 originally emerged to solve complex pc-board testing problems. For board testing, IEEE 1149.1 provides a set of predefined instructions for interconnect, component, and cluster-testing capabilities.

  Many chip designers routinely incorporate boundary scan by default because of familiarity with the IEEE 1149.1 standard for board testing. Most logic-synthesis tools offer basic automatic boundary-scan synthesis capabilities, so incorporating basic boundary-scan structures has become a push- button approach.

  The IEEE 1149.1 boundary-scan standard allows privately defined test instructions, so that one test interface can act as a protocol for many, or even all, of your test problems. In addition, new, more flexible techniques for boundary-scan synthesis provide custom implementation of the 1149.1 standard's test-access port (TAP). For instance, users can specify user-defined instructions, to interface boundary-scan circuitry to internal test structures, and to provide behavioral, synthesizable JTAG models to facilitate design and verification of boundary scan up-front in the design phase, rather than as a back-end add-on to logic synthesis.

Scan testing internal logic

  DFT techniques are now widely accepted to help designers achieve high-coverage vector sets. Increasing silicon densities and high-level design automation, such as synthesis, have almost completely removed the IC and ASIC designer from understanding the structure of his design. Therefore, automatic test synthesis, the process of incorporating test structures into a design, and automatic test-pattern generation (ATPG) are becoming commonplace for VLSI designs having more than 10,000 gates. Of these DFT approaches, scan is the most widely used. The scan process converts sequential elements in a design, such as flip-flops and latches, into scan cells, and stitches them into a serial scan chain for use in test mode. This process dramatically eases ATPG, because each scan cell introduces a new control-and-observe point into the design. The amount of scan introduced into a design depends on many factors, and scan methodologies include two main types: full and partial scan (Figure 1).

  Full scan converts every, or almost every, sequential element to a scan cell. It then stitches the scan cells into a scan chain, thereby reducing the ATPG task to a combinational problem. Thus, test generation runs much faster. The leading commercial ATPG tool can achieve fault coverage in the high 90% range for 100,000-gate designs in less than 20 minutes.

  However, the full-scan overhead can be prohibitively restrictive. In addition to a potential 5 to 10% silicon overhead associated with making every sequential element scannable, the design may require dedicated test logic. Test logic controls scan cells' clock, set, and reset inputs during the test (Figure 2). Without a standard protocol, such as the 1149.1 TAP, such control often necessitates chip-level test signals to constrain parts of the design. These signals could be multiplexed with existing data pins. Although multiplexing ensures that the scan test can proceed, constraining these shared pins to constant values can result in lower test coverage.

  Another method to facilitate ATPG without such high silicon overhead is partial scan. Partial scan converts only a portion of the sequential elements to scan cells, with the selection being performed by a testability-analysis tool. This process reduces the silicon overhead associated with scan and removes the possible performance degradation for critical parts of the design. ATPG with partial scan produces less predictable results, however, and takes longer than full scan. Therefore, it is less likely that multiple iterations of ATPG can be run in one day.

  However, augmenting the process with other DFT techniques can alleviate these problems. These techniques include fault-simulating functional vectors and then targeting the undetected faults for scan and ATPG and using ad hoc techniques, such as test-point insertion, to add controllability and observability to a design. The new pioneering technique of partition scan (offered by the DFTAdvisor testability tool) provides partial-scan testability selection and insertion at the design phase of each hierarchical block, increasing the control and predictability of partial-scan coverage results.

  Nevertheless, the requirements for test logic and extra dedicated test pins still exist. In fact, without a protocol such as the TAP, many more test pins may be required if a large number of ad hoc test points are necessary to attain adequate test coverage (Figure 3).

Circuit self-testing

  In addition to scan techniques, BIST—most notably memory BIST—is beginning to gain acceptance in DFT. Most large VLSI ICs and ASICs contain embedded memories, and the types of faults that occur in memories differ from those addressed by ATPG (Reference 2). Memory BIST requires an on-chip BIST controller, which applies patterns to the inputs of the RAM according to a known algorithm and which also senses the RAM data outputs and compares them to the known fault-free expected result. A single-bit pass/fail result on a dedicated signal indicates the status of the test (Figure 4).

  This type of test differs from scan ATPG in that the test routine requires only the initiation of the self test and the reading of a pass/fail flag. Hence, it needs to be scheduled separately from the scan test. Also, this technique requires many dedicated or shared external pins to initiate and control the memory-BIST application (typically, the test_reset, test_hold, test_enable, and fail signals). Depending on the design constraints, BIST controllers can span multiple memories, thus reducing the number of test pins. However, some designs may need to schedule and run multiple BIST applications separately.

  The IEEE 1149.1 provides a standard protocol for testing ICs and pc boards. Figure 5 gives an overview of the boundary-scan architecture. The 1149.1 standard defines the TAP as an interface consisting of five pins to control the test instructions:

• Test clock (TCK) clocks all 1149.1-compliant test applications and registers.

• Test-data input (TDI) serially loads all test instructions and data into the 1149.1 registers.

• Test-mode select (TMS) controls the 16-state TAP controller and the sequence of test operations to be performed.

• Test-data output (TDO) serially unloads data from all instruction and data registers.

• Test reset (TRST) resets the state of the TAP. This pin is optional, because a sequence of five successive 1s applied to TMS also resets the TAP.

  The TAP controller is a 16-state, finite-state machine that controls the sequence of test operations. TMS controls the state transitions (Figure 6). The state machine controls two major functions: defining when to load values into the instruction register and defining when to load values into one of the data registers (defined by the loaded instruction). The 1149.1 standard provides precise definitions of each state in the TAP controller. Basically, a sequence of values to TMS moves the TAP controller through the Capture-, Shift-, and Update-IR states, and allows instruction loading/unloading from the test controller via TDI and TDO. Sequencing through the Capture-, Shift-, and Update-DR states allows test data loading/unloading to and from the data register specified by the current instruction.

  The 1149.1 standard provides nine predefined instructions (Table 1). Three of these instructions are mandatory; the other six are optional. These instructions define which data registers to place between TDI and TDO. A standard 1149.1-compliant TAP must contain at least two data registers—the boundary register, which allows data to be serially loaded and captured at all primary I/O pins of the device, and the bypass register, a single-bit register allowing pc-board tests to bypass the device. Also, the optional instructions may require additional data registers, such as a device-ID register and a USERCODE register.

  Furthermore, the designer can program user-defined instructions into the TAP to perform user- or design-specific test functions. These instructions place a user-defined data register between TDI and TDO, using the TAP to load and unload the data. The data register can include any register, either internal or external to the device core. For example, it could be a scan chain, a register that sets constraints on core pins during test mode, or a register to initiate and read out a BIST test. In fact, private instructions and techniques can integrate a 1149.1 test controller, internal scan, and BIST such that the five-pin TAP could provide access to all test structures. This approach places no burden on extra pin count or loss of test coverage due to pin sharing, regardless of the number of scan chains, test constraints, and self-test structures on chip.

  Scan chip testing can use either stand-alone or boundary-scan mode. Stand-alone mode places the TAP controller in the test-logic-reset (TLR) state, effectively bypassing boundary scan. Stand-alone mode provides direct access to the scan-in, -out, and -enable ports at the chip boundary, and it also allows simultaneous access to multiple scan chains at primary inputs and outputs for more efficient chip testing. Board testing cannot use stand-alone mode but instead uses boundary-scan mode, in which the test patterns are loaded using the TDI port. Because one scan input (TDI) loads all test patterns in boundary-scan mode, it takes longer to load the test data than in stand-alone mode. Thus, stand-alone mode at the chip level provides shorter test time.

   Figure 7 shows how stand-alone mode multiplexes the scan-in and -enable signals to make them available at the top-level logic. The scan-in pin is multiplexed with the TDI port. The scan-enable port is multiplexed with Scan Instruction and Shift-DR signals. When the scan instruction is loaded in the instruction register and the TAP controller is in Shift-DR state, the scan-enable signal is enabled for scan operation. The control for the multiplexers comes from the TLR state.

Clock gating

  TCK provides clocking for the TAP controller and boundary-scan cells. During test mode, either TCK or system clocks clock the system logic. If TCK clocks the system logic during test mode, clock-gating logic is needed (Figure 8).

  When a scan instruction is loaded into the instruction register, TCK is connected to the core logic clock during Shift- and Capture-DR states of the TAP controller. The Shift-DR state loads and unloads the scan chain, and the Capture-DR state captures data into scan cells. Multiple system clocks are derived from TCK during test mode. If a system clock provides clocking for system logic during test mode, the system clock must be synchronized with TCK.

  The EXTEST instruction is the only instruction needed for interconnect testing at the board level. Internal chip testing, however, requires some additional instructions. Internal chip testing implies exercising chip circuitry using test patterns and internal scan chains. Two approaches can connect boundary scan with internal scan. The first uses one instruction; the second uses multiple instructions.

  Understanding the operation of test patterns facilitates understanding internal chip testing using boundary-scan circuitry. A test pattern or test cycle for internal scan includes four steps:

• Load/unload scan-chain activates the scan_enable signal, placing the test-pattern data on the scan-in pin and serially shifting data through the scan chain. While a new pattern loads through scan-in, the data captured in the previous test pattern unloads through scan-out.

• Force PI forces stimulus data on primary inputs.

• Measure PO measures circuit response on primary outputs.

• Pulse clocks pulses the system clock, capturing response from combinational logic into scan cells.

  The first internal chip-testing approach defines an optional instruction (MULT_SCAN) to interconnect internal- and boundary-scan chains between TDI and TDO. Figure 9 shows two possible options for connecting the internal- and boundary-scan chains.

  The circuitry for the first option of the MULT_SCAN instruction includes a multiplexer, controlled by the MULT_SCAN instruction, at the input of the internal scan chain. One input of the multiplexer is the output of the boundary-scan register, and the other input is TDI. The second option includes a multiplexer, again controlled by the MULT_SCAN instruction, at the input of the boundary-scan register. One input of this multiplexer is the output of the internal-scan chain, and the other input is TDI.

  If the same clock captures data into both the internal- and boundary-scan chains, clock-skew considerations become important. When you use the MULT_SCAN instruction, the load/unload of scan-chain data is done in the Shift-DR state of the TAP controller. The capture of combinational logic responses into scan cells is done in the Capture-DR state of the TAP controller. The sequence of steps needed to perform internal chip testing using this approach follows:

 1. Reset the TAP controller. As a result of reset, the TAP controller is in TLR state.

 2. Load the MULT_SCAN instruction in the instruction register.

 3. Advance the TAP controller to the Shift-DR state.

The following additional steps repeat for every test pattern:

 4. Set the clocks to the inactive state.

 5. Load/unload the scan chain. The last shift occurs while leaving the Shift-DR state.

 6. Advance the TAP controller to the Capture-DR state.

 7. Apply the system clocks using TCK as the system clock. The application of TCK changes the state from Capture- to Shift-DR.

 8. CRepeat steps 4 through 7 in this process for every test pattern. There is no need to load any instructions for successive patterns.

  The following approach is based on Reference 4. Here, three instructions provide internal-scan testing:

• CORE_SCAN activates scan-enable and connects the internal-scan chain between TDI and TDO. The load/unload operation for the scan chain is done in the Shift-DR state of the TAP controller.

• CORE_MEASURE connects the boundary-scan register between TDI and TDO, applies stimulus at primary inputs, and measures responses at primary outputs. It shifts the test pattern through TDI into the boundary-scan register to apply stimulus at primary inputs, changing values on the primary outputs. The responses at primary outputs are unloaded by unloading the boundary-scan register through TDO. The scan_enable signal is deactivated, and system clocks are not applied. This instruction connects the boundary-scan register between TDI and TDO.

• CORE_CAPTURE captures the responses of the combinational logic into scan cells. Application of one system clock during the Shift-DR TAP-controller state captures responses into scan cells. This instruction deactivates the scan_enable signal.

  The sequence of steps needed to test a device using this approach are as follows:

 1. Load the CORE_SCAN instruction into the instruction register.

 2. Load the test-pattern stimulus using the Shift-DR controller state.

 3. Load the CORE_MEASURE instruction into the instruction register.

 4. Shift the parallel test pattern stimulus into the boundary-scan register using the Shift-DR controller state.

 5. Advance the TAP controller to the Update-DR state, resulting in application of new stimulus at primary inputs.

 6. Advance the TAP controller to the Capture-DR state to capture responses at primary outputs into boundary-scan register.

 7. Advance the TAP controller to the Shift-DR controller state to unload responses at primary output from the boundary-scan register through the TDO port.

 8. Load the CORE_CAPTURE instruction into the instruction register.

 9. Advance the TAP controller to the Shift-DR state and generate one system clock to capture responses of combinational logic into scan cells.

  This approach requires loading three separate instructions for every test pattern. The single-instruction approach does not require instruction loading for every pattern, because there is only one instruction. However, in this second approach, the internal-scan registers and boundary-scan chain are clocked in different test cycles, so there are fewer clock-skew considerations compared with the single-instruction approach.

Combining multiple scan chains

  The scan cells in the design are sometimes divided into independent subchains to reduce the test time needed for loading scan cells. The boundary-scan interface has one scan-in (TDI) and one scan-out (TDO) port, which provides data for all scan cells. Therefore, either all chains must be interconnected to form one scan chain, or individual instructions need to be defined for every scan chain. If a separate instruction is defined for every scan chain, the instruction must be loaded into the scan chain to load the scan data. This method is inefficient compared with combining all chains and defining one instruction to load all scan chains. Figure 10 shows connection of multiple scan chains to form one scan chain.

  The various approaches entail different costs with respect to test cycles. Assume that multiple scan chains are serially connected to form one scan chain for boundary scan. Assume that N represents the number of cells in the internal-scan chain, B represents the number of cells in the boundary-scan register, and J represents the number of cells in the boundary-scan instruction register. One test pattern in stand-alone mode requires these test cycles:

Function Cycles
Scan in/out N+1

Capture 1
Total N+2

  One test pattern in boundary-scan mode using single instruction requires these test cycles:

Function Cycles

Scan in/out N+B

Advance TAP controller

  to Capture-DR 3

Capture 1

Total N+B+4

  One test pattern in boundary-scan mode using multiple instructions requires these test cycles (Reference 4):

Function Cycles

Load scan instruction J+7

Scan in/out N+6

Load measure instruction J+7

Shift in parallel stimulus B+6

Shift out the response B+6

Load capture instruction J+7

Execute capture instruction 6

Total 2B+3J+N+45

  The boundary-scan-mode, single-instruction approach requires fewer test cycles than does the boundary-scan-mode, multiple-instruction approach.

  A memory BIST controller typically requires reset and self-test-enable signals. The reset signal resets the memory-BIST controller to its starting state, and the self-test-enable signal starts the self-test. The reset and self-test-enable signals can be easily generated in the boundary-scan environment. The response generated after running memory BIST could include either a pass/fail bit or signature in a signature register. The pass/fail bits or signature registers can be serially connected to form a register. In the boundary-scan environment, an instruction called MBIST can trigger memory-BIST operation. The MBIST instruction connects the register containing the pass/fail bits or signature registers between TDI and TDO. Running self-test includes the following steps:

 1. Load the MBIST instruction in the instruction register.

 2. Advance the TAP controller to the Update-IR state. Generate the reset signal to reset the memory-BIST controller.

 3. Advance the TAP controller to Shift-DR state to initialize the register containing pass/fail bit or signature register. This step is not needed if the pass/fail bit or signature register is initialized to the desired state during reset in the previous step.

 4. Advance the TAP controller to the run-test-idle state to run the test. If the instruction is MBIST and the TAP controller state is run-test-idle, activate the self-test-enable signal.

 5. Run the self-test.

 6. Advance the TAP controller to the Shift-DR state to unload the signature.

  A design with logic BIST requires a controller to control logic-BIST operation. The IEEE 1149.1 controller is suitable for use with logic BIST, and the IEEE 1149.1 defines an optional instruction called RUNBIST to help in running the logic BIST. For logic BIST, the boundary-scan chain can be reconfigured to construct the pseudorandom pattern generator and multiple-input shift register. The other option is to connect the boundary-scan chain between the pseudorandom pattern generator and multiple-input shift register. The self-test is run in the run-test-idle state of the TAP controller.

References

1. IEEE Standard 1149.1, "IEEE Standard Test Access Port and Boundary-Scan Architecture," IEEE Inc, New York, NY, 1990.

2. Van de Goor, AJ, Testing Semiconductor Memories, John Wiley and Sons, New York, NY, 1991, pg 25 to 62.

3. Robinson, MF, F Mailhot, and J Konsevich, "Technology-Independent Boundary Scan Synthesis," Proceedings of the IEEE International Test Conference, October 1993, pg 157 to 166.

4. Parker, Kenneth P, The Boundary Scan Handbook, Kluwer Academic Publishers, Norwell, MA, 1992.

5. Eichelberger, B, and TW Williams, "A Logic Design Structure for LSI Testability," Proceedings of the Design Automation Conference, 1977, pg 462 to 468.

Acknowledgment

The authors would like to acknowledge Michelle Kuyl for her contributions to this article.

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