|
Design IdeasDecember 5, 1996 |
You can use
many techniques, such as using low-power ICs and low-power wait, stop, or sleep modes, to
minimize power. The small, simple power-off circuit in Figure 1demonstrates yet another power-saving approach. The circuit and a simple program
(Listing 1) can sense a µC system's lack of activity and
subsequently remove power to the µC. The code in Listing 1
removes the power if the system is idle and you don't press the pushbutton switch within 7
minutes. This approach is similar to simply turning equipment on and off, except that the
processor, not the user, decides to turn off the power supply.
You can use either battery power or an unregulated dc line source from 9 to 12V to feed Q1 and Q2. The µC controls Q1, an npn transistor, and Q2, a p-channel MOSFET, through pin 7 of port A, PA7. As long as the gate-to-source voltage of Q2 is higher than the threshold maximum of 1.5V, this p-channel MOSFET is off, and only leakage current flows from VCC to VSS. This current is typically very low with VDS=12V and VGS=0V, IDSS=0.5 µA maximum.
You can easily modify this controlled-shutdown approach to operate at 3V because the manufacturer of the TPS1101 (Texas Instruments) optimized this device for 3V systems. The only modification necessary is the substitution of the 5V regulator with a low-dropout regulator specified for operation at 3V. Click here to download DI_SIG, #1958. (DI #1958)
Listing 1--Automatic power-off 68HC705 code |
| MOR EQU $0017 ;Mask Option Register RAM EQU
$00E0 ;Beginning of RAM memory ROM EQU $0200 ;Beginning of ROM memory VECTORS EQU $03F8
;Interrupt vectors DRA EQU $0000 ;Port A Data Register DDRA EQU $0004 ;Port A Data Direction Register TSCR EQU $0008 ;Timer Status and Control Register RTIE EQU 4 ;Real Time Interrupt Enable RTIFR EQU 2 ;Real Time Interrupt Flag Reset POWER EQU 7 ;Power ON/OFF control pin IDLE_TIME EQU 25 ;Auto-power off after 7 minutes * MOR Byte definition ORG MOR FCB $00 ;COP watchdog disable * RAM variable allocation ORG RAM IDLE_H RMB 1 ;Idle time counter (high) IDLE_L RMB 1 ;Idle time counter (low) * Program definition ORG ROM RESET BSET POWER,DRA ;Power pin is configured as output with BSET POWER,DDRA ;a high level to saturate NPN transistor ;Q1. Power on condition: Q1=ON & Q2=ON ;Now the ON push-button may be released CLR IDLE_L ;Initialization of the idle time to 7 LDA #IDLE_TIME ;minutes: 6400 RTI interrupts every 65.5 STA IDLE_H ;milliseconds. BSET RTIE,TSCR ;Start auto-power off count down CLI ;Enable interrupt generation IDLE BRA IDLE ;System is idle ********************************************************************* * Real Time Interrupt service routine * ********************************************************************* RTI_INT BSET RTIFR,TSCR ;Clear RTI flag DEC IDLE_L ;Decrement idle counter (low) BNE END_RTI ;Idle counter (low) overflow ? DEC IDLE_H ;Decrement idle counter (high) BNE END_RTI ;End of count down ? BCLR POWER,DRA ;Power off condition: Q1=OFF & Q2=OFF END_RTI RTI ********************************************************************* * External Interrupt Request service routine * ********************************************************************* KEY_DOWN CLR IDLE_L ;Reset count down to 7 minutes again LDA #IDLE_TIME STA IDLE_H RTI ********************************************************************* * Software interrupt * ********************************************************************* SWI_INT RTI ;Not used * Interrupt vectors ORG VECTORS FDB RTI_INT ;RTI overflow FDB KEY_DOWN ;Key Pressed FDB SWI_INT ;SWI not used FDB RESET ;RESET vector END |
| EDN Access | feedback | subscribe to EDN! |