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Design IdeasDecember 19, 1996 |
The block diagram in
Figure 1
shows how you can implement a 333 10-bit kernel using two dual FIR-filter and
two delay-buffer ICs. This configuration operates with clock speeds of 32 MHz.
With the appropriate modifications, the technique is also applicable to
convolutions that require greater than 10-bit resolution.
The block diagram implements the 333 convolution as the sum of three row vectors' dot products. FIR 1A and 1B implement the top two row vector dot products, and dual FIR 2B implements the bottom row vector dot product. FIR 2A provides a path for summing the three dot products to obtain the convolution sum.
You program the row-vector coefficients as the first three coefficients of FIR 1A and 1B and FIR 2B. The first coefficient of FIR 2A requires a value of 1.0 with all other coefficients set to zero. Program the output of both FIRs to A+B.
You program row buffer 1 for a length commensurate with the image row pixel length (1024 pixels) and program buffer 2 for the image row pixel length plus five additional delays. These five additional delays compensate for the pipeline delay associated with Dual FIR 1 (that is, 1024+5=1029).
Because of the rounding feature in both FIR ICs, there is no need to shift the MSB position at the output. You program the appropriate rounding value, which is easy to derive, into bits 8 to 5 of control address 001H. (DI #1966)
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