Design Features February 3, 1997

Good things come in small (IC) packages

Bill Schweber, Technical Editor

Analog functionsin tiny IC packagesgive you pc-board-layout flexibility, but consider design guidelines,thermal management,and manufacturing issuesas you "go small."

  In the rank and file of digital and analog ICs, analog devices have always marched to a different drummer. The latest in IC packaging confirms this fact. Although digital ICs are moving into ever-larger packages with hundreds of leads, analog ICs are increasingly available as minimal-function components in ever-tinier packages the size of pinheads or match heads. The route from DIPs through SOICs and MSOPs now leads through the latest popular analog manifestation—a basic regulator, a reset function, or an op amp—in a five-lead, 1.6´3´1-mm body-size SOT23 package.

  These tiny ICs offer many benefits. RF designers have long favored them for discrete devices, such as transistors, because these devices have much lower parasitics and strays. Although a smaller package for a function leads to a smaller overall design, these tiny ICs have another virtue: You can put them where you need them in the layout, thereby reducing your need to run space-wasting and constraining pc-board tracks.

  These parts can help you more easily implement last-minute design changes, such as adding a signal buffer or supply-rail regulation. Further, most components do a better job when they are closer to their targets. For example, a regulator more likely yields its spec-sheet performance when it is close to its load with less stray inductance and IR drop in its output lines.

  Despite the advantages of these tiny ICs, using them effectively requires you to adapt your prototyping techniques, layout tools, passive components, and even production methods. You also need to carefully consider your circuit board's thermal design, because these ICs' greatest shortcomings are their dissipation limits.

How small is small?

  Size is relative. When manufacturers introduced the DIP in the 1960s, it looked small and fragile compared with the TO-5 cans and other larger packages it replaced (Figure 1). The transition to tiny, sub-DIP packages is less traumatic, because virtually all designs are already using surface-mount technology (SMT).

  Many varieties of tiny ICs exist, each occupying just a little more area than the basic die itself (Table 1). Packages that are smaller than the SO-series devices that dominate today's SMT designs yield dramatic space savings (Table 2). For example, an SOT23 uses about 25% the surface area of an SO-8, for example. You come out ahead by using two SOT23 devices in place of one SO-8 for a dual op amp in that you use less board space, have greater layout flexibility, and gain improved crosstalk performance from using two dice vs one die. Also note that a 16-lead QSOP device occupies the same board area as an eight-lead SOIC.

Adjust prototyping techniques

  To design successfully with these tiny ICs, you must do more planning before physical prototyping. These ICs do not fit well with the old-fashioned technique of breadboarding a preliminary design and then probing with scope probes, culminating in improvised changes at the pc board to improve performance. It's impractical—and, with some packages, impossible—to put even one probe on these ICs; putting on multiple probes is even less practical. Unsoldering and replacing components is time-consuming, and you could ruin the circuit-board tracks.

  Instead of rushing to prototype a design, use device models to do rigorous simulation. Nearly all vendors provide Spice or equivalent models. Unless a component is essential, you should probably avoid those lacking these models. The good news is that the smaller packages have lower parasitics; therefore, the supplied models are typically more accurate in application.

  The top-grade, highest performance version of a device may not be available in the tiny package you want to use because of the fabrication and test difficulties that the IC vendors face. Be prepared to incorporate design techniques and circuit adjustments, via hardware or software, that let you use parts with less than top-grade specifications. Don't expect to find a complex component that packs multiple functions into one package, either. Vendors of tiny ICs are providing carefully defined and focused functions, such as one op amp, one converter, or one regulator, with the constraint of the largest die they can fit into a package.

  If you must do a preliminary layout of a subsection to validate a design premise, consider using ICs in larger packages. Many vendors, even if they think that most of their latest IC designs will use the tinier form factor, also provide larger DIP packages to ease prototyping. Again, you may want to consider the availability of DIPs for critical ICs as one of your device-selection criteria.

  Although you can get sockets for some of the tiny IC packages to help in prototyping and debugging, sockets for the tiniest ones are unavailable. The plethora of tiny IC packages means that getting the right socket, even if available, becomes another item on your to-do list. Instead, look carefully at your schematic and decide where you likely need to probe, such as amplifier inputs and outputs, and place vias in the board tracks near the IC body. You can then insert short, stiff-wire test points into the vias, to use as probe connection points. You can remove these vias from your final design or leave them in place in case you have to debug early production units; their effect on signal flow and impedance is negligible for most applications and frequencies.

  Review your product-development-lab habits and standard operating techniques. Tiny ICs come not in tubes, but on tape-and-reel carriers. Be sure you can get the low quantity of these parts you need for prototyping. Review how you physically handle, store, and track these parts in the hectic development environment to make sure you don't lose or scramble them.

  The lab-procedure task is more challenging than you may initially think. Because the parts are so small, their markings are abbreviated, hard-to-read, laser-branded codes just a few digits long, rather than the actual part number. All the project-team members must have discipline in documenting internal procedures. Keep careful records of the actual device number vs the barely visible part marking, and note layout corrections and changes.

  Consider the capabilities of your board-layout tools. Verify that the software has appropriately tight tolerances and can handle the smaller packages and the narrower board tracks and spacing. Also, check the linkage among the screen layout, pc-plot files, and the final photoplot to ensure that your overall system can hold the dimensions and tolerances you need. When you lay out the board, consider the placement and sizing of tracks and holes, or vias (see box, "What gets bigger, the more you take away?").

  Functionally equivalent devices don't always have the same pinouts. For example, the basic op amp in an SOT23 comes in two common variations, which affect board layout (Figure 2).

Beat the heat

  The limited dissipation capabilities of tiny IC packages define the greatest challenge in using them. Although the package dissipates little heat, the IC's lower dissipation requirements partially offset this shortcoming. The lower dissipation requirements result from the IC's limited functionality, small die, and lower operating voltages of 2 or 3V vs older 5 or even 15V rails.

  A look at some typical numbers shows the thermal difficulties. An SO-8 package can dissipate as much as 300 to 500 mW, and the SOT23 dissipation is about 150 mW. In thermal resistance, an SO-8 package has a u_AJ value of about 180°C/W, and the TSSOP mini SO-8 value is 250 to 300°C/W. The SOT23-3, a three-lead SOT23, has the highest thermal resistance, about 400°C/W.

  Solving thermal problems depends on both the IC vendor and the circuit-board designer. If possible, vendors join unused leads at the lead frame to act as heat sinks and heat paths exiting the package. For example, an SOT23-5, a five-lead SOT23, has a thermal resistance 50 to 100°C/W less than the three-lead version; a four-lead SO-8 with four unused leads joined reduces thermal resistance about 20%.

  However, IC-packaging techniques solve only a small part of the thermal problem, and using IC-mounted heat sinks is impractical. Because the package dissipation is smaller than the potential heat-sinking capabilities of the copper cladding and layers of the circuit board, designers must consider using the circuit-board copper as a thermal ally, beyond just an electrical medium. Use as-large-as-possible IC-pad patterns. In multilayer boards, connect the inner copper layers, which normally carry power and ground, to the corresponding leads on the IC with several nearby blind vias, which then function as effective heat conduits between the IC and the inner layers.

  Carefully study the IC data sheet's derating and operating curves, and look at suggested layouts in the application section of the data sheet. Although you can use estimates and rough calculations to ensure a thermally secure design, consider using modeling software or even a basic spreadsheet analysis to better understand the thermal profile of your design. This approach also helps you understand the impact of any changes you make in device placement, board traces and pad size, and layout changes.

  Vendors of tiny ICs typically test devices at 25°C but use sampling and statistical techniques to ensure performance at temperature extremes because of handler and test-fixture difficulties at these high and low temperatures. If you have any concerns about actual performance at either end of the operating range, talk to the vendor to better understand the statistical and test methods used.

  The dissipation limitations of small packages do not rule out their use for power devices. Improved device performance and lower on-resistance, for example, allow Temic and Motorola to offer a 4.2A power MOSFET in a six-lead TSOP. This package has a 2.85´3.10-mm footprint and a 1-mm profile; it occupies about one-fourth the area of an SO-8.

Can you build it, if parts come?

  Determining standard package sizes and designations occurs in two ways: Vendors can develop a package and seek a standard designation from the EIA-J { Electronic Industries Association of Japan) or JEDEC (Joint Electronics Device Engineering Council). Alternatively, a vendor can produce a proprietary package for a customer or application and either temporarily or permanently forgo an official designation. Either way, new-package development requires close coordination among makers of lead frames, molding machines, test handlers, and ICs.

  Some vendors offer nonstandard packages, such as Maxim's mMAX or Micrel's "IttyBitty". Although you may feel you have to use standard packages instead of proprietary ones, using the nonstandard ones usually presents no problem. The nonstandard factor may be height, for example, which does not affect layout the same way that footprint does. The pick-and-place equipment in production does not critically depend on the precise device size, but you must have equipment that has placement accuracy commensurate with the pitch and devices you use. Verify that other parts of your circuit-board production, including solder-paste application, board washing, and handling, can handle the tiny ICs and associated tolerances.

  If you are doing state-of-the-art production, you will have no problems unless you use ICs with lead pitches lower than 0.5 mm; pitches lower than that figure may necessitate re-evaluating your production-process compatibility. The array of available conventional and tiny SMT packages makes it easy to fall into the package-proliferation trap, but you should minimize the number of package styles you use in any design. Don't forget about passive components either (see box, "Passives are vital, too"). Several resources can provide insight into the production requirements, standards, and constraints as you migrate to smaller packages (References 1 through 4).

References

1. Electronic Packaging & Production, www.cahners.com/mainmg.
2. Circuits Assembly, www.cassembly.com.
3. The Institute for Interconnecting and Packaging of Electronic Circuits, Northbrook, IL, (847) 509-9700, www.ipc.org.
4. Surface Mount Technical Association, Edina, MN, (612) 920-7682, www.smta.org.
5. Brist, Gary, John Stewart, and Steve Bird, "Advantages of Microvia Formation Using Dycostrate Technology," Merix Corp, Forest Grove, OR.
6. Elliott, Heidi, "Honey, they've shrunk the passives—again," Electronic Business Today, October 1996.
7. Balian, Maria, and Edgar Zuniga-Ortiz, "TVSOP Application Brief," Texas Instruments Inc, August 1996, Item SCBA009A.
8. "Semiconductor Group Package Outlines Reference Guide," Texas Instruments Inc, 1996, Item SSYU001B.

Acknowledgments

Thanks to Richard Koury of Advanced Linear Devices Inc, Carl Robertson and Oliver Kierse of Analog Devices Inc, Ken Fields of Elantec Semiconductor Inc, Northe Osbrink of Hewlett-Packard Corp, Zahid Rahim of Impala Linear Corp, Bob Dobkin of Linear Technology Corp, Charlie Allen of Maxim Integrated Products, John Stewart of Merix Corp, Al Zahedi of Motorola Semiconductor, KH The of National Semiconductor Corp, Bill Hall of National (Fairchild) Semiconductor, and Wharton McDaniel of Temic Semiconductors for their comments and insight.

You can reach Technical Editor Bill Schweber at (617) 558-4484, fax (617) 558-4470, e-mail bill.schweber@cahners.com

| EDN Access | Feedback | Subscribe to EDN | Table of Contents |