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Design FeaturesFebruary 3, 1997 |
Glen Chenier, Fitel Photomatrix
An unusual circuit, the "tanktwanger," provides some clock-generating and -adjusting advantages over conventional clock-synthesis methods. You can adapt the main circuit for numerous applications, but you must take care when constructing this VHF design.
When you think of clock synthesis, you typically think of simple digital division or a PLL. However, using a wire delay line and an unusual circuit known as a "tanktwanger," you can produce a clock generator with numerous advantages, including phase that is continuously variable. Al-though originally designed for evaluating the bit-error-rate performance of a synchronous-optical-network (SONET) OC1/OC3 (51.84/155.52-Mbps) fiber-optic receiver, this circuit can also perform as a clock kick starter for Ethernet packets, generate a fiber-distributed-data-interface (FDDI) 125-MHz clock from a 20-MHz crystal, and do frequency shifting. Using the same techniques with the surface-mount ECLinPS (ECL in picoseconds) logic family (Motorola, Phoenix) extends the circuit's operation to OC12 frequencies (622.08 Mbps) and beyond.
In the case of the bit-error-rate-test (BERT) equipment, the circuit allows you to position the test equipment's bit clock anywhere within the data's eye pattern at the turn of a knob. You can then use this clock to drive a BERT receiver and either sweep the clock-sample edge across the eye pattern or position the edge in the center, all while monitoring both signals on an oscilloscope triggered to this clock edge. This approach is superior to the cut-and-try alternative of splicing together short lengths of coaxial cable to get the clock into the phase you need to do the test.
What is a "tanktwanger"?
The original term "tanktwanger" applies to a packet-data, clock-recovery circuit that starts an LC tank ringing instantaneously at the start of the first bit, when switching off the tank's dc bias releases pent-up magnetic flux. The effect is similar to twanging a guitar string, hence the name. The term also applies to gentle digital pumping of an LC tank by a series of resonant pulses, similar to stroking a violin with a bow or pushing your child on a swing every second or third cycle. You can use this technique to multiply, add, and subtract frequencies (heterodyning), thus freeing you from the limitations of only digital division and PLLs for clock synthesis.
For generating odd harmonics, you usually drive the tank from a symmetrical (50% duty) digital square wave. If even harmonics are necessary, you drive the tank with unsymmetrical pulses derived from an XOR gate and a delay line equal to one-half the period of the desired harmonic.
Balancing the coil's physical expansion (positive-temperature coefficient) with the capacitor's intentionally picked negative-temperature coefficient makes the tank's temperature stability tight enough for most practical purposes. RF-quality capacitors in various negative-temperature coefficients are readily available; from NP0 or C0G (less than 30 ppm change per degree Celsius) to N1500 (negative 1500 ppm/°C) or higher for stabilizing LC tank circuits. Two paralleled capacitors of different coefficients with properly chosen picofarad ratios can create any nonstandard temperature coefficient you need.
Tanktwanger combines ECL with LC tank
The tanktwanger phase-shift circuit in Figure 1a uses, but is not limited to, the Motorola 10H ECL family. You can also use this method of clock synthesis at OC12 rates (622.08 MHz) and higher with careful construction and the ECLinPS logic family instead of the 10H series. The figure doesn't spell out IC pin numbers because the physical layout varies with the application and the dimensional requirements. You must choose pin numbers and the IC's physical orientation to minimize noncoaxial lead lengths. Refer to the applicable Motorola data books and Reference 1 for a basic understanding of termination pulldown resistors and transmission-line effects.
Note that the circuit ground connects to the common, earth, and bench-equipment-chassis ground of the test setup. Two voltages, 2V and –3.2V, power the circuit. ECL features open-emitter outputs to drive a few hundred ohms to VEE in a ±5V system. However, ECL outputs can also drive 50 ohms to VTT, a voltage 2V more negative than VCC. By defining VCC as 2V, VTT becomes system ground, which provides the convenience of 50 ohms patch cables and test-equipment terminations of 50 ohms to system ground. Even on your breadboard, you'll find it easy to terminate 50? transmission lines with this single resistor.
The 50 ohms coaxial cables that supply the 155.52-MHz differential clock from the BERT transmitter terminate to circuit ground. IC1A's line receiver buffers the clock, and IC2's dual D flip-flop divides it by 4 to 38.88 MHz. IC2B's output drives an LC tank tuned to resonate at 38.88 MHz. A voltage-dependent capacitor (varactor diode) is part of the tank- capacitance network. When you adjust its bias voltage, this capacitor shifts the resonant frequency slightly above or below 38.88 MHz. This adjustment retards or advances the phase of the tank's sine wave by more than ±45° .
Buffer amplifier IC1B squares up the sine wave. This ECL line receiver usually operates with its inputs symmetrical about VBB (a bias 1.3V more negative than VCC), but its common-mode range allows it to operate about ground when you use 2 and –3.2V supplies. These two power-supply voltages simplify the circuit because both buffer inputs are dc-referenced directly to ground, one through the coil, requiring no bias resistors. These supply-voltage settings also permit easy mechanical mounting of a trimmer capacitor and an air-wound coil by simply soldering directly to the ground plane.
The squared-up 38.88-MHz signal drives a terminated delay line with a length equal to one-half the cycle of a 155.52-MHz clock, or 3.215 nsec. The line is simply 64.3 cm of RG174 coax cable, whose propagation delay is 1 nsec/20 cm. IC3 exclusive-ORs the delay line's inputs and outputs, producing a 3.215-nsec-wide pulse on every input transition.
This pulse is rich in even harmonics and twangs a four-times multiplier tank at 155.52 MHz. The XOR pulses twang the tank on every second cycle, and the tank itself rings to fill in the missing pulses. The buffer amplifiers in IC4 square the tank sine wave—don't reuse sections of IC1 to avoid crosstalk jitter—to produce the phase-adjustable OC3 clock outputs for the test equipment, where the coax cables are terminated with 50 ohms to bench (earth) ground. Because the 38.88-MHz clock can slew at least ±45º, the multiplied-by-4 clock can slew at least ±180°, that is, greater than one full clock cycle.
If you use a 51.84-MHz OC1 clock input instead of the 155.52-MHz clock, the 38.88-MHz tank rings at the third harmonic of 12.96 MHz instead of at the fundamental, and the circuit still produces an OC3 clock. Simply adding a wired-OR, divide-by-3, dual D flip-flop counter at IC6 creates the phase-adjustable 51.84-MHz clock, allowing the circuit to adapt easily to OC1 with minimum effort.
Consider other tanktwanger applications
The simplified schematics in Figures 2, 3, and 4show other built and tested tanktwanger possibilities. These figures don't show all the circuit details, just the general ideas.
The circuit in Figure 2—the true inspiration of the term "tanktwanger"—prebiases the tank inductor with dc during the Ethernet interpacket gap. The first edge of the first incoming data bit clocks IC3A and forces the output of IC2A from low to open-collector. This action causes the tank to ring instantly, and the clock edge for this first bit is immediately available one-half symbol time later at the eye center. The ECL buffer operates as positive ECL (PECL); the series diodes place the inputs within this buffer's common-mode range.
A 25-nsec active delay line and an exclusive-OR gate, IC1A, generate pulses from each data edge. Applying these pulses to the tank maintains ringing for the duration of the packet. This technique of ringing a tank with the data edges is well-known but results in start-up delay because of the tank's Q (quality factor). The tank's Q is the ratio of reactance to resistive losses. However, the extra kick of the dc-bias shutoff ensures an instant clock. This extra kick is the same phenomenon that you try to suppress in relay coils by placing a diode across them. This step prevents the relay coil's turn-off spike (actually, the ringing of the tank that the relay coil and stray capacitance form) from killing the switching transistor.
The tanktwanger in Figure 3 produces an FDDI 125-MHz clock from a 20-MHz crystal. The crystal drives the tank to its fifth harmonic at 100 MHz. The circuit buffers this signal, divides it by 4 to get 25 MHz, and XORs the result with the 100-MHz signal. The XOR heterodynes in the frequency domain, producing the sum and difference of the input frequencies. The sum at 125 MHz rings the second tank, and the buffer squares up the tank sine wave to produce the 125-MHz FDDI clock.
Figure 4's frequency shifter divides the master 16.384-MHz clock of a data private-branch exchange by 256 to generate an RS-232C sample clock at 64 kHz. This circuit was necessary for a test that temporarily shifted the sample clock to 57.6 kHz, exactly six times the standard 9600-baud rate, by shifting the master-clock frequency to 14.7456 MHz. The master clock had to remain phase-locked to a lab network reference, requiring a master voltage-controlled crystal-oscillator (VCXO)/PLL that could not be substituted with a function generator. The problem was that there was no time for that special-frequency VCXO. The figure 57.6 kHz is exactly nine-tenths of 64 kHz. The circuit shifts the master clock by the same ratio by dividing by 10 (first 5, then 2 for 50% symmetry waveform), then multiplying by 9 with a tanktwanger to produce a shifted master clock of 14.7456 MHz.
Build a test jig
Analyzing how all of these tanktwanger circuits work is relatively easy; actually realizing the circuit performance you want from the real physical layout requires skill. You need to know how to build this VHF/ECL circuit, how to install and tune the tank, how to make the interconnections properly, and, finally, how to probe and debug the circuit. None of these items is trivial at high frequencies. By following the suggested practices below, you can construct high-frequency breadboards that operate well for ECL and other wideband analog or digital technologies.
This discussion highlights the physical-layout and -design practices you need to build a fairly simple but specialized test jig. Sometimes, only one copy of a special test circuit may ever be necessary, and, in such cases, it is hardly worth the trouble to lay out a circuit board if you can hand-build one on perf board. But where VHF frequencies and ECL are involved, perf board doesn't quite cut it. Only a solid-copper ground plane will do if the circuit is to work at all.
This test jig uses the ECL 10H family in standard DIP packages for ease of assembly, although you can adapt the techniques for both through-hole and surface-mount RF ICs. You can breadboard surface-mount packages by substituting 0805-size resistors for 1206 types. You need to use tweezers instead of needle-nosed pliers, and a steady hand is an asset. Also, use a fine-tipped soldering iron, thin no-flux solder and no-clean flux, and the lowest heat possible to avoid damaging the components. The services of a skilled assembler would be a good idea here, although even the most fumble-fingered engineer should be able to handle the DIP packages.
Prepare the breadboard and IC pins
Start with a piece of double-sided, copper-clad, 1/16-in. pc-board material cut to about twice as large as you think you need. Circuits such as the tanktwanger tend to grow with add-on features; leave plenty of spare room for design-as-you-go additions. When you have completed and debugged the circuit, then and only then should you carefully cut off the excess pc board with a hacksaw. Determine IC physical placement and choose circuit pinouts to minimize non-coaxial lead lengths. Leave plenty of room (1 in.2) for each tank circuit.
The top component-side copper plane is ground. This plane is where you solder most ground-referenced parts for mechanical support. It connects to bench equipment and earth grounds. The underside plane is for distribution of the 2V supply. Pins 1 and 16 of each ECL IC package pass through holes countersunk on the component side (drill with a rotary hand tool with a #68 drill bit), and you solder the pins to this underside plane (Figure 5). Perform the countersinking of the ground plane with a 3/16-in. drill bit in a hand chuck deep enough to prevent the IC pins from shorting to the ground plane as they pass through. Bend the remaining pins of the ICs (not 1 and 16) outward by 90° and cut off their "tails" to leave 1/8-in.-long "pinpads" for wire and component attachment. Put self-adhesive rubber feet in the corners and middle of the underside plane to support your board on the bench and keep it from sliding or shorting out as you probe it.
When installing the prepared ICs, push pins 1 and 16 of each package through their predrilled and countersunk holes from the ground-plane side, fold them over, and solder them to the 2V underside plane. Measure the resistance from 2V to ground every time you add the next chip to ensure that you don't cause any shorts.
When all the ICs are in, install the decoupling capacitors (Figure 5). You solder these 0.01- to 0.1-mF, 1206-sized surface-mount types directly between each IC power pin and the ground plane. Solder quickly and carefully using low heat to avoid cracking the capacitor ceramic. Use three capacitors per chip—one for each of the two VCC pins and one for the VEE pin. Check for shorts with a DVM after you install each capacitor. Install at least one 10- to 100-µF tantalum capacitor from 2V to ground on the card; drill and countersink the 2V hole as you do for the IC power pins.
Use 28 to 30 AWG insulated wire to distribute –3.2V to pin 8 of all ICs in a star fashion from a central point. Solder a mechanically big 10- to 100-µF tantalum capacitor to the ground plane (remembering to ground the positive lead) and to the –3.2V to serve as a filter and the central mechanical tie point.
Solder a red wire to the 2V plane, a green wire to the ground plane, and a black wire to the –3.2V tie point for attachment to two lab power supplies. Label the wires' functions, and write them directly on the pc board with a fine-tipped felt marker to minimize the chance of somebody's someday blowing up the board with incorrect supply connections. A reverse-biased power diode across each supply to ground and a pair of fuses also go a long way toward protecting your work if reverse-polarity voltage application occurs.
Install the tank
Your board is now ready for the tank circuits (Figure 6). Install the first tank for 38.88 MHz and its varactor network. It's a good idea to complete just enough of the wiring to test-fire and resonate the first tank; then, install just enough wiring and the second tank and resonate it, and so forth. Verifying the circuit at each step of construction is much better than having to determine the source of several errors all at once on a breadboard built all in one shot.
Solder the trimmer capacitor to the ground plane using the terminal electrically connected to the adjustment screw. This connection is necessary so that touching the adjustment with a metal tool has minimal effect on tuning; when you remove the tool, you don't want the tuning to change because of the change in stray capacitance. Keep the capacitor close to the buffer-amplifier input pins. You should place the whole tank section, including the driving ECL output and buffer input pins, to allow minimum lead lengths in this area.
Next, wind the tank coils with bare tinned bus wire on a pencil or whiteboard marker, putting some space between each winding so that adjacent turns don't short to each other. Wind extra turns (seven or eight total) and cut off the excess after resonating. Bend a square foot at one end for soldering to the ground plane. Thin wire is acceptable if protected from accidental physical mashing. Heavy-gauge wire results in higher Q and battleship robustness.
Higher Q improves the final signal's spectral purity, but the Q value is not critical as long as it is reasonable (20 or higher). Don't use a lossy, ceramic resonating capacitor; use only a good RF-quality, fixed ceramic or trimmer capacitor to maintain good Q. Make sure the capacitor loss is specified by its manufacturer at RF frequencies, not at 1 kHz.
Take care with transmission-line interconnects
You must make any connection longer than an inch or two using miniature, 50 ohms coax cable (RG174 is a common type) terminated at the farthest end from the driving source with a 49.9 ohms, 1% 1206 surface-mount resistor to the ground plane. All ECL outputs that you use require this pulldown resistor even when the connection is physically too short to warrant a transmission line. However, the beauty of this requirement is that in a transmission-line environment and with the correct choice of power-supply voltages, the pulldown resistor also doubles as a matched-line termination, preventing reflections on the line and their associated problems. This ability to use long lines allows you to create precise delay lines because of propagation delay (66% speed of light or 1 nsec for every 20 cm) on the coaxial cable. Again, read Reference 1 for more transmission-line theory and design practice.
On your breadboard, the 50 ohms termination resistors fit nicely out of the way when you stand them between the ground plane and the underside of the chip's pinpad. Solder carefully to both. Solder the coax cable's center conductors to the tops of the pinpads, and solder the coax shield braids to the ground plane nearby.
Keep the coax braid connections and exposed center conductor as short as possible. Prepare the coax ends using a sharp modeling knife to cut back 1/4 in. of the insulation jacket. Try not to cut any braid strands—two or three broken strands are OK. Don't let the strands roll around on the pc board where they will lodge under a chip and eventually cause shorts. Separate the braid strands into two groups at each cable end to solder to the ground plane; this connection provides more secure cable anchoring than does a single braid connection. Strip the center conductor insulation to leave 1/16 in. of insulation past the braid split-off point.
The RG174 coax cable needs some care when soldering. Heat-resistant Teflon cables are also readily available, but the difficulty of working with Teflon more than justifies RG174. The center dielectric of RG174 can melt during soldering if you overheat the shield braid wires and if physical stress is present on the cable end. The result is a short between the center conductor and ground. To avoid this problem, wrap a rubber band around the handles of needle-nosed pliers to clamp the shield with a heat sink (Figure 7). (You may remember soldering germanium transistors this way.)
Finally, you can build shield "houses" for sensitive analog-receiver front ends from scraps of double-sided, copper-clad pc-board material (1/32-in. thickness is preferred for this purpose). You can even use tin cans or low-profile sardine cans as pc-board enclosures or low-profile, pc-board area shields soldered to the ground plane. Power leads can pass through the shield walls with feedthrough capacitors, and you can cut notches in the metal to allow signal cables to exit.
Tune the tanks
The tank's resonant frequency, fo, is equal to 1/(2pi÷LC). Tuning each tank to frequency is necessary for proper operation. Coils at known values with adjustable magnetic slugs are readily available. However, for practical VHF values, a few turns of stiff #12 to #18 bus wire with one end rigidly soldered to the ground plane is easy to make and is all that is necessary. Tune with a trimcap or select the closest standard fixed capacitor value, and tune by physical distortion and tap selection of the coil.
How do you know which way to tune? Monitor the tank sine wave with a 10-to-1 oscilloscope probe and time the cycles. Try holding a little piece of ferrite into the coil to raise its inductance and lower its resonant frequency or a little piece of brass to achieve the opposite effect. Squeeze the turns a little closer to raise the inductance, and stretch them like a spring to lower it. Watch the sine wave as the frequency you want, or its harmonic, starts to rise out of the mud and into a pure tone as you tweak the tank into an exact resonance.
Once you've found any harmonic, by knowing your tank capacitance, you can calculate your coil's inductance and, from that, the required capacitance to tune it to the desired harmonic. But it is easier just to wind five or six turns around a pencil or a whiteboard marker, diddle with it a bit to find a suitable coil tap point while using a 5- to 100-pF trimmer capacitor to search for the resonant frequency you want.
While probing the square wave at the tank-buffer output, you find the exact tuning by triggering the scope from the original clock source and noting the relative phase shift of the buffered clock as you tune the tank through resonance. Position the phase in the middle of its adjustable range. You should center-tune the 38.88-MHz signal with the phase-adjusting potentiometer set to the center of its phase slew range.
The 10-pF coupling capacitor between the tank circuit and its driver in Figure 1 provides a peak-to-peak ringing of about 300 to 500 mV to ensure full clipping in the buffer amplifier. The value of this capacitor depends on the tank's Q and the frequency-multiplication factor, but the value is not critical. Try a few values to find which works best with your coil; 10 pF should be adequate in most cases.
If you use adjustable ferrite-core tuning, be sure you are using the correct-sized plastic alignment tool. Use of the wrong tool, especially a metal screwdriver, is a guaranteed way to crack the core and lock it tightly in position.
One last caution if you really want to use store-bought, slug-tuned coils instead of winding your own high-Q, air-core instant specials: As you screw the slug into and through the winding, the inductance will rise and then fall again. If the tank capacitance is too small, the tank circuit may appear to approach resonance but never get there. The same situation is true for the trimcap, which can tune into, then away from, maximum or minimum. Be sure there are two resonant peaks near the midadjustment point as the ferrite slug screws through the coil or that there are two resonant peaks per 360° of trimcap rotation.
Probing and debugging the circuit
Remember that your scope probes will add about 10 pF to the tank capacitance, so retweak or add a 10-pF fixed capacitor when you remove the probe. Be sure your probes use that little springy thing that comes with the probe kit for solid, noise-free scope traces. Press the spring down onto your pc-board ground plane when probing. Do not use the 4-in. probe ground wire you were able to get away with in a high-speed CMOS environment. For hands-free probe holding, use hollow round pins cut out of IC sockets (Figure 8). Solder the pin to the ground plane; then, the scope-probe spring slips into the socket pin and holds fairly firmly. Rig the same setup to hold the bare probe tip poking just past the probe spring.
If you want to display an ECL output, you can remove the 50 ohms termination resistor from that point and replace it with a soldered-in RG174 cable terminated at the scope's 50 ohms input for the most accurate, noise-free scope display.
You can make a low-impedance, resistive 10-to-1 probe by soldering a 450 ohms resistor (1/8W-axial leaded, not surface mount) at the measurement point in series with an RG174 coax cable terminated by the scope's 50 ohms input (Figure 8). This probe loads the circuit under test with 500 ohms more, which is almost negligible compared with the normal 50 ohms load. Keep the resistor leads and exposed coax center conductor and shield just barely long enough to do the job. Do not use this method to measure the tank sine wave; the tanks require a high-impedance load to ring at resonance.
RG174 miniature 50ohms coax cables are recommended for equipment interconnections at OC3 frequencies and below because they are flexible and lie easily on a benchtop. Keep these cables all the same length (2m is a good, general-purpose length) to avoid clock-vs-data measurement errors that time skews on different lengths cause. Time skews are equivalent to 1 nsec for 20 cm of cable. Equal-length cables are especially important for differential-signal coaxial pairs.
1. MECL System Design Handbook, Motorola Inc.
Glen Chenier is a design engineer
with Fitel Photomatrix (Ottawa, ON, Canada), where he designs and develops
fiber-optic interface hardware for datacomm and test equipment. He has been with
the company for 31/2years.
In his spare time, he enjoys guitar, ham radio, woodworking, and railroad
modeling.
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