Design Ideas

February 3, 1997

Memory supply includes battery backup

Craig Varga, Linear Technology Corp, Milpitas, CA

The 5 to 3.3V switching regulator in Figure 1 includes battery-backup power for low-voltage memory if the 5V supply fails. The design of such a backup circuit is difficult if only one NiCd or NiMH cell is available for the backup power source and you assume that the standby current drain on the 3.3V supply is in the 5- to 10-mA range. Also, for the battery backup to function correctly, several actions are necessary when the switchover to backup power occurs. One is that the whole circuit must disconnect from the 5V supply; otherwise, the battery tries to power the whole system. Also, the switcher must shut down to a micropower condition. The circuit in Figure 1 accomplishes all of these tasks.

The circuit operates as follows: MOSFET Q₂ is normally on, providing power to the main power path. IC₁ is a high-frequency, synchronous buck regulator, which, combined with Q_3A, Q_3B, and L₂, provides the 3.3V, high-current (2.5A) output. IC₂ is a 600-kHz, monolithic boost regulator that runs from inputs as low as 1V. Together with L₁ and D₁, IC₂ provides the standby supply. IC₂'s internal low-battery detector continuously monitors the input supply. R₂ and R₃ divide the input, and IC₂ compares this divided voltage to its internal 200-mV reference. As long as the input supply voltage is adequate to maintain high-power regulation, the comparator output (LBO) is high, turning on Q₁, which in turn pulls the gate of Q₂ low to turn on Q₂. If the input voltage drops too low, IC₁'s comparator output goes low, which turns off Q₁ and, therefore, Q₂.

Approximately 5 mA of current flows through R₁ when the system operates on the main power source. This current flows through R₄ and generates a small positive offset to the voltage at IC₂'s comparator. When the system switches to backup mode, this circuit removes this current. The result is approximately 0.25V of hysteresis in the comparator switch off/on levels, which prevents chattering of the comparator. IC₂ receives power from the output through D₂. Because the comparator must have some initial power to get the system to start, D₃ provides 5V at power-up. The output of IC₂ regulates at 3.0V. When the main switcher shuts down, the output voltage starts to droop. When it reaches 3V, the boost regulator takes over and holds the output at 3.0V. This level is more than adequate to hold up inactive RAM. (DI #1976)

FIGURE 1

This circuit provides main power (3.3V at 2.5A) for low-voltage memory but also backup power (3.0V) when the 5V supply fails.