EDN Access--02.03.97 Leading Edge

In the TLA 700 series of PC-based logic analyzers from Tektronix, Windows 95 brings ease of use to feature-laden instruments. The familiar Windows interface provides easy access to PC features, such as printing and file management. Logic-analysis capabilities, on the other hand, go beyond those of benchtop and system-level instruments.

The modular units offer 2-GHz timing and 100- and 200-MHz state analysis and as many as 680 channels; a portable configuration offers 272 channels. A set of probes provides simultaneous access to the state and timing analyzers, obviating the need to connect separate probes for each mode. The passive probing system is pin-compatible with probes of earlier Tek logic analyzers and provides four times the connection density where the probes attach to the unit under test. Besides logic-analyzer modules, the mainframes accept DSO modules, including one whose performance resembles that of Tek's stand-alone TDS 684—5G-sample/ sec real-time acquisition, 1-GHz bandwidth, four channels, and 15k-sample/channel memory depth.

The heart of the logic analyzers' acquisition system is Tektronix's MagniVu technology. In each tick of a 250-MHz clock, the analyzer takes eight samples at 500-psec intervals. The analyzer stores these samples in two places: off chip in conventional RAM at full memory depth with a timing resolution of 4 nsec (asynchronous capture) or 5 nsec (synchronous) and on chip with 500-psec resolution and a memory depth of 2 kbits/channel. This architecture lets you view a state analysis and, without resampling, zoom to a timing view of a critical segment, improving resolution eight times.

The devices feature true setup-and-hold-violation triggering that lets you trigger an acquisition if a setup-and-hold interval is too short or too long, and you need not choose between too short and too long. Moreover, the trigger state machine is 16 levels deep. The systems use a menu-driven, graphical interface to address the frequent complaint that setup times are confusing.

The TLA 704 portable mainframe with a 10.5-in., 640´ 480-pixel, color LCD costs $9000. The TLA 711 benchtop mainframe costs $14,000. Logic-analyzer-module prices start at $5000. DSO-module prices start at $10,000. The high-density probes, in 34-channel groups, cost $995.

8-bit, 200M-sample/sec A/D converter avoids being flashy

High-speed A/D converters are normally implemented with flash architectures, which provide the speed needed but require a large number of comparators and, hence, consume a lot of power. The AD9054 from Analog Devices uses the company's proprietary MagAmp architecture to provide high-speed-per-bit conversion, with just one comparator per bit supported by a resident quantizer stage. In the final implementation, this 8-bit converter uses 19 comparators compared to 255 for a conventional flash design; the reduced number of comparators also simplifies and improves the input stage design.

Total power dissipation for this 200M-sample/sec converter is less than 500 mW with a 5V supply. The A/D converter has a 380-MHz full-power –3-dB bandwidth and includes an integrated track/hold amplifier and onboard reference. Its output data stream is available either as a single 8-bit parallel word or as two demultiplexed, interleaved 8-bit words at one-half the conversion clock rate. The 44-lead TQFP device costs $48 (100); a 135M-sample/sec version costs $28.

Backplanes for VME64 extensions appear

The VMEbus community is close to accepting a standard for extensions of VME64, called VME64x. These extensions will include additional connector-pin definitions, optional J0 connectors, multiple supply voltages, and EMI protection. The standards committee is still finalizing the voltage levels and timing of the VME64x signals, but the mechanical definition is complete and stable. Backplanes and enclosures that will conform to VME64x are, therefore, possible. A range of such backplanes is now available from Vero Electronics.

The backplanes include the 160-pin J1 and J2 DIN connectors with z and d pin rows and an optional J0 connector. The backplanes also provide bused connection for the additional 5V, ground, and other power lines for VME64x, and 10 spare bused pins for future expansion. Backplanes are available in seven-, 10-, 14-, 17-, and 20-slot sizes.

Fast Ethernet ICs slash hub/switch costs

Combo 10/100-Mbps Ethernet implementations are approaching de rigueur status on network-interface cards (NICs), but many applications can't afford to support the cost of hub and switch ports that operate at the higher speed. Costs have remained high because hubs and switches require horizontally integrated, multiport ICs rather than the NIC ICs that fully implement a port from the physical-layer (PHY) interface to the medium-access controller (MAC). Broadcom, however, claims that costs will soon drop, thanks to the BCM5000 family of Fast Ethernet ICs that target hub and switch applications.

For hub designs, the BCM5203 integrates four 100-Mbps PHY interfaces, each with adaptive equalization and transmit wave shaping. The company claims that the $32.60 (10,000) ICs will reduce the cost of 12-port 100-Mbps hubs from $175 to $90 per port. The 5203 targets applications in which the hub manufacturer has developed repeater-controller technology. To further lower costs, however, Broadcom offers the BCM5205, which includes four PHY interfaces and an integrated repeater core. Groups of three 5205 ICs provide a 12-port implementation; you can cascade the ICs to form 64-port or larger implementations. A BCM5020 repeater-controller IC in a management module can control all 5205 devices in such a cascaded design. The 5205 costs $39.80 (10,000), and the 5020 costs $58.50 (10,000). Broadcom claims that the 5205/5020 combination lowers 100-Mbps hub costs to $70 per port.

Switch designs, meanwhile, typically require that each port support both 10- and 100-Mbps PHY interfaces, so that users can gradually upgrade nodes to the higher speed. For such applications, Broadcom offers the BCM5208, which integrates four PHY interfaces, each of which can seamlessly operate with 10- or 100-Mbps nodes. The PHY interfaces support autonegotiation and include digital adaptive equalizers and transmit wave shapers without requiring external filters. The 5208 costs $38.70 (10,000), and Broadcom claims that it can reduce the cost of 10/100-Mbps switches from $500 to $200 per port.

Broadcom implemented the family using an all-digital design technique. The company harnessed its own DSP compilerlike tools to generate the designs that essentially implement signal-processing functions in hard-wired state machines. All of the new ICs will be available in March, except for the 5208, which will be available in April.

To digitize a video waveform—whether NTSC, PAL, or VGA—you need as many as a dozen timing and control signals. The ML6430 genlocking sync generator from Micro Linear takes the analog waveform and produces timing pulses for clamping, decoding, blanking, and video processing. It accommodates real-world difficulties, such as glitches and variations due to VCR head-switching, missing sync pulses, freeze frames, tape dropouts, and high-speed playback. The IC provides high noise immunity and is relatively insensitive to varying signal amplitudes, overmodulated color carriers, and signal glitches.

Internal PLLs and signal-handling algorithms result in short-term, locked clock-timing jitter lower than 200 psec rms and locked line-to-line jitter lower than 900 psec. You can select standard or nonstandard clock frequencies, as well as many other operating options, via pin selection or serial control bus. Micro Linear did not forget the audio channel and video playback, either: The genlock IC provides a synchronized clock to trigger an audio digitizer at 48, 44.1, or 32 kHz and supports a free-running mode to ease creation of analog video output, such as those that MPEG decoders require. The 5V, 32-pin TQFP costs $15 (1000).

16-bit DAC squeezes into eight-pin SOIC

Maxim's MAX541 packs a 16-bit DAC designed for industrial and instrumentation applications into a space-saving SOIC. The three-wire serial-input (SPI, QSPI, and Micro-wire compatible) unbuffered voltage-out device requires an external reference (typically 2.5V) and provides ±1-LSB integral- and differential-nonlinearity specifications over temperature. Output span for the DAC, which consumes 1.5 mW at 5V, is 0V to V_REF. The MAX541 can drive a 60-kilohms load and settles to ¹/₂ LSB in 1 msec with a 10-pF load.

Because many industrial applications require complete electrical isolation, the MAX541 has Schmitt triggers on its digital inputs to ease interfacing to relatively slow-transitioning optocouplers. An internal reset circuit sets the output to 0V at power-on. If you need a bipolar output swinging ±V_REF, you can use its larger sibling, the MAX542, which incorporates matched scaling resistors for use with an external precision op amp; the MAX542 also has provision for Kelvin sensing to increase output precision. The MAX541 in eight-pin SOICs or DIPs cost $9.95 (1000).

RISC chips provide secure encryption and decryption

Two security processors from VLSI perform all security encryption/ decryption within a dedicated RISC processor chip, making the security system immune to outside attack. Software security systems, on the other hand, use mathematically intense cryptographic algorithms that congest the host mPs. Offloading the algorithms to a dedicated processors increases both system and security performances. The software-only security systems are vulnerable to attack.

The PCI-based VMS230 GhostRider, a real-time encryption/decryption cryptographic processor, targets such applications as file encryption, secure communications, electronic commerce, private e-mail, and user authentication. The chip includes a PCI-bus master-slave interface, a cryptography-acceleration block, VLSI's secure vROM, an ARM RISC processor, and one-time-programmable memory. Besides the PCI bus, the chip includes an I2C serial-interface block and a generic 8-bit input-interface block. The cryptography-acceleration block supports the Data Encryption Standard (DES), Triple DES, and random-number generation. The ARM RISC manages operations on the chip, accelerating encryption/decryption.

The VMS310 NetArmor processor targets mobile computing by including the PCMCIA interface. It enables functions such as DES, access control, firewall building, digital signature processing, data authentication, certificate generation, and key management. Other circuits on the device include the ARM RISC core, the DES engine, the Secure Hash Algorithm engine, secure vROM, and VLSI's secure memory-management unit.

Both chips use an internal embedded operating system that manages the performing RSA (Rivest, Shamir, and Adelson) public-key duties; the operating system also controls data flows to and from the high-speed DES engine.

The VMS230 is available in a 144-pin TQFP and costs $37 (10,000). The VMS310 sells for $49 (10,000).

SCSI adapter operates with PC and Mac hosts

Although both Macintosh and Intel PCs now use the PCI bus, most board vendors have had to customize their offerings to ensure operation in the vastly different software environments. Now, ATTO Technology has developed and packaged a SCSI host adapter that you can install seamlessly in either type of system. The company's ExpressPCI-PS includes an Ultra SCSI implementation and supports a 16-bit-wide data bus for transfers that top out at 40 Mbytes/
sec. The board also offers autotermination, a RISC-based SCSI controller, PCI-bus-master support, and plug & play compatibility. The board carries a suggested list price of $395.

Integrated supervisory IC cuts design time, board space

Implementing supervisory functions for a processor-based system can occupy a disproportionate amount of a designer's time and board space. The TC70 and TC71 from Telcom Semiconductor incorporate the supervisory functions into an eight-pin SOIC or DIP. The devices include a power-supply monitor, a watchdog timer, an external reset override, a threshold detector, and a battery-backup controller. Both ICs generate a power-on reset and monitor unstable processor operation, which may occur from power-supply brown-out. You can "wire-OR" their outputs to a manual switch or an electronic signal to reset the processor; the ICs also integrate contact-closure debounce.

The two ICs are nearly identical but for one slight difference. The TC70 has a watchdog-disable pin, which eases prototyping and in-circuit emulation by deactivating the watchdog function. The TC71 has a power-fail output indication to act as a voltage monitor or low-battery indicator. Either 5V IC costs $1.57 (5000).

Telcom Semiconductor Inc, Mountain View, CA. (415) 968-9241, fax (415) 967-1590.

LogicVision's icBIST offers an at-speed, all-in-one built-in self-test (BIST) system for chip designs. The new product combines BIST design objects (controllers) in RTL code and software for implementing logic, memory, and boundary-scan (IEEE 1149.1) testing. During front-end chip design, icBIST automatically builds synthesizable RTL code for logic- and memory-BIST design objects and for the 1149.1 boundary-scan chain and test-access port (TAP). After the software configures the controllers, it embeds them into the chip design and makes the appropriate logic-, memory-, and TAP-controller connections.

The icBIST package includes memory BIST for all types of embedded memory, including DRAM, SRAM, and ROM. One controller handles any type, configuration, mix, and number of embedded memories on the chip. This memory BIST is also available separately as memBIST-IC. The logic-BIST controller lets you do at-speed testing of 100-MHz or faster logic; you can also use it for chips with multiple-frequency clocks. As with memory BIST's implementation, a chip requires only one logic-BIST controller. The icBIST product generates all necessary synthesis scripts and testbenches for the on-chip BIST controllers, including logic, memory, and TAP.

Prices for icBIST start at $46,500 per design for your first three designs. The memBIST-IC package costs $16,700 per design for the first three designs. Both icBIST and memBIST-IC run on Hewlett-Packard and Sun workstations.

Quickturn Design Systems has broadened its emulation product line with the CoBALT (Concurrent Broadcast Array Logic Technology) Emulation System. Quickturn based the product on a custom chip and other technology from IBM (Essex Junction, VT). CoBALT can handle designs with as many as 8 million gates and can compile a design faster than 1 million gates per hour on one design station. Using an internal, 100-MHz step clock, the emulator operates at tens of megahertz.

CoBALT's processor chip contains 64 interconnected processors. Each processor connects to every other processor on the chip, reducing CoBALT's signal-delay time and speeding emulation. Each emulation board contains 64 chips, totaling more than 4000 processors. A CoBALT system comes with as many as eight boards. Each board has eight separate clock domains, allowing you to emulate multiple designs simultaneously, even with a one-board system. CoBALT also compiles designs to fit into available domains, making more efficient use of available emulator resources. You also use this feature when emulating chips with multiple independent clocks. A fully configured CoBALT system contains 64 Mbytes of RAM and 128 Mbytes of vector memory, sufficient for debugging and analyzing complex digital chips.

CoBALT emulates a chip functionally without timing information. In addition, you use CoBALT with chips that are mostly synchronous, providing a complementary function to Quickturn's FPGA-based System Realizer emulator. The entry-level CoBALT system, with a 500,000-gate capacity costs $495,000, or less than $1 a gate.

Quickturn Design Systems, Mountain View, CA. (415) 967-3300, fax (415) 967-3199, www.quickturn.com.

Formal verification moves up in the world

The Design Insight formal verification and design software from Chrysalis lets you validate design functionality at the RTL. Formal verification tools require no vectors for design verification, unlike functional simulators, which may need millions of vectors for large designs. The first Design Insight module, a state-machine analyzer, catches problems that simulation may miss, such as deadlock, livelock (repetitive deadlock over multiple states), mutual exclusivity, and unexpected transitions.

Design Insight compiles your synthesizable RTL design description into a symbolic representation; you need not modify the design description. This representation contains equations for every state bit and primary output of the design, including clock, reset, and feedback terms. The state-machine analyzer treats any part of a design as a finite-state machine. From a list of state bits, the state-machine analyzer module extracts all reachable states and transitions. You analyze this state and transition data to determine whether a design's operation meets expectations.

Design Insight runs on Hewlett-Packard, IBM, and Sun workstations. The software works on Verilog, and the company is testing a VHDL version. The state-machine analyzer module costs $45,000.

Chrysalis, North Billerica, MA. (508) 436-9909, fax (508) 436-9697, www.Chrysalis.com.

Chip bridges USB to parallel port

Lucent Technologies has provided designers a shortcut to designing Universal Serial Bus (USB) peripherals. The USS-720 device acts as a bridge between the USB and an IEEE-1284 parallel port. You can use it to quickly adapt to the USB any existing products that offer a parallel port. You can also build the device into an external adapter that lets a user connect parallel peripherals to the USB. The USS-720 will be in production by the second quarter of this year. Baseline software drivers for Windows are under development at Lucent and SystemSoft (Natick, MA).

PCI-to-CardBus controller nears 132-Mbyte/sec PCI limit

The PCI1250 CardBus-to-PCI controller from Texas Instruments uses a dual-pipeline, wraparound-buffer architecture to achieve a 130-Mbyte/sec speed, approaching the interface's theoretical limit of 132 Mbytes/sec. The device has two ports for CardBus interfaces; each port can transmit or receive at the same time as the other port. This approach allows for two applications, such as high-speed networking and video processing, to run simultaneously.

The PCI1250 is the first of two new CardBus controllers in the PCI12 series. All parts in the series support Microsoft's PC 97 Advanced Configuration Power Interface (ACPI) for complete systems. The PCI1250 allows Windows to power down the controller while not in use and shut down socket power when a card is not inserted. The device functions in either 3.3 or 5V systems.

The PCI1250 provides for a flexible design-in by incorporating 12 programmable multifunction pins for interrupt signals, LED, or general-purpose I/O. The device also integrates zoomed-video buffers that support both slots. This feature enables routing video signals directly to the display to avoid saturating the motherboard PCI bus with video and audio data.

The second device in the family, the PCI1220, provides the same performance as the PCI1250 but lacks the integrated zoom-video buffers and has only eight programmable multifunction pins. It will be available in the same 208-pin TQFP as TI's previous CardBus controller, thus easing performance upgrade for those designs.

The PCI1250 is available in a 256-pin BGA and costs $16.52 (100,000). The PCI1220 will be available in the second quarter of this year for $14.24 (100,000).

Tiny-op-amp family offers 80- to 350-MHz bandwidths

An increasing number of manufacturers are offering high-performance analog components in SOT23 packages, which minimize board space and parasitics. Four new op amp/buffers from National Semiconductor Corp/Comlinear Product Group further extend the trend. The CLC450 through CLC453 feature combinations of bandwidth, slew rate, and dissipation and operate from unipolar or bipolar 5V supplies. The devices target applications such as driving video lines, high-speed modem interface, broadband communications, and driving digital video A/D or D/A converters.

For example, the CLC452 has a bandwidth of 130 MHz at gain of 2 with a 5V supply and dissipates 15 mW; with ±5V supplies, its bandwidth is 160 MHz, and dissipation is 30 mW. Slew rate is 400V/m sec, and second- and third-order distortion figures are –78 and –85 dBc, respectively. All devices in the family sink or source as much as 130 mA with dual supplies and 100 mA with a single supply, driving a 100 ohms load to within 1.2V of the supply rails. Prices begin at $1.39 (1000).

National Semiconductor Corp/Comlinear Product Group, Fort Collins, CO. (800) 272-9959, www.national.com.

Linear launches Web site for analog ICs

Linear Technology has launched a searchable, online information-resource site, www.linear-tech.com, for analog-IC users on the Web. The site provides access to any of the company's technical publications, including data sheets, application notes, design ideas, and articles in Linear Technology Magazine and the LT Chronicle. The site also lets you request sample devices and order the new LinearView CD-ROM, which includes the company's publications and a search engine. You can also order data books, application handbooks, and other publications and download design-tool software, such as SwitcherCAD and FilterCAD.

CALENDAR
Feb 28 to March 2	1997 Symposium on Applied Computing (SAC-'97), San Jose, CA, focuses on database technology. Other topics include experimental computing and application development. Jim Hightower, California State University—Fullerton, Fullerton, CA. (714) 773-2221.
March 9 to 13	IPC Printed Circuits Expo '97, San Jose, CA, focuses on the printed-wiring board industry. The conference's 35 workshops and tutorials address developments in design, fabrication, and assembly of pc boards. The entire conference costs $750; other packages are available. IPC, Northbrook, IL. (847) 509-9700.
March 10 to 12	Embedded Systems Conference East, Boston, offers a comprehensive program with exhibits covering development tools, hardware, and services for embedded design. Conference costs $895, and discounts are available with early registration. Miller Freeman Inc, Canton, MA. (617) 821-9210.
March 15 to 21	PCB Design Conference, Santa Clara, CA, focuses on education keep you at the forefront of pc-board-design technology and showcases tools, technologies, and services. Conference costs $795; discounts are available for early registration. PCB Design Conference, Canton, MA. (617) 828-9185.

Leading Edge

February 3, 1997

Performance underscores Windows 95-based logic analyzer