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Design FeaturesFebruary 3, 1997 |
Spice not only can predict the exact EMI levels produced by a switched-mode power supply, but also can produce plots that allow you to easily evaluate your design and the effectiveness of the EMI filter.
The classical method of quantifying conducted EMI disturbances of a switched-mode power supply (SMPS) consists of evaluating the level of the perturbing signal that the power supply generates. To simplify the calculation, you can approximate the SMPS signature using a recurrent square wave with corresponding rise and fall times. Despite the correct estimation that this procedure often produces, the differential signal that some power-supply topologies deliver can be far from this square-wave assumption. One way to achieve more accurate results is to precisely calculate the Fourier transform of each original signature. However, depending on the operating parameters, such as line level, load, and conduction mode, you have to perform the calculation for every condition.
Fortunately, you can use Spice to analyze the precise behavior of any power structure and give first assessments of future differential EMI results. Specifically, Spice can help you evaluate the exact level of differential EMI noise that an SMPS produces under a variety of line and load conditions. You can also use Spice to test your filter configuration. And, Spice can produce convenient pass or fail plots that allow you to easily compare the simulations to real measurements and to maximum EMI levels that various international standards dictate.
Generate a parasitic signal
Before setting up the simulation, you need to understand how an SMPS generates an EMI signal and how you can measure that signal. Figure 1a represents a simple offline supply, regardless of its inherent topology. An external pulse-width modulator (PWM) IC activates a transistor switch that "chops" the inductor current at a high frequency. The bulk capacitor, C_BULK, provides all of the energy because of the difference in the period between the ac mains' low frequency (50 or 60 Hz) and the switching action's high frequency (as high as hundreds of kilohertz). In other words, C_BULK acts as a reservoir for the high-frequency pulses, while the ac-mains network recharges C_BULK at a low rate.
Figure 1b shows the equivalent model of an SMPS connected to the equivalent impedance of a line-impedance-stabilization network (LISN) if the network's impedance is small and negligible at high frequencies. At high frequencies, the bridge diodes always conduct, so, in Figure 1b, a short circuit replaces them.
An equivalent current source, I_SIGNAT, whose shape corresponds to the SMPS signature, depicts the current flowing inside the inductor. You can replace the capacitor with its equivalent series resistor (ESR), R_ESR. Also, for switch cycles less than 1 m sec, you can add the equivalent series inductance (ESL), which is typically 20 nH for a 47-m F 400V snap-in capacitm or. However, keep in mind that the equivalent-series representation of a capacitor has elements that depend on frequency, bias, and temperature. An accurate model should account for all these contributions but may be too computationally intensive for some applications.
If you want to include the equivalent series capacitance in the capacitor model, manufacturers' C/C0 curves provide the capacitance value at the operating frequency (C0 is the capacitance at 20° C and 100 Hz). You can extract the ESR value from the ESR/ESR0 curves, which depict the variations of this ratio vs frequency (ESR0 is the ESR at 100 Hz and 20° C). Reference 1describes a complete capacitor model and illustrates how to accurately model a capacitor with temperature-, frequency-, and bias-dependent elements.
As defined by international standard CISPR (International Special Committee on Radio Interference) 16 for EMI measurements, the LISN's impedance starts from nearly 5 ohms at 10 kHz and rises to a constant 50 ohms above 1 MHz. In Figure 1b's model, the LISN equivalent impedance consists of two simple 50 ohms sense resistors in parallel with 50-m H LISN coils. You can also add 5 ohms resistors in series with these coils.
The actual LISN (Figure 1c), which sits between the mains and the power supply under test, measures the differential and common-mode EMI signals that the supply generates. The LISN network in Figure 1c must maintain a known RF impedance at the measuring points during a frequency-sweep analysis, isolate the device under test from incoming perturbations, and route the noise components to the spectrum analyzer.
By flowing through R_ESR, the SMPS current generates a noise voltage. This noise voltage superimposes on the main rectified dc rail and gives rise to a sense signal across both 50?ohms resistors in Figure 1b. To reduce this noise below the electromagnetic-compatibility-standard limits, an EMI filter consisting of single or multiple LC networks is necessary to isolate the mains from its polluter. Figure 1d shows the final model that you can use for simulations and tests.
Evaluate and correct harmonic disturbances
After you understand how an SMPS generates the harmonics, you need to know how to evaluate the level of these harmonics. As a starting point, you can calculate the corresponding Fourier coefficients of a classical square-wave signal with a duty cycle, D; a peak value, IP; and a finite rise time, tr. The well-known result for the fundamental is:
Suppose that you want to fulfill the FCC Part 15 Class B rules, which require that the noise level stay below a flat line at the 48-dBm V level over a frequency range of 450 kHz to 30 MHz. For example, consider an SMPS that produces a 300-mA peak current characterized by a 25-nsec rise/fall time and a 50% duty cycle into a 100-milohms ESR resistor. The switching frequency is 800 kHz. To reduce the level of harmonics, you must calculate the necessary attenuation ratio that keeps the final measured level under the normalized curve. To simplify the calculations, assume that the sum of the ESR and series resistance of the filtering coil is less than 1% compared with the 50 ohms sense resistors. In this case, you can omit the LISN's 50-m H coils because their value no longer modifies the impedance curve at an operating frequency of 800 kHz.
You can split the calculation into successive steps as follows:
1. Evaluate the fundamental current using Equation 1: The result is 200-mA peak.
2. Convert the fundamental current into a voltage using the capacitor's ESR: IPEAK´ ESR=20 mV. Transform this voltage level into decibel microvolts: 20´ LOG(0.02´ 106) or 20´ LOG(0.02)+120. The result is 86 dBm V.
3. Select a target level and deduce the desired attenuation level: FCC Part 15 Class B imposes a maximum level of 48 dBm V. If you use 40 dBm V as a maximum level, which provides a safety margin of 8 dBm V, the required attenuation is 86–40=46 dB. (Note the decibel units instead of decibel microvolts because 46 represents an attenuation ratio.)
4. Calculate the corner frequency (fc) of the LC filter that produces a –46-dB attenuation at 800 kHz using the following equation:
The result is a corner frequency of 56.6 kHz.
5. Select a small, low-cost, 100-nF X2 capacitor.
6. Extract the value of L using fc=1/(2pi¸ LC.The result is L=79 m H. Select an inductor with this minimum inductance value up to the 300-mA peak current.
By evaluating and tailoring the level of the fundamental to stay within the FCC limit of 48 dBµV, you automatically reduce the level of the remaining higher harmonics to a safe value because the FCC specification is flat along the analysis bandwidth.
However, for the stringent German VDE 0871 A/B, which the European Standard EN-55022 replaces, or even for the CISPR 15 standard, the international rule for ballast applications, the curve is much more complex. The fundamental signal of a ballast operating at 33 kHz at an arbitrary 90-dBµV value can be inside the open window at 10 to 50 kHz (CISPR 15). However, the higher order harmonics would be outside the rest of the authorized levels.
Therefore, this classical method for calculating harmonic levels leads to impractical component selection. Specifically, approximating the power supply's signature with a square wave is oversimplistic and leads to a filter design that improperly corrects the SMPS's level of parasitic noise. In addition, the current shape of a ballast differs greatly from that of a simple square wave.
FFT options with Spice
Alternatively, Spice can simulate the exact current signature and extract all the harmonics, which lets you more precisely evaluate your circuit's level of attenuation over the range of interest.
Spice can evaluate the harmonic levels in several ways. The .FOUR directive performs a classic harmonic decomposition over a period and gives results up to the ninth harmonic. Unfortunately, you can't visualize the calculations with a graphic interface. The FFT function of a Spice graphic processor usually implements the Sande-Tooke algorithm. This algorithm evaluates the harmonic coefficients from an array consisting of a binary radix of data points (128, 256…). Depending on the software editor, the processing method can differ.
During the simulation, Spice continuously modifies its internal time step to provide accurate results. Depending on the activities of the computed signals, the time step can be either shorter or longer than the transient TSTEP parameter. Generally, the minimum time step cannot drop below 10E-9 times TMAX, but this boundary also depends on the proprietary Spice algorithm. Unless you specify a different TMAX, Spice fixes it at (TSTOP–TSTART)/50.
At the end of the simulation and before storing the data, some Spice simulators, such as IsSpice from Intusoft (San Pedro, CA), invoke a linear-interpolation algorithm to produce an evenly spaced output at a TSTEP interval. IsSpice places the results in an ASCII Spice-compatible output file that the company's IntuScope investigation tool can examine. IntuScope also lets you explore the raw simulated data.
PSpice (Microsim Corp, Irvine, CA) does not interpolate the data in its .DAT file, and the user navigates through the raw acquisitions using the company's Probe graphical interface. When you initiate the FFT algorithm, Probe first interpolates the data to convert the unevenly spaced acquisitions into fixed time-step data. Probe then places the new acquisitions into a data array of the nearest binary radix of points, for example, 128 locations for a 100-point simulation. PSpice can also produce an ASCII output file with interpolated data points—but, in this case, you must specify the nodes to be saved with the appropriate .PRINT statement in the netlist file (.CIR).
Watch out for aliasing
The maximum frequency available from the interpolated data array cannot exceed the Nyquist criterion: FMAX= 1/(2´ TSTEP). If higher frequencies are present during the simulation because of a parasitic oscillation, for example, these frequencies would incorrectly appear as lower frequencies when displayed with a graphical interface. Variable time-step simulators, such as Spice, are equivalent to sampling systems. If the time step becomes too large, aliasing problems occur and the linear interpolation algorithm leads to inaccurate results. To circumvent this problem, you should clamp down on the maximum internal time step by setting TMAX to one-half to one-quarter of the TSTEP value. If TMAX is too small, the simulation becomes unnecessarily long. If TMAX is too large or not set at all, data aliasing problems can occur.
Make Spice conform to CISPR 16
The CISPR 16 EMI measurement standard specifies four measurement bands from 10 kHz to 1 GHz. The bands of most interest are bands A (10 to 150 kHz ) and B (150 kHz to 30 MHz). The standard specifies two analysis filters to sweep the spectrum from A to B. In range A, the measuring instrument uses a filter whose 6-dB bandwidth is 200 Hz. In range B, the instrument filter toggles to a 6-dB bandwidth of 9 kHz. Depending on the target compliance curve, the spectrum sweep occurs with peak, quasipeak, or average detectors.
For example, the VDE 0871 standard includes specifications for quasipeak detection, which accounts for weighted charge and discharge time constants. If the sweep succeeds with a peak detector, the power supply automatically passes the quasipeak test, which always delivers a lower output voltage. By modifying the analysis bandwidth during the sweep, the energy the filter encompasses accordingly changes, leveling the noise floor . Thus, when switching from 200 Hz to 9 kHz, the noise floor grows by a factor of 16.5 dB.
Consider a 100-m sec simulation for which the user saves the data to an ASCII output file by specifying a TSTEP value of 1 m sec. The resultant file contains 100 data points. When launched under the graphical interface, the FFT algorithm first interpolates the data and then creates an array consisting of 128 locations in which to place the new interpolated data points. The time interval becomes 100 m sec/128=0.78 m sec. With this new time interval, the displayed analysis bandwidth truncates to 1/(2?0.78 m sec), or 640.2 kHz.
Finally, in its time-to-frequency conversion, the graphical processor places half the data points in a real array and half in an imaginary array. The result from this example is then 64 points. The frequency resolution is 1/100 m sec, or 10 kHz. This last value also defines the analysis filter that is centered at 10 kHz. Some graphical processors allow you to build time windows, such as Hanning and Hamming, to reduce the spectral leaks. If you build a Hanning window over the 100-m sec temporal block, the filter width is 10 kHz at –6 dB.
Normally, for accurate comparisons between simulated and real plots, you should adjust the simulation time to match the normalized CISPR 16 filter bandwidth at –6 dB (200 Hz and 9 kHz). However, to simplify the various timing values and limit the number of simulated data points, the following examples use 500 Hz and 10 kHz as analysis bandwidths.
Set the analysis bandwidths
With a Spice simulator, you cannot modify the time-step resolution accuracy during a transient run. Nevertheless, you can run multiple transient analyses corresponding to the bandwidth you want in separate windows and then use the copy/paste function on a common window. The following statements show the Spice transient commands you can use to obtain various analysis bandwidths. The command lines correspond to the standard Spice transient statement:
.TRAN TSTEP TSTOP [TSTART] [TMAX] [UIC] [optional].
For example, the line
.TRAN 100NS 801US 400US 50NS UIC (1)
results in a 5.2-MHz sweep range, a 2.493-kHz analysis bandwidth, and 4010 data points. The line
.TRAN 24.44NS 500US 400US 12.22NS UIC (2)
results in a 20.48-MHz sweep range, a 10-kHz analysis bandwidth, and 4091 data points. The line
.TRAN 489NS 2.1MS 100US 244.5NS UIC (3)
results in a 1.024-MHz sweep range, a 500-Hz analysis bandwidth, and 4090 data points.
Multiple transient runs can be time-consuming. For switching frequencies of 100 kHz and lower, you can compromise by using a 2.5-kHz frequency step and a 5.2-MHz sweep range. These choices allow you to quickly run and modify the design.
The overall goal of the simulation is to produce an exact signature of the power system under test to see how the filter diminishes the polluting harmonics. A plot that superimposes the target standard over the final simulation waveforms clearly demonstrates if the calculation failed or succeeded.
Figure 2 shows an offline, flyback SMPS delivering 1A to a resistive load from a 220V ac rectified network. The heart of the circuit is an Intusoft UC1843 model that you can replace with any other equivalent switched model. The supply operates discontinuously and uses the current-mode technique. The UC1843 drives a high-voltage MOSFET. A clipping network protects the drain of this MOSFET against leakage inductance effects. A controlled current source, F1, routes the primary current into R_ESR and generates the corresponding noise voltage. The model uses the ESR from the manufacturer's data-sheet of the tank capacitor at the operating frequency (ESR/ESR0 curves). You can even draw the complete ESR+C+ESL network if necessary. The rest of the circuit is a direct copy of the model in Figure 1d.
VSENSE1 and VSENSE2 are the final voltages output from the LISN network. To detect the differential noise in Spice, you can simply use VSENSE1, which is the voltage across RSENSE1. Under real testing situations, you send both values to the spectrum analyzer, and, depending on whether you want to measure differential or common-mode noise, you subtract or add the two voltages and divide the result by two.
The simulation runs in two steps. First, you replace the L_FILTER and C_FILTER elements with low values, such as 1 nH and 1 pF. This step eliminates these elements from the simulation, effectively removing the filter from the circuit, and produces the simulated harmonic level generated by the SMPS under evaluation. Second, you replace these LC-filter elements with the calculated values and start a new simulation to see if the final result corresponds to the design goals. In both cases, once the simulation is complete, you can perform the FFT on the VSENSE1 voltage to get an EMI plot (Figure 3). You can easily scale the y axis for units of decibel microvolts by first LOG-compressing the y-axis FFT and then adding a 120-dB offset to the curve.
Generated using the Spice transient, Statement 1, the plot in Figure 3 sweeps from 10 kHz to 5 MHz with a 2.5-kHz resolution bandwidth. You can immediately evaluate the level of harmonics that the simulated SMPS produces and check whether the SMPS complies with the standards requirements. After identifying the guilty harmonics, calculate the required attenuation that leads to a successful final level across the two sense resistors. You should run the simulation until you obtain the correct result (Figure 4).
Note that Figure 3 is the result of running a classic FFT plot with a single-bandwidth—in this case, 2.5-kHz— analysis filter. The plot in Figure 4 is a result of performing multiple transient runs using the .TRAN Statements 2 and 3 to conform to CISPR 16's requirement of a width change of the analysis filter during the whole frequency sweep. Thus, Figure 4 shows the result of pasting two simulations, each with different analysis filters, on one graph.
Once you get this far, Spice lets you modify the operating conditions, such as the overload and line variations, to see if the resulting filter is still efficient. You can add the power-cord elements, if available, to the whole model to reveal any annoying resonance.
Simulate and correct an electronic ballast
Figure 5a shows the schematic of a 32W ballast. You typically drive this half-bridge configuration using a dedicated IC, such as the IR2155 from International Rectifier (El Segundo, CA), which implements a bootstrap technology. The main frequency is around 33 kHz with the internal dead-time set at 1.5 m sec. The circuit delivers square waves to drive an LC circuit that the active fluorescent tube strongly damps. You can model the tube by its equivalent-resistive behavior, which is weakly capacitive. To make the tank resonate at power-on, C9 tunes the LC network and provides the high-voltage spike to start the tube. Figure 5b shows the most important curves of the operating circuit, especially the current flowing through the capacitor's ESR.
To show the harmonic content of the parasitic signal, you display the VSENSE1 voltage and launch the FFT algorithm. If you superimpose the CISPR 15 compliance curve that pertains to lighting applications, you can immediately see that the level of parasitic noise is much too high. Note, however, that the fundamental of the switching frequency is roughly within the limits of CISPR 15 (Figure 6a).
In Figure 5a, C2 limits the dc-output component. To limit the amount of ac flowing in C10, thus elevating its temperature with the corresponding ESR losses, you can add a capacitor with the same value as C2 from node 23 to node 6 (the dc rail). As you would expect, the amount of noise across C10 should be lower, thus reducing the generated parasitic noise.
Unfortunately, this approach doesn't do much to lower the overall noise (Figure 6b). Adding the capacitor to produce a true half-bridge configuration cuts the level of the fundamental below VDE 0871A EMI limits but keeps the remaining spectrum virtually intact.
Using filter-design and component-selection techniques , you can determine the proper filter to install and run the simulation again until the specs are met. In Figure 7, which shows the results of trying an initial filter-component combination, it is obvious that the low operating frequency associated with a rather high-ESR capacitor leads to prohibitive component values (C_FILTER=100 nF, L_FILTER=330 m H) without completely curing the perturbations. The solution lies in selecting a higher switching frequency, choosing a capacitor characterized by a lower ESR, or implementing a multistage filter topology.
You can also modify the parameters of the circuit. For instance, if you remove R6, the circuit simulates power-on, leading to the illumination of the tube. The currents are then much higher than in normal operation. You need to ascertain if your calculated filter can sustain the transient without trouble.
Displaying the standard you want
As you can see in the plots, superimposing the compliance curve on the graphics allows an immediate pass or fail evaluation. You can accomplish this feature using any graphical processor that reads Spice-compatible ASCII files and implements the copy/paste functions. You simply create a short file in which you describe the time and amplitude coordinates of the salient points corresponding to your compliance curve. Below is the content of a sample file for the FCC Part 15 class B. You save the file using the .OUT extension:
.PRINT TRAN V(1) .END
******* TRANSIENT ANALYSIS *******
TIME V(1)
450K 48
30MEG 48
Compare simulated data to real measurements
To see how closely the simulated data matches the real results, we performed EMI tests on a 32W ballast at the Schneider Electric EMC facility (Grenoble, France). The heart of the ballast is an IR2155 operating at 33 kHz, including two 0.47-m F (C2) capacitors wired in a half-bridge configuration. There was no correcting filter at the input. We used a Rohde & Schwarz (Lanham, MD) ESH3 measuring receiver. A 1-hour warmup before the measurement ensured a stable operating point.
Figure 8 shows the results, which you can compare to the simulated plot of Figure 6b. You can account for the amplitude discrepancies between the two graphs as follows: First, it is difficult to exactly match the real and simulated operating points, especially with a fluorescent tube as the load. Second, the filtering-capacitor model does not account for capacity and ESR variations that result from frequency and bias-voltage variations. Third, the simulations omit the high-frequency noise that the diodes generate.
Input-filter instabilities
The purpose of a closed-loop power supply is to maintain the output power at a steady-state level. In other words, if the line voltage rises, the input current falls to keep the power transfer constant. From the input side, you can model this behavior as a black box that exhibits negative resistance. In an excited LC filter, the amplitude of the ringing oscillation is associated with an exponential term. The negative real part of the exponent describes the decay that the ohmic losses of the coil introduce. If by some means, the ohmic losses are perfectly compensated, the real part of the exponent would be nullified and the oscillation would never end. In our case, inserting an LC filter between the mains and the SMPS can lead to instabilities if you do not take some precautions at the design stage.
A complete filter design accounts for both the filter-output impedance, ZO, and the converter-input impedance, ZIN. To avoid instabilities, the design must fulfill this criterion: |ZO| << |ZIN|. So far, we have focused on SMPS noise from the EMI point of view. However, for those interested in simulating the complete structure, including the SMPS and its filter read SMPS Simulation with Spice3 (Reference 2). The material in Reference 3 is also relevant to people involved in SMPS Spice simulations.
You can use Spice to predict parasitic interferences that electronic equipment produces by simulating the equipment's exact current signature. You can improve the model of the final LC filter by adding all the parasitic reactances and capacitances. Unfortunately, you can't easily predict common-mode noise because it depends upon capacitive links induced by the overall layout and the positioning of the components on the pc board.
I appreciate the help of F Broyde of Excem (Maule, France), J Delaballe and S Bigot of Schneider Electric (Grenoble, France), F Uberto of the European Synchrotron Radiation Facility (Grenoble, France), C Hymowitz (Intusoft Corp, San Pedro, CA), and Dr V Bello (DrVGB@aol.com).
Christophe Basso is an engineer in the beam
diagnostics group of the European Synchrotron Radiation Facility (Grenoble,
France), where he has worked for eight years. Among other projects, he has
designed steering-coil power supplies for an X-ray feedback system. He recently
released a book about the IEEE-488.1 and .2 bus, and he enjoys mountain biking,
windsurfing, and jogging. You can reach him at basso@esrf.fr.
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