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Design FeaturesFebruary 17, 1997 |
INNOVATION/INNOVATOR OF THE YEAR
This is the seventh year EDN has held its Innovator and Innovation of the Year competition. Since 1990, we have paid tribute to the innovative products and people in the electronics industry by asking our readers to vote on finalists selected by EDN's editors from a large field of nominations.
Our job—selecting the finalists—was difficult in a year filled with advances that spanned all technical disciplines. Your job is even tougher. Please read and carefully consider the entries in each of the nine categories for the most innovative products and people of 1996. Vote on the postage-paid ballot card that appears in this special section and mail or fax in your choices. An independent research company will tally your votes, and the winners will be announced in our May 8 issue.
What's more, if you mail your ballot to us by the deadline, you'll be automatically entered to win a Dilbert Mousepad and coffee mug. Vote now, and do your part to celebrate innovation.
Dean Wallace, a senior staff
engineer at Linfinity Microelectronics, is an Innovator finalist for his design
of a family of active SCSI terminators, the recently introduced UltraMAX LX5218
and LX5219 components. Unlike previously existing linear terminators, these
components are adaptive and nonlinear; they do not require a large, external
compensation capacitor and an additional high-frequency capacitor. As a result,
these terminators react faster and yield a significantly improved bandwidth,
typically 35 MHz.
In designing the new components, Wallace looked at the fundamental issues of designing SCSI into a system. The most basic question, he found, was, "How much current can a terminator provide as quickly as possible?" By providing a large rush of current into the bus, a terminator can give a higher first voltage step on deassertion.
Wallace responded with a design that provides maximum continuous current until the voltage reaches a certain threshold—essentially approaching the performance of an ideal current source. By creating a complex, nonlinear function of voltage and current, the design optimizes the first and subsequent steps upon SCSI-bus deassertion. As a side benefit, each channel is fully isolated with its own circuitry, reducing crosstalk between channels.
In addition to his design work, Wallace is a principal member of the ANSI committee developing the new Ultra-2 SCSI interface that uses low-voltage differential (LVD) signaling. He has a BS degree in physics from Moorhead State University.
To vote for this entrant as Innovator of the Year, mark the appropriate box on the ballot.
Linfinity Microelectronics
Inc
Garden Grove, CA
(714) 372-8357
David Bingham and Charlie Allen of
Maxim Integrated Products are an Innovator finalist team for their past and
recent technical achievements. Allen, managing director of corporate
applications, defines products; Bingham, a senior scientist and a Maxim founder,
designs them. Allen has a BSEE from Michigan State University; Bingham has a BSc
degree from Imperial College London. Bingham has more than 20 US patents, six of
them held jointly with Allen, and has four more pending. The two men have worked
as a team for 13 years.
The team's most recent success is an RS-232C transceiver that uses two of Allen's patents in a sophisticated automatic-shutdown procedure. These parts look for activity (not just valid RS-232C levels) on receiver and transmitter inputs. If no activity exists on either, the transmitter shuts down, saving significant power. No software is needed to achieve the power savings; the chips are drop-in replacements for previously existing transceivers.
One of the pair's first innovations, in 1985, was a 5V-only RS-232C family of products. Allen realized that, in many portable computers, the only supply voltages needed other than 5V were ±12V for RS-232C transceivers. But RS-232C components' inputs, according to the RS-232C standard, had to accept voltages of ±30V, and the only economically viable semiconductor process then available had a 15V breakdown. In addition, developing a charge pump with ±10V rails was problematic. Bingham cleverly solved these problems, however, and other successes followed. Key developments include 3V and 1-Mbps RS-232C parts, plus parts with 15-kV ESD protection.
To vote for this team as Innovator of the Year, mark the appropriate box on the ballot.
Maxim Integrated Products
Sunnyvale, CA
(408) 737-7600
Ron Cline, Tom Davies, and
Schuyler Shimanek of Philips Semiconductors are an Innovator finalist team for
creating the CoolRunner series of CPLDs. Cline, manager of design engineering,
has a BSEE degree from MIT and holds eight patents. Davies and Shimanek are
senior design engineers. Davies has a BSEE degree from the University of
Michigan and holds 10 patents; Shimanek has BSChE and MSEE degrees from Brigham
Young University.
The team came up with two innovations to develop large, fast CoolRunner parts. The most significant innovation is the development of a digital CMOS product term (PT) that consumes very low static power. The second innovation, involving the method of PT distribution, is a logic-block architecture that handles combinatorial logic functions exceeding five dedicated PTs.
Although it's obvious that a zero-static-power PT allows higher gate counts, the ability to produce faster devices is not so obvious. Reducing total power in a large device requires reducing the current in each PT, but reducing the current reduces a PT's switching speed. The team's response to this problem was an extended-programmable-logic array (XPLA). The XPLA consists of a PAL and a PLA. The PAL achieves highest speed when a logic function can be implemented with five dedicated PTs. The PLA, for logic functions that require additional PTs, uses a technique called PT sharing (rather than PT steering), allowing multiple macrocells to share a PT. Sharing PTs provides the XPLA with its capacity advantage.
To vote for this team as Innovator of the Year, mark the appropriate box on the ballot.
Philips Semiconductors
Albuquerque, NM
(505) 858-2739
Peter Eichenberger of Viewlogic
Systems is an Innovator finalist for spearheading development of the Verilog
Model Compiler (VMC) technology, a technique that protects proprietary design
information. VMC technology allows semiconductor vendors to create and
distribute secure simulation models, thereby protecting the vendors'
intellectual property. Eichenberger, vice president and chief technical officer
of Viewlogic, has a PhD in electrical engineering from Stanford University.
Before VMC, semiconductor vendors could either protect their detailed, proprietary design information with encryption, or they could distribute only basic information, such as bus-functional models, to allow customers to simulate before the availability of first silicon. If the vendors chose encryption, they needed to encrypt for each of the many simulators on the market. If vendors distributed only basic information, customers had to wait for first silicon to fully wring out a design.
Eichenberger's solution was the invention of a technique that protects proprietary information by compiling a Verilog source-code model of core, IC, and ASIC designs into a binary model, or object file, thus avoiding the need to distribute source code. The binary model supports accurate simulations on HDL simulators, but it cannot be deciphered or reverse engineered. Models generated by VMC run on any Verilog simulator that supports standard Verilog PLI, including Viewlogic's VCS and Cadence's Verilog-XL. Synopsis puts a SWIFT wrapper around these models, enabling them to run with any SWIFT-capable simulator—almost all merchant simulators and some proprietary simulators.
To vote for this entrant as Innovator of the Year, mark the appropriate box on the ballot.
Viewlogic Systems Inc
Marlborough, MA
(508) 303-5226
DICE, a deinterlacing IC, performs
temporal and vertical video processing. It is the first single chip to convert
interlaced video into progressive-scan video for display on noninterlaced
systems. Available in both 8- and 10-bit versions, DICE accepts Y/UV video input—both
525- and 625-line formats—and the 10-bit version also accepts D1-video
format. The built-in color space converter produces an RGB output.
DICE uses a temporal filter architecture to deinterlace video. Other deinterlacing methods include field merging, line replication, and motion adaption, with the more sophisticated methods using filtering. Genesis engineers determined the optimum filter coefficients and filter-aperture values to provide deinterlacing functions all on one chip.
There are three ways the device deinterlaces. It performs static mesh processing, which is suitable for images with little or no motion. The device meshes together odd and even video fields to create an output frame, and only one external field store is required. If the image has substantial motion, the static method creates jagged artifacts on the moving image. In this case, the device employs three-field processing, a unique combination of vertical and temporal filtering on the past, present, and future fields to produce one output frame with smooth edges. This process requires two external field stores. The third process uses vertical and temporal filtering on two fields to produce the output frame more economically. This method requires only one external store.
DICE provides an alternative to the stand-alone box products that OEMs now use for integrating video line doubling into their products. The gmVLD8 is available for $48.60 (1000), and the gmVLD10 is $76.85 (1000).
To vote for this entrant as Digital IC Product of the Year, mark the appropriate box on the ballot.
Genesis Microchip
Markham, ON, Canada
(905) 470-2742
The S631001 is a 1,048,576-bit,
mask-programmable ROM organized as 128k´8 bits. Access time for any byte is less than 45 nsec
when operating from a 5V power supply (70 nsec at 3V). Reading eight data bits
from the ROM takes 45 nsec (from the 17-bit address transition to the data being
available on the output bus). The user provides data that is mask-programmed
into the ROM during fabrication, thereby eliminating additional programming cost
and circuitry. The ROM is 100% tested to the customer's data and is nonvolatile.
It is available for $1.80 (10,000).
The S631001 is a self-timed ROM. Each address pin and the chip-enable control pin have an address-detection circuit that creates a pulse when a transition occurs. The address-transition pulse starts a chain of events in the timing-chain circuit that makes it possible to achieve the fast access time. The timing-chain circuit creates signals designed to match internal delays in the ROM. The matched delay signals enable each subcircuit on the ROM to be in a precharged state at the appropriate time in the read cycle to quickly perform the operation for which the subcircuit was designed.
Creating the signal that reads the core cell transistor is a key innovation. Outside the main core, there is a small core piece programmed to simulate the worst-case, read-one current condition in the main core. A circuit reads the worst-case, read-one current from the mini core and then creates the signal indicating the core cell-transistor read is complete.
To vote for this entrant as Digital IC Product of the Year, mark the appropriate box on the ballot.
American Microsystems Inc
Pocatello, ID
(208) 234-6890
The 3DImàge integrates all
the graphics functions required for a multimedia PC. The functions include 2-
and 3-D graphics, dual hardware video windows, and display to either TV or CRT
using on-chip RAMDAC. In addition, the device collaborates with a 166-MHz,
MMX-enabled CPU to provide digital-video-disk (DVD) playback capability at low
additional system cost. It combines all these elements at a high-volume,
multimedia-PC price and adds high-quality TV-display capability.
To get these functions on one chip and to improve performance took innovative design techniques. Retaining the 3-D setup task on the controller instead of offloading to the CPU and supporting 83-MHz synchronous graphics RAM (SGRAM) gives this device significant 3-D graphics-performance improvement. Video includes not only the horizontal and vertical interpolation, but also diagonal edge detection to eliminate jagged edges for quality display. The TV display uses on-chip, three-line buffer to remove flicker and to scale down from CRT format to NTSC and PAL formats. DVD assist uses a custom hardware block that collaborates with an MMX-enabled CPU to perform motion compensation.
The design focus for this device is the entertainment PC; you can play high-performance video games on a PC with the same quality graphics as a home arcade station. The TV-display capability also lets you use a large-screen TV for games.
The product is complete with on-chip VGA, 2-D acceleration, 170-MHz RAMDAC, and PLL clocks. You just need to add memory for a complete graphics subsystem. The chip costs $32.50 (10,000).
To vote for this entrant as Digital IC Product of the Year, mark the appropriate box on the ballot.
Trident Microsystems Inc
Mountain View, CA
(415) 943-3757
The ZPSD4XX "zero-power"
devices provide a low-power means to add programmable logic, EPROM, and SRAM to
embedded-system designs. They consume 0.76 mA operating at 1 MHz from a 2.7V
power supply and 7.0 mA operating at 5 MHz from 5V. Standby power consumption is
1 mA at
2.7V. The devices are available with 32-, 64-, or 128-kbytes of EPROM, 2 kbytes
of SRAM, and programmable logic equivalent to three or five 22V10s. The devices
also have a programmable interface to almost any 8- or 16-bit microcontroller,
extra I/O, code security, and automatic power-down features. Prices start at
$10.50 for the 2.7V devices and $9.47 for the 5V devices (10,000).
Reducing power consumption without compromising performance results from combining several existing technologies. Address-transition detection allows powering down of the chip until the address changes. Address changes generate a clock pulse that equalizes the address decoder, memory arrays, and sense amps to a predetermined voltage. This voltage provides a reference to read a small voltage swing on a signal. Differential pass-transistor logic, which all logic on the device uses, also reduces power and the signal voltage swing. The dual reference sense amp reduces signal voltage swing by sensing signal direction rather than voltage. The circuitry senses signals as low as 63 mV, as opposed to conventional memory sense circuitry at 250 mV.
Alternate metal-ground EPROM architecture produces physically small EPROM cell size. It enables integration of high-density EPROM and reduced capacitance on bit lines for fast access. The 5V device has a 70-nsec access time; the 2.7V device has a 200-nsec access time.
To vote for this entrant as Digital IC Product of the Year, mark the appropriate box on the ballot.
WSI Inc
Fremont, CA
(510) 498-1723
System-programmable gate-array (SPGA) chips come in two versions: with and without embedded soft blocks or cores. The eight-member SPGA family spans 50,000 to 400,000 gates and has two devices with embedded cores that integrate mask-programmable ASIC blocks into programmable-logic bases. The SPGA architecture currently uses SRAM technology; however, the technology is switch-technology-independent, which allows future chips to use antifuse or flash technology for their programming elements.
SPGA uses hierarchical routing levels, with as many as five layers of metal and as many as eight levels of routing hierarchy. Each level of routing builds upon the prior level by a factor of four, in a two-by-two matrix. Actel uses a technique called MultiDrive Active Routing, which uses different transistors to implement logic cells and drive interconnect lines. Actel scales the interconnect drivers to match a hierarchical routing level. This method reduces worst-case (corner-to-corner) delay compared with traditional FPGA routing schemes, provides more predictable routing delays, and gives you fan-out-independent delays on a hierarchical level. SPGA technology uses additional local and global routing techniques to take advantage of the hierarchical routing methodology. Typical routing delay on a 100,000-gate device is 7.6 nsec from corner to corner. The SPGA architecture also reduces individual logic-block size compared with high-complexity FPGAs, resulting in higher chip density and speed. Pricing starts at $348, dropping to less than $100 volume pricing on maturity.
To vote for this entrant as Digital IC Product of the Year, mark the appropriate box on the ballot.
Actel
Sunnyvale, CA
(408) 522-4291
There are two key technologies in
CoolRunner that give you fast, high-density complex PLD (CPLD) chips: extended
PLA (XPLA) architecture and Philips' Fast Zero Power (FZP) design technique.
XPLA combines PLDs and PALs on one device, providing the advantages of both
types of logic. You use the PAL to provide the highest speed when you can
implement a logic function within the PAL array's five dedicated product terms
(PTs). You employ the PLA for logic functions needing more PTs, using PT sharing
instead of PT steering. PT sharing lets multiple macrocells share a PT. The
maximum incremental delay with a CoolRunner chip is 2.5 nsec, whether a design
uses one or all of the 32 available PTs in a PLA array. XPLA-based CoolRunner
devices thus give increased logic capacity and higher speed compared with CPLDs
that use a traditional PLA architecture.
FZP design replaces the sense
amplifiers, which are used to reduce capacitive loading in long word lines, with
a chain of CMOS gates. This technique eliminates the static current that each
sense amplifier/PT requires, and it reduces standby current in any CoolRunner
device to less than 100
mA.
CoolRunner chips also offer significantly lower dynamic power, set by gate
switching times. The advantage of a reduced-power CPLD structure is a CPLD
family with high-gate-count chips. Philips has developed both 5 and 3V
CoolRunner devices, with prices starting at $18.47 (100).
To vote for this entrant as Digital IC Product of the Year, mark the appropriate box on the ballot.
Philips Semiconductors
Albuquerque, NM
(505) 858-2739
The cell-based MDL60 family uses 0.5 mm CMOS technology with both DRAM- and ASIC-technology features. The chip has one silicide, two metal, and three polysilicon layers and offers 60,000 gates of fast logic (0.26-nsec gate delay at 3.3V) and 1 Mbit of hard-core (fixed-block) DRAM. The DRAM block, made possible by the storage capacitors formed by polysilicon layers, is configured as 64k´16 bits extended-data-out (EDO) memory with a 60-nsec access time. You test the DRAM using built-in self-test (BIST) techniques. Embedded DRAM reduces power consumption by as much as 60%, because fewer signals have to travel off the chip, and reduces the number of pins on the chip required for memory interfacing. Reduced power and lower pin count let you use low-cost plastic packages in many applications and makes MDL60-based products attractive for portable applications.
Other key features of the MDL60 include an ASIC core optimized for 3.3V and 3.3V/5V I/Os; high-performance PLL and I/O support, including PCI, low-voltage differential signaling (LVDS), and ATA; high-performance I/O Spice models for system-level signal-integrity analysis; test support for internal-scan automatic test-pattern generation (ATPG), 1149.1 boundary scan, RAMBIST, and IDDQ; and power dissipation of 1.6 mW/MHz/gate under average load conditions. NRE prices start at $50,000; component pricing is a function of gate count and production volume.
To vote for this entrant as Digital IC Product of the Year, mark the appropriate box on the ballot.
Samsung
San Jose, CA
(408) 954-7027
This precision op amp, in a
14-lead DIP or SOIC package, targets applications such as photodiodes,
ionization chambers, and similar charge/current sensors, all of which require a
high-transimpedance-value input device. The IVC102 achieves lower
leakage-current and charge-injection errors than do discrete designs, because of
its high level of integration and innovative architecture. The device combines
an FET-input integrating amplifier with a selection of on-chip capacitors
(including reset and hold switches). The user can select from a combination of
10-, 30-, and 60-pF integration capacitors or can use external capacitors if
desired.
The leakage current of the
integral reset and hold switches largely cancels the input bias current. Leakage
current, below 100 fA, is stable and predictable. To minimize charge injection,
the design uses dummy switches that operate simultaneously, but in opposite
phase, to the actual hold and reset switches; typical charge-injection error is
0.5 pC. The design achieves low nonlinearity, typically 0.005%, by laying out
the integration capacitors in a parallel back-to-back configuration. $4.25
(1000).
To vote for this entrant as Analog IC Product of the Year, mark the appropriate box on the ballot.
Burr-Brown Corp
Tucson, AZ
(520) 746-1111
www.burr-brown.com
These nine-channel SCSI
parallel-bus terminator ICs overcome the limitations of conventional linear
regulator-based terminators by using an adaptive, non-linear mode architecture.
This process results in higher bandwidth, elimination of external capacitors,
reduced interchannel crosstalk, and greater tolerance of system-integration
variations such as improper cable lengths. The ICs (one is active-low and the
other is active-high) thus allow designs to achieve the 20-Mbyte/sec
data-transfer rate of the UltraSCSI specification. The 35-MHz bandwidth is 100
times faster than that of existing techniques.
To achieve this performance, the UltraMAX terminators provide maximum continuous current at the highest possible rate of speed. The bus voltage vs current is not the usual straight-line function; instead, the terminator's current source acts as a complex, nonlinear source function. In addition, no large external-compensation or high-frequency capacitors are needed. Since the ICs maximize current in the first and subsequent voltage steps as the bus is deasserted, users gain more speed margin in their design. $2.08 (1000).
To vote for this entrant as Analog IC Product of the Year, mark the appropriate box on the ballot.
Linfinity Microelectronics
Inc
Garden Grove, CA
(714) 372-8357
This EIA/TIA-232 and V.28/V.24
serial-port IC, for data rates to 250 kbps, incorporates an automatic
power-saving mode, which reduces quiescent current from 500 mA to 1 mA. It further
reduces current drain by isolating the transmitters from their loads (typically
3 kiliohms each) in shutdown mode, saving several milliamps.
Shutdown and wakeup operations are automatic and self-induced, requiring no
initiation via a hardware-control signal or changes to the BIOS or operating
system.
The single-supply IC works by monitoring transmit and receive lines. When the autoshutdown circuitry does not see a valid signal transition within 30 sec on either the receiver inputs (connected to the associated peripheral) or the transmitter inputs (controlled by the system processor), the onboard charge pump and drivers are disabled. This process leaves the receivers active, but forces the transmitter outputs to a high-impedance state and reduces supply current to 1 mA. A level change on any of the transmitter inputs, or valid RS-232C levels on the receive inputs automatically wakes up the IC within 100 msec, without any external hardware or software intervention. $3.29 (1000).
To vote for this entrant as Analog IC Product of the Year, mark the appropriate box on the ballot.
Maxim Integrated Products
Sunnyvale, CA
(408) 737-7600
www.maxim-ic.com
The Microstamp is a very small,
high-performance, 2.4-GHz remote-intelligent-communications unit designed to
provide a complete RF-identification (RFID) system with the addition of a
battery and an antenna; the unit needs no crystal. It integrates a
direct-sequence spread-spectrum radio (both transmitter and receiver), a
microcontroller, and 256 bytes of low-power RAM. The IC also includes key
support functions such as clock-recovery circuitry, low-battery sensor, voltage
reference, random-number generator, and differential encoder. Applications
include toll-collection, container-tracking, identification-tag, security, and
inventory-control systems.
The device, normally available as a 20-pin SOIC, can be packaged as part of a circuit board or in a badge, tag, or similar small enclosure. Previous implementations of these system functions required several ICs; the Microstamp reduces the overall size by as much as 90%. In operation, the IC is in sleep mode until its programmable timer wakes it up, at which time it checks to see if there is a valid modulated signal present. If not, the device returns to sleep mode. If there is a received signal, the device processes the command and sends a reply.
To ease widespread adaptation and encourage interchangeability between systems and components, the vendor supports the Microstamp device with a licensed open protocol that uses 4 kbytes of on-chip ROM. $7 to $42.
To vote for this entrant as Analog IC Product of the Year, mark the appropriate box on the ballot.
Micron Communications
Boise, ID
(208) 333-7345
This "system-health-monitor"
IC for
mP
systems oversees the health of key analog and digital inputs in a system and
communicates error conditions via ISA or I2C-bus interface. The device
incorporates onboard temperature sensing, five positive voltage inputs as well
as op amps for negative voltage inputs, fan speed counters, an 8-bit A/D
converter, limit registers, and watchdog comparators into one IC. The product
generates interrupts based on user-defined, programmed limits for conditions
such as temperature, fan speed, voltages, or other system parameters.
This device monitors most, if not all, of the awkward-to-measure health "indicators" of a PC. It eliminates the need for a separate subsystem built from a handful of ICs to accomplish the same functions. The device combines suitable analog circuitry and digital functions into a focused mixed-signal IC. This approach makes it easier to incorporate these noncore (yet critical) functions into a PC, reduces required board space, simplifies electrical interfacing, offloads the system processor from these housekeeping functions, and aids more thorough parameter monitoring. $5.50 (1000).
To vote for this entrant as Analog IC Product of the Year, mark the appropriate box on the ballot.
National Semiconductor Corp
Santa Clara, CA
(408) 721-5000
www.national.com
For simplifying inclusion of an IrDA-standard compatible data link into a PC or peripheral, this integrated infrared transceiver includes both optics and analog-control circuitry in one package measuring 13´5.5´5.6 mm. Incorporating the receiver photodiode, its preamplifier stage, the transmitter-driver stage, and an LED, the device greatly reduces the number of ICs and discrete components needed to provide a half-duplex wireless link that connects to an RS-232C port. The product targets interconnecting portable PCs, desktop PCs, peripherals, digital still cameras, and similar devices at rates as high as 4 Mbps and at distances of 1m (as far as 3m at lower speeds).
Housed in an epoxy-resin surface-mount package, the TFDS6000 not only reduces component count, but also takes care of mounting and alignment issues associated with the two electro-optical devices. AGC sets the optical output power and receiver sensitivity to a level that allows communications within a ±15°cone, as required by the standard, and minimizes optical "pollution" and the effect of optical interference. The differential receiving front end rejects interference, amplifying and reshaping the photodiode signal before sending it to an RS-232C port. The only external components the device requires are a current-limiting resistor and a supply bypass capacitor. The 5V device requires 5 mA (typical) in active-receive mode and 35 mA in shutdown mode. $5 (100,000).
To vote for this entrant as Analog IC Product of the Year, mark the appropriate box on the ballot.
Temic Semiconductors
Santa Clara, CA
(408) 567-8220
info@temic.com
A DSP coprocessor module for ARM
mPs,
Piccolo adds a 32-bit DSP instruction set and uses the existing ARM coprocessor
interface for communicating with the ARM processor core. ARM's innovation is the
single memory bus shared by the mP and the Piccolo DSP.
Piccolo's interface includes a tagged input-queue structure and an output FIFO. The input queue, or Reorder Buffer (ROB), enables the ARM mP to preload Piccolo with data before Piccolo requires the data, essentially demultiplexing multiple input data streams for DSP algorithms. The ROB allows ARM code to fetch DSP data or coefficients from memory in the most convenient order and allows the DSP code to consume the items in the required order. Piccolo automatically and transparently refills its registers from the ROB as Piccolo uses and replaces old data. It sequentially returns results to the mP through the output FIFO.
The ARM mP handles all
interrupts and data-address generation. Although the mP operates in
parallel with Piccolo, its performance degrades when the DSP is active, because
Piccolo consumes the mP's bandwidth. In addition, because Piccolo reloads only
from the ROB, a data-intensive algorithm may starve the register file. However,
ARM made this trade-off to achieve a smaller DSP core with minimal power
consumption.
Piccolo's other features include a private instruction cache, four nestable zero-overhead looping constructs, a 16´16-bit single-cycle multiplier, a 32-bit barrel shifter, four 48-bit extended-precision accumulators, and register-based storage for 64 16-bit data items. Piccolo also has a split ALU that provides single-cycle, dual 16-bit arithmetic and logical operations in one instruction word. Pricing for Piccolo is determined by the ARM licensee.
To vote for this entrant as Microprocessor/Controller Product of the Year, mark the appropriate box on the ballot.
Advanced RISC Machines
Los Gatos, CA
(408) 399-5199
www.arm.com
PicoJava I, a processor core that
directly executes Java byte codes, also implements many components of the Java
Virtual Machine (JVM). Sun applied RISC principles to a stack architecture and
included thread-synchronization and garbage-collection support. PicoJava's
primary innovation is the combination of features that the processor requires to
execute the JVM platform.
PicoJava contains a 64-entry stack cache implemented as a circular register file with datapath logic for all 64 entries. PicoJava can forward operands from any two stack elements. Spilling and filling the stack cache from memory occurs in the background and ensures that the stack cache doesn't run dry.
Thread-synchronization support is another innovation on picoJava. The JVM platform supports multiple concurrent execution threads. In addition, thread primitives are integral to Java. As a result, Java programs frequently enter "monitors" associated with objects to ensure that only one execution thread can access the associated object until the thread exits the monitor. The speed of monitor-entry operations is important for overall system performance. PicoJava includes a hardware mechanism that can yield a 40´speed increase compared with the software version that the current Java interpreter implements.
Another innovation is the instruction decoder's ability to detect when the program stores a local variable on a stack, which an instruction immediately uses; the decoder folds the store and use instructions together. Simulations show that folding eliminates as much as 15% of all instructions typically executed on a stack-based machine. Sun expects the pricing for chips based on the picoJava I core to range from less than $20 to $100.
To vote for this entrant as Microprocessor/Controller Product of the Year, mark the appropriate box on the ballot.
Sun Microelectronics
Mountain View, CA
(415) 961-1551
www.sun.com
The SH7708 is a member of
Hitachi's RISC-mC family. The device operates to 100 MHz and has an
8-kbyte, four-way set associative cache. Innovative design techniques allow the
SH-3 to achieve high performance and low power. These techniques are especially
apparent in the on-chip cache, a portion of the mC that accounts for
one-third of the total power dissipation.
The SH-3 uses three cache power-reduction schemes. In one scheme, the cache controller turns on only one of the cache's four data arrays—the one in which an address comparison matches the "way." The comparison followed by data-array read is possible when the address comparison determines a hit or miss before the array starts its operation. This sequence occurs only if the mC is operating at less than 40 MHz; over 40 MHz, the cache controller exits the sequential operating mode and operates the four data arrays in parallel.
In the second scheme, which functions regardless of operating frequency, the mC uses short pulses to drive a cache word line. Circuitry restricts the pulse level to a narrow range between VCC and ground. This pulse-level control requires precise timing for correct sense-amplifier operation. Delay-adjust circuitry, with taps in several places, increases the sense-amplifier's reliability and accuracy. This circuitry allows Hitachi to adjust the timing of the sense amps, precharge, etc.
The third scheme uses column switches on the bit lines between memory cells and the latch-type sense amplifiers, which engage after the column switches turn off. The column switches isolate the parasitic capacitors of bit lines from the active sense amps, which decreases loading on the sense amps. The SH7708 costs $25 (10,000).
To vote for this entrant as Microprocessor/Controller Product of the Year, mark the appropriate box on the ballot.
Hitachi America Ltd
Brisbane, CA
(800) 285-1601, ext 27
www.hitachi.com
The PIC16C9XX family combines
Microchip's PIC core with an innovative implementation of an LCD controller.
Whereas other low-cost LCD controllers rely on a resistor ladder to generate
their LCD voltages, Microchip's LCD design concentrates on a high-current,
switched-capacitor charge pump. This charge pump operates off a 3V supply
voltage. The charge pump uses four external capacitors as part of an analog
sampling circuit that measures system losses and overcharges accordingly.
Specifically, the charge pump can generate as much as three times the supply
voltage, resulting in improved display contrast independent of varying battery
voltages.
The PIC's LCD module supports 32 segments; multiple timing sources; and static, 1/2, 1/3, or 1/4 multiplexing. The multiplexed voltages of the PIC16C9XX's LCD controller must track each other with ±2% tolerance, or the display has ghost images. The controller can even drive an LCD panel while the mC is in its sleep mode.
The first two devices in the PIC16C9XX family are the PIC16C923 and PIC16C924. Both devices run off an 8-MHz clock and contain a 4k´14-bit EPROM, 16 bytes of dedicated LCD RAM, a PWM output, and a synchronous serial port that supports SPI and I2C buses. The PIC16C924 also contains a five-channel, 8-bit ADC. The devices come in 64-lead TQFP and 68-lead PLCC packages. Pricing is $7.09 and $7.84 for the PIC16C923 and PIC16C924, respectively (1000).
To vote for this entrant as Microprocessor/Controller Product of the Year, mark the appropriate box on the ballot.
Microchip Technology Inc
Chandler, AZ
(602) 786-7668
www.mchip.com/microchip
The WavePoint II wireless-LAN
access point offers users both a bridge to connect wireless nodes to a standard
wired LAN, such as Ethernet, and a bridge to the evolving IEEE 802.11 standard
for wireless LANs. You can also use the product to bridge two wireless LAN
channels or to bridge two wired LANs when physical obstacles block traditional
wiring. The product supports peak data rates of 2 Mbps using a direct-sequence
spread-spectrum (DSSS) communication scheme in either the 915-MHz or 2.4-GHz
frequency bands for unlicensed industrial, scientific, and medical (ISM) usage.
The 7´10´2-in. access point includes dual PC Card slots that each can host wireless-LAN radios. The dual-slot approach allows the LAN bridge to work with existing Lucent Technologies WaveLAN nodes and 802.11-compliant nodes when they become available this year. The modular design also allows users to leverage the greater range available with a 915-MHz radio using one slot and the greater available frequency spectrum at 2.5 GHz with the second slot. Alternatively, the two slots allow the user to simply double available bandwidth by co-locating two LAN channels.
The DSSS technology provides superior aggregate throughput, peak data rate, and robustness to noise than frequency-hopping, spread-spectrum products. The bridge supports transparent IEEE 802.1D bridging functions, a spanning-tree protocol that eliminates network loops, and seamless client roaming among multiple wireless bridges. Windows-based LAN-management software simplifies configuration of the WavePoint bridge and remote nodes and provides diagnostic and statistic-gathering facilities. The WavePoint II bridge costs $1295, and PC Card radios cost $695 each.
To vote for this entrant as Computer and Peripheral Product of the Year, mark the appropriate box on the ballot.
Lucent Technologies
Wireless Communications and Networking
Division
Nieuwegein, The Netherlands
(31) 3060-97666
Packing a 240´144-pixel
amber-LED monochrome display into a 28´29´16-mm package, the VirtuoVue weighs just 18g and easily
fits in your shirt pocket or palm. The portable display device includes a lens
with 15-times magnification that, when held adjacent to the eye, provides the
equivalent of an 18-in. CRT viewed at a distance of 5 ft. It can operate from 3
or 5V supplies and consumes less than 40 mW of power. Designers can attach
systems to the display using a standard 28-pin CMOS digital interface.
The VirtuoVue targets "pocket-portable" computing and communication products, including smart phones, portable Web browsers, advanced messaging pagers, smart-card readers, wearable computers, head-mounted displays, closed-caption eyeglasses, e-mail readers, and digital cameras. Suitable for daytime or nighttime usage, the display supports both graphics modes with 16 levels of gray scale and a text mode that produces 14 rows of 40 characters.
The display provides 50,000-times faster switching than competing STN LCDs and uses less power. Design innovations include both a monolithic GaAs-based, amber LED array with 34,560 pixels, and a packaging scheme that bonds the display and two display-driver flip chips directly to a transparent glass substrate. The display device and packaging scheme promise to make the VirtuoVue the first such ultraportable display to be economical when manufactured in high volume. Motorola is quoting prices of $75 (10,000) and $38 (1 million).
To vote for this entrant as Computer and Peripheral Product of the Year, mark the appropriate box on the ballot.
Motorola Semiconductor
Products Sector
Phoenix, AZ
(602) 914-8070
(800) 521-6274
By boosting the platter spin rate
to 10,000 rpm, Seagate Technology has developed, in the Cheetah family, the
fastest disk drives available from both data-transfer-rate and access-time
perspectives. The 3.5-in., 4.5- and 9.1-Gbyte drives feature average seek times
as low as 7.5 msec, due in part to low rotational latency, and data-transfer
rates of 11.3 to 16.8 Mbytes/sec. To complement the high-speed drive assembly,
Seagate offers either an Ultra SCSI interface that can transfer data at 40
Mbytes/sec in wide mode or a dual-port Fibre Channel Arbitrary Loop (FC-AL)
interface that supports a peak data rate of 100 Mbytes/sec per port. The
controllers also use a multisegmented cache to support burst transfers at
interface speed.
The Cheetah design includes several innovations to achieve the fast spin rate. First, the designers sandwiched a unique sound-dampening material into the middle of the top cover—without which the drive would be too noisy for an office environment. The designers also tightened the mechanical drive shrouding in a form-fitting manner to improve airflow control and thereby minimize the effects of heat that the faster spindle motor generates. Moreover, the designers had to develop new bearing and grease combinations to provide reliable operations in the spindle motor. Finally, dual-stripe magnetoresistive heads allow the drive to perform accurately when reading and writing data.
The design innovations resulted in a product that Seagate rates at 1-million power-on hours MTBF, and the company backs the product with a five-year warranty. Such high-end disk drives typically sell for approximately $0.35 per Mbyte (OEM).
To vote for this entrant as Computer and Peripheral Product of the Year, mark the appropriate box on the ballot.
Seagate Technology
Scotts Valley, CA
(408) 438-8111
Digital still cameras may still
be a few years away from replacing traditional cameras, but new devices such as
the Sony DSC-F1 provide several capabilities that simply aren't possible using
traditional film. For example, the camera designers developed multiple recording
modes that maximize creativity. A continuous mode records a sequence of frames
during 1 sec. A time-machine mode records frames before and after the user
presses the shutter button. Finally, a multiscreen mode captures a sequence of
nine frames at 1/30-sec intervals and automatically composes the tiled action
sequence into one picture.
The camera designers also tried to ensure that users had easy access to captured images. The camera can directly display images on the integrated 1.8-in. color LCD or on a TV that connects to the NTSC output. An IrDA-compliant infrared interface or a standard serial interface lets you offload images to a computer. The integrated 4-Mbyte flash memory can store 108 640´480-pixel images. The flash storage and NTSC output also make the camera useable as a portable presentation device.
The DSC-F1 weighs only 10.6 oz and measures 4´3´1.6 in. A Li-ion battery requires less space than more traditional AA alkaline batteries and doesn't suffer from the memory problems that plague other rechargeable batteries. Sony's designers developed a CCD with progressive-scan and square-pixel technology, which allows the camera to produce clear images. The camera sells for $849.99.
To vote for this entrant as Computer and Peripheral Product of the Year, mark the appropriate box on the ballot.
Sony Electronics Inc
San Jose, CA
(408) 432-1600
Without question, SPARC-based
computers offer among the most capable platforms for advanced applications, such
as EDA, but the available SPARC platforms have typically been too expensive for
many other applications, including embedded systems. Sun now offers the
SPARCengine Ultra AX motherboard that includes an UltraSPARC-II processor yet is
designed around the low-cost Intel PC motherboard model. Sun targets the Ultra
AX at Internet Web-server applications, but designers can use the low-cost board
anywhere the performance and robustness of a SPARC processor and Unix might fit.
The Ultra AX features a form factor that fits in standard PC cases, and the board integrates standard PC functions, such as an IDE disk controller, floppy controller, serial and parallel ports, and four PCI slots. The design supports a standard Sun keyboard and mouse or a standard PS-2 keyboard and mouse. The design can host 32 to 512 Mbytes of DRAM and 1 Mbyte of flash ROM.
Despite the PC trappings, the Ultra AX core offers several workstation-level innovations. Two of the four PCI slots are 64 bits wide and can run at 66 MHz in both cases—double the capability of the typical PC implementation. The board uses Sun's Ultra Port Architecture (UPA) to connect the processor, memory, and I/O. UPA supports data rates to and from the processor at 300 Mbytes/sec. Together, UPA and the fast PCI implementation can support applications such as emerging 622-Mbps asynchronous-transfer-mode cards. Sun also offers proprietary graphics and imaging cards, although standard PCI cards also work. The board runs any Sun-supported operating system. A 167-MHz version costs $2900 (1000), and a 250-MHz version costs $4900 (1000).
To vote for this entrant as Computer and Peripheral Product of the Year, mark the appropriate box on the ballot.
Sun Microsystems
Mountain View, CA
(415) 960-1300
Custom ASICs help SuperTAP
provide all the functions of a traditional high-end emulator in a module that
fits in your pocket. The module replaces the CPU in the target system, then
communicates to a host controller over an RS-232C, high-speed serial, or
Ethernet link. The host, running the CAD-UL XDB debugger, displays trace data
and controls the emulator's operation.
SuperTAP provides real-time emulation at clock speeds to 33 MHz, traces code execution with a 64k-sample buffer offering time stamps, and provides overlay memory in 4k blocks for the target system. Because SuperTAP has its own communications path to the host system, it does not use any target-system resources. The device also has a secondary processor to handle emulation tasks, so a target-system crash doesn't kill emulation or trace activity. Similarly, trace triggering, capture, and upload to the host don't stop target-system operation.
The device's trace operation captures CPU address, data, and status fields and provides a time stamp accurate to 25 nsec. SuperTAP can prequalify trace information and can use external signals to qualify data. The system displays executed code as raw bus cycles, assembly code, or C-source with symbols. Users can search the trace buffer for bus cycles matching any combination of address, data, and status bits. Trace triggering includes 16 comparators, four trigger levels with forward and backward branching, and eight active bus events to capture obscure or intermittent problems. Prices start at $13,495 for an Intel 386EX emulator.
To vote for this entrant as Embedded Development Product of the Year, mark the appropriate box on the ballot.
Applied Microsystems Corp
Redmond, WA
(206) 882-2000
A compiler and debugger are only
the beginning of the pRISM+ software-development system. The system also
includes software performance analysis, project-management tools, and an
industry-standard framework for adding on third-party tools. The system allows
tool-to-tool and tool-to-target communications over local- and wide-area
networks, allowing a project to readily move from a single workstation to a
distributed network.
The pRISM+ system is built around an object bus conforming to the CORBA (Common Object Request Broker Architecture) standard. CORBA is middleware that enables programs to interact in a heterogeneous environment. Tools conforming to CORBA can exchange data and control information, even if the tools are not designed to work together. The object-request broker lets tools determine each other's assets and attributes and provides a common format for intercommunicating.
As a result of using CORBA, pRISM+ lets developers readily add third-party tools to the system. The added tools then share pRISM+'s user interface and target-system connection. In addition, the tools can access data collected by other tools in the system. Yet the tools remain distinct and separate, allowing them to operate even if distributed across a network.
A variety of tools come with pRISM+. Diab Data provides C/C++ compilers, assemblers, linkers, and libraries. TakeFive Software contributes project-management and analysis tools and native-environment code browsers. ISI includes a pSOS-aware debugger. Pricing for pRISM+ starts at $7500. The system is available for 68K, MIPS, i960, PowerPC, and x86 processors, and ColdFire and ARM will follow.
To vote for this entrant as Embedded Development Product of the Year, mark the appropriate box on the ballot.
Integrated Systems Inc
Sunnyvale, CA
(408) 542-1500
The QNX/Neutrino real-time
operating system brings the Posix application-programming interface (API) to
embedded systems. Neutrino provides Posix real-time APIs and threads APIs, with
the exception of processes, in 32 kbytes of code. An optional 32-kbyte process
manager extends Neutrino to include processes, memory protection, and
pathname-space management. Runtime licenses cost <$40.
To achieve this small size, Neutrino uses the microkernel approach. The microkernel itself is a collection of routines that manipulates a set of common objects from which all abstractions needed to build the API derive. OS services come in software modules that behave like application programs. When the application software needs an OS service, the application calls the microkernel, which passes the message to the service module for execution. This approach also allows extension of the OS to include services such as filesystems and networking by simply adding software modules. Such extensions do not affect application code.
This flexibility extends to memory protection. Because OS services look like application programs to the microkernel, changing memory-protection levels requires only a change to the program's build file. Thus, user code running on a processor with a memory management unit (MMU) can run unchanged on a processor without an MMU.
By bringing the Posix API to embedded systems, Neutrino enables designers to work with an industry-standard API. This option, in turn, allows designers to use third-party source code to build their applications. The result is faster development time and fewer bugs. The reused software has already been tested and debugged.
To vote for this entrant as Embedded Development Product of the Year, mark the appropriate box on the ballot.
QNX Software Systems Ltd
Kanata, ON, Canada
(613) 591-0931
For many designers of
high-performance digital pc boards, the Hewlett-Packard MultiProbe system ends
the nightmare of trying to acquire true pictures of waveshapes on the pins of
high-pin-count ICs. Not only do the ICs have hundreds of pins, but pc boards
also usually contain several such devices. The devices can have pin spacing that
is almost invisible—as small as 0.5 mm. Getting an undistorted picture also
requires making a reliable connection to a ground pin located as close as
possible to the signal pin. In addition, when you start debugging, you can't
predict which signals might hold the key to an elusive problem.
HP's MultiProbe system eases these problems by simultaneously contacting as many as 960 pins and connecting any pair of signals to your scope's inputs without moving a probe. The probing system also eliminates the need to note signal names on captured-waveform printouts. In addition, the system extends the benefits of active probing to points only a few millimeters from the signal pins.
A control module for one to four pods costs $5000. A pod with an adapter kit for 240-pin PQFPs costs $5500. A pod with an adapter kit for either 160- or 208-pin PQFPs costs $4700. A nine-channel flying-lead pod costs $3700.
To vote for this entrant as Test and Measurement Product of the Year, mark the appropriate box on the ballot.
Hewlett-Packard Co
Colorado Springs, CO
(800) 452-4844
The patented TruTrace feature of
Gould Instrument Systems' four-channel, 200-MHz-bandwidth Classic 6000 DSO
($6195) is the latest in the trend toward making digital scopes emulate analog
scopes. TruTrace, which adds a third dimension to the DSO display in both
single-shot and repetitive-sampling modes, does its job without affecting the
way the scope captures waveforms. TruTrace faithfully emulates an analog scope's
z-axis or intensity modulation. Gould's approach is not just a way of
distinguishing infrequently occurring anomalies from normal waveforms, but also
of revealing details in long waveform records that a DSO's minimum/maximum or
peak-detection mode normally renders invisible. To achieve its computational
power, TruTrace uses a Texas Instruments TMS320C40 DSP.
To present more information than would normally be possible without horizontally expanding the display, the scope constructs a histogram of the frequency of each y-axis value. It quantizes this histogram into eight levels and intensity-modulates the display accordingly. The result is an effective emulation of the z-axis modulation of analog-scope displays. Unlike other schemes for providing z-axis information in DSO displays (color grading, for example), TruTrace even works with single-shot data.
To vote for this entrant as Test and Measurement Product of the Year, mark the appropriate box on the ballot.
Gould Instrument Systems
Inc
Valley View, OH
(216) 328-7000
HP's 54645A and D DSOs aim at
engineers who build systems around 8-bit microcontrollers, including designers
of electromechanical and medical systems. An unusual feature in DSOs in this
price range is a capture memory of 1M samples/channel. Most scopes with such
deep memories cost more than $10,000. Both the $3495 54645A and the $4995 54645D
have two analog channels with 100-MHz bandwidth and a maximum real-time sampling
rate of 200M samples/sec. In addition, the 54645D includes a 16-channel
logic-timing analyzer that also captures 1M samples/channel. When you use all 16
channels, the timing analyzer's maximum capture rate is 100M
samples/sec/channel. If you use only eight channels, the capture rate and
per-channel memory double.
Because of the MegaZoom multiprocessor architecture, the two DSOs avoid the noticeable delay that typically occurs between changes in front-panel settings and the resulting changes in the display. A similar lag occurs when the signal changes. With the HP scopes, the delay is imperceptible. As with HP's earlier 54620 units, which perform only logic-timing analysis, the 54645D emphasizes the requirements of people who don't use a logic analyzer every day. You select trigger conditions by using a straightforward menu system. And, you can use logic patterns to trigger analog acquisitions.
To vote for this entrant as Test and Measurement Product of the Year, mark the appropriate box on the ballot.
Hewlett-Packard Co
Loveland, CO
(800) 452-4844
The TDS 210 (60-MHz bandwidth)
and TDS 220 (100 MHz) from Tektronix give back 75% of the bench space that your
DSO has been occupying. To do this, these products replace the CRT with a
bright, high-contrast, back-lit LCD diagonally measuring approximately 6 in. The
resulting package has a front panel that, at 6?12 in., is slightly smaller than
the panels of conventional scopes. The new scopes are only 41/3 in. deep,
however. They weigh just 4.25 lb, and they offer some of the industry's lowest
DSO prices: $995 for the TDS 210 and $1695 for the TDS 220. Each is a
two-channel unit that samples both channels simultaneously in real time at 1G
samples/sec/channel.
Handheld LCD DSOs are even smaller and offer other advantages, such as battery power. Although handheld scopes have proven successful in field service and maintenance, Tek believes that design engineers demand scopes designed for the benchtop. To save space, nearly all handheld DSOs substitute unfamiliar pushbuttons for benchtop scopes' standard rotary controls. Unlike handheld units, the TDS 210 and 220 use a familiar control layout. A plug-in accessory adds printer, RS-232C, and IEEE-488 ports. Because battery power is rarely a requirement on the benchtop, but external power supplies can be a nuisance, the new scopes are ac-line-operated (90 to 250V, 47 to 63 Hz), and their supplies are internal.
To vote for this entrant as Test and Measurement Product of the Year, mark the appropriate box on the ballot.
Tektronix Inc
Beaverton, OR
(800) 479-4490
Fluke's handheld models 163
(160-MHz) and 164 (1.3-GHz) counter/ timers include high-contrast, back-lit,
50-MHz-bandwidth waveform displays that let you see what you're measuring.
Despite their appearance and size, which is identical to that of Fluke's
ScopeMeter LCD DMM/DSOs, the units are counters, not scopes.
The waveform-sampling technique differs from that of a DSO. Instead of measuring voltages at known points in time, the units determine the points when the waveform voltage equals a set of known values. When you're gathering time-related information, this approach can more quickly, easily, and precisely get you the data you seek than a scope can—even one that costs an order of magnitude more and that is much bigger and heavier. The waveform display indicates the trigger points and the hysteresis band of the counter's trigger circuit.
The units, which you control via a menu-driven user interface, can operate from alkaline C cells as well as from the provided NiCd cells. The NiCd cells fully recharge in two hours inside the instrument. The 163's price begins at $1495; the 164 begins at $1895. Besides the 1.3-GHz range, the 164 includes an optically isolated RS-232C port, statistical and mathematical functions, and burst-measurement capability. Both units automatically measure phase shift between signals on two inputs and measure pulse parameters, such as width, period, duty cycle, rise time, and fall time.
To vote for this entrant as Test and Measurement Product of the Year, mark the appropriate box on the ballot.
Fluke Corp
Everett, WA
(800) 443-5853
A line of LEDs uses a combination
of high-brightness material and optical mechanisms that make these lamps ideal
for outdoor applications. Aluminum indium gallium phosphide (AlInGaP) material
gives the LEDs high luminous output and enhanced readability in sunlight.
According to the manufacturer, the uniformity of three features—color,
brightness, and radiation pattern—is crucial for light sources in traffic
signs and signals, for example. LEDs in outdoor signals use only about 20% of
the power of incandescent lamps, and last six to 10 times as long. The LEDs use
special optical-lens structures that allow precise control of light output,
thereby ensuring that the letters and symbols in message panels appear
consistently sharp and bright over the specified viewing angle.
The optical-grade epoxy used in the LEDs' four package options contains ultraviolet-A and -B inhibitors that reduce the effects of long-term exposure to direct sunlight. The lamps are available with viewing angles of 8°, 15°, 23°, and 30°, based on off-axis intensity equal to half the axial intensity. They are available in four colors: amber (590 nm), Portland orange (605 nm), reddish-orange (615 nm), and red (626 nm). Luminous efficacies are 480, 370, 263, and 150 lm/W, respectively. The LEDs come in untinted, nondiffused T-13/4 packages that use second-generation optics to produce well-defined, spatial-radiation patterns at specific viewing-cone angles. In million-piece lots, the LEDs cost approximately $0.30.
To vote for this entrant as Component, Hardware, and Interconnect Product of the Year, mark the appropriate box on the ballot.
Hewlett-Packard Co
Santa Clara, CA
(800) 537-7715, ext
2124
The Polar Cap Series of heat
sinks provides highly efficient cooling of semiconductors mounted to the sink's
cooling surface. A self-contained fan pushes high-velocity air over augmented
fin surfaces to remove accumulated heat. The position of the fan mounted to the
fins impinges air on the back surface of the heat sink to provide increased
cooling. The impingement cooling increases air turbulence and removes more heat
than conventional cooling methods. The augmented fin surfaces disrupt the air
boundary layers on the fin surfaces, thereby increasing heat transfer. The
manufacturer claims the Polar Cap uses a more efficient cross-cut extrusion
profile than that of similar heat-sink designs, and thus yields greater heat
removal per cubic inch.
Typical applications for Polar Cap heat sinks are in motor controls, power supplies, and telecommunications equipment. The sinks are useful for cooling thermoelectric modules, IGBTs, and other power semiconductors. The units come in 119-mm models with lengths of 122.9, 180.9, and 248.4 mm, and thermal resistances of 0.117, 0.084, and 0.068°C/W, respectively. 172-mm models with lengths of 176.2 and 263.1 mm provide thermal resistances of 0.055 and 0.038°C/W, respectively. In addition to these standard models, you can obtain customized sinks, with tailored fin height, spacing, and overall length and width, to suit specific applications. Customized mounting-surface configurations are also available. Prices for standard models range from $44 to $98 (500).
To vote for this entrant as Component, Hardware, and Interconnect Product of the Year, mark the appropriate box on the ballot.
Aavid Thermal Technologies
Laconia, NH
(603) 528-3400
The PressOn is an adapter for
interfacing test and measurement equipment, such as in-circuit emulators (ICEs)
and logic analyzers, with high-density, flat-package ICs. The adapter uses
multiple vertically aligned conductive strips housed in silicone-rubber contact
blocks. It attaches to the IC via a threaded bolt that's temporarily glued to
the top of the IC. Alternative adaptation techniques use metallic contacts,
clipped over the flat-pack IC and held in place by spring force. With this
technique, the spring force of the clip-over adapter quickly decreases over
time, resulting in open connections. Clip-over adapters are also susceptible to
misalignment by the operator. Another technique, widely advocated by ICE
suppliers, uses a socket adapter in the board in place of the CPU. Although this
method eases adaptation to the test equipment, it introduces additional
production, alignment, and timing problems into the debugging setup.
The PressOn adapter requires only 1 to 2 mm of space around the IC, a critical dimension on high-density boards. Its conductive strips can have a pitch as narrow as 0.4 mm, compared with the 0.6-mm limit with clip-on technology. The bolt-and-nut attachment technique ensures high contact reliability by exerting constant contact pressure. The method also eliminates the possibility of accidentally knocking the adapter off the target IC—in fact, you can lift the target board by the adapter. PressOn technology is not new; similar products exist in the flat-panel-display industry. However, application to the embedded-systems industry is unique. The adapters cost $1950 each for 144-, 176-, and 208-pin versions.
To vote for this entrant as Component, Hardware, and Interconnect Product of the Year, mark the appropriate box on the ballot.
Kontron Elektronik
Newport Beach, CA
(714) 851-1872
The 266 EMILM laser module
increases the capacity of current lightwave-communications systems eightfold.
The module uses an electroabsorption-modulated, isolated laser. Current
long-haul systems can send as many as 50,000 simultaneous conversations on a
pair of optical fibers as long as 200 km before the need for signal regeneration
arises. Systems based on the 266 EMILM can transmit 400,000 conversations as far
as 600 km without regeneration. The module can transmit 2.5 Gbps over each of
eight wavelengths, for a total of 20 Gbps. In existing long-haul systems, a
device turns the laser on and off, like a light switch, creating binary ones and
zeros. The 266's modulator is integrated with the laser in a package the size of
a toothbrush head. It modulates the laser with an action similar to that of a
camera shutter.
The integrated design yields several benefits: low levels of chirp, allowing the module to triple the capacity of current laser configurations; low signal dispersion, hence greater distance; a small footprint, taking only one-fifth the space needed for a laser/external-modulator system; and low cooling and power requirements. The 266 uses a 1.5-mm laser that's available for 38 ITU-T wavelength standards in the 1550-nm band. Its package contains a thermoelectric cooler, thermistor, backfacet monitor, and optical isolator. Modules are available for 360- and 600-km operation. Unit prices range from $6900 to $8600.
To vote for this entrant as Component, Hardware, and Interconnect Product of the Year, mark the appropriate box on the ballot.
Lucent Technologies
Optoelectronics Products Unit
Breinigsville, PA
(610) 391-2524
Versa-Pac products are six-winding, surface-mount devices that satisfy hundreds of transformer and inductor requirements. Each device provides tightly coupled windings with the same number of turns on each winding. The family offers more than 500 transformer or inductor configurations from 25 standard off-the-shelf devices that come in five low-profile sizes. Their versatility stems from configuring different windings in parallel or series connections or both, a concept the manufacturer dubs pin-configurable magnetics (PCM). The windings use multifilar wire, which improves cross regulation by enhancing voltage coupling and also reduces voltage spiking caused by leakage inductance. The devices are appropriate for prototyping and for moderate-volume production runs.
You can configure each Versa-Pac in at least six combinations for inductor use, or in at least 15 turns ratios for transformer applications. For example, if you connect six windings in series, you obtain 36 times the base inductance. You can also connect windings in parallel to increase current rating. For example, six parallel-connected windings in the Versa-Pac VP5-0083 provide the base inductance and 12.5A current-handling capability without saturation. The devices come in five sizes to accommodate saturation currents from 60 mA to 4.59A; base inductance ranges from 3.2 to 89.6 mH. The Versa-Pac family specs a power range from 1 to 70W, with operating frequencies to more than 1 MHz. Prices range from $1.50 to $2 (25,000); an engineering design kit is available for $99.
To vote for this entrant as Component, Hardware, and Interconnect Product of the Year, mark the appropriate box on the ballot.
Coiltronics Inc
Boca Raton, FL
(561) 241-7876
The EL7560C is a synchronous
dc/dc switcher IC that integrates PWM control logic with two 12.4A
continuous-rated power MOSFETs in a 28-pin SOIC. The internal-MOSFET design
eliminates the need for the lossy (as high as 1W) current-sense resistor used in
external-MOSFET designs. The internal-MOSFET design also reduces EMI, because it
eliminates the need for high-slew-rate, MOSFET gate-drive signals on the pc
board. The EL7560C complies with the Intel Pentium Pro four-bit handshake that
defines 15 programmable voltages from 2.1 to 3.5V. The power SOIC for the
converter has an exposed heat slug that presents a low thermal resistance to the
internal die. The device is rated at 12.4A continuous with 100-linear-ft/minute
airflow and a heat sink.
Internal protection circuits
include soft-start to protect the CPU against initial power-on transients,
overtemperature protection that uses an on-chip silicon temperature sensor,
overvoltage protection that turns off the output when the output voltage is
excessive, and a power-good output that indicates if the CPU voltage is within
normal operating limits. You can set the switcher's operating frequency (as high
as 1 MHz) by choosing an external capacitor. You can also synchronize the
switching with an external frequency source. A user-adjustable
slope-compensation capability optimizes loop response and noise immunity and
eliminates subharmonic oscillation. The EL7560C costs $10.67 (1000).
To vote for this entrant as Power Source Product of the Year, mark the appropriate box on the ballot.
Elantec Inc
Milpitas, CA
(408) 945-1323
Designed for backing up bridges, routers, gateways, and entry-level servers, the ESV5 uninterruptible power supply (UPS) uses a proprietary design that reduces product size and weight by 50% compared with traditional UPSs, according to its manufacturer. The ESV5 uses a high-frequency switching technology derived from sophisticated online UPS models. For a print server, it provides power protection for as long as 45 minutes. For a typical CAD workstation, backup time is as long as 10 minutes. You can use the UPS to protect five to 10 users in a Windows NT system.
The ESV5 comes equipped with a SolutionPac CD-ROM, which contains a complete set of UPS-administration applications. The ROM provides the connection and supervision of ESV products on local- or wide-area networks and multiplatform systems. It contains all the software modules you use for local or remote administration in a variety of systems, such as Novell NetWare, Windows NT, OS/2, and Unix. The UPS also features PowerShare switchable sockets, which allow independent control of each element of a stack. Using PowerShare, a PC or network-administration station can reset faulty devices, assign different battery runtimes, sequence start-ups, and monitor the power status of protected devices. The ESV5 also contains a control panel that incorporates an eight-level bar graph that displays battery-charge level, load level, and the activation of the PowerShare mode. Windows 3.1 and 95 driver software comes standard with the $349 ESV5.
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MGE UPS Systems
Costa Mesa, CA
(714) 557-1636
The LM2825N is the industry's
first step-down, or buck, dc/dc converter that integrates all the usual external
components into a single 24-pin, industry-standard package, according to the
manufacturer. A member of the Simple Switcher family, the 1A device converts
poorly regulated voltages as high as 40V to well-regulated 3.3 or 12V levels.
The LM2825N attaches all power devices—active and passive—directly to
a lead frame without using a ceramic substrate. The lead frame is 15 mils thick,
compared with the usual 9 mils for most 24-pin packages. The converter offers a
standby mode with quiescent current typically 65 mA. Typical
operating quiescent current is 5 mA. Efficiency is typically 80%, with ±4%
output-voltage tolerance.
Extended life testing reveals an
MTBF exceeding 20 million hours. Radiated EMI meets the CISPR 22 standard, Class
B. The radiated emissions in the frequency bands of 30 to 230 MHz, 230 to 1000
MHz, and 1 to 10 GHz are within 30, 37, and 46 dBmV/m, respectively.
Line regulation, with input voltages from 4.75 to 40V, is typically 1.5 mV. Load
regulation, with load currents from 0.1 to 1A, is typically 8 mV. Output ripple
voltage is typically 40 mV p-p. The converter operates over a
junction-temperature range of 0 to 125°C. The LM2825N operates with a 150-kHz switching
frequency and costs $8.55 (1000).
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National Semiconductor Corp
Santa Clara, CA
(800) 272-9959
The SP4422A generates a
high-voltage (to 200V p-p) ac signal from a 1.5 to 6V low-voltage supply. The
device is suitable for generating the high-voltage input to electroluminescent
(EL) lamps in handheld, battery-operated systems. Alternative approaches to
driving EL lamps entail the use of a transformer, transistors, and several
resistors and capacitors. The resulting circuitry is large, bulky, and
unsuitable for handheld applications. The SP4422A is a monolithic IC that uses
an external inductor and capacitor. A generator using the SP4422A comprises
three major circuit blocks: an oscillator, an external inductor, and a switched
H-bridge network. The oscillator provides an onboard clock source to control the
charging and discharging phases of the coil and lamp.
The external coil stores energy and then releases that energy into the SP4422A. When the circuit releases the energy into the H-bridge (which comprises two SCR structures), the H-bridge produces a high-voltage spike that triggers the SCR switches. The H-bridge creates 16 voltage steps from ground to 100V on pins 4 and 5, which are 180°out of phase with each other. The result is lamp-drive voltage of typically 180V, at a frequency of approximately 256 Hz. The switcher's on-chip oscillator operates at approximately 64 kHz. You can override the on-chip oscillator by removing the external capacitor and connecting an external clock source. An external clock signal may be desirable to synchronize any parasitic switching noise with the system clock. The SP4422A costs $1.05 (25,000).
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Sipex Corp
Billerica, MA
(508) 667-8700
The memBIST-XT memory controller
generates built-in self-test (BIST) for discrete multichip-module (MCM) and
board-based memory chips. For these chips, memBIST-XT generates test data and
expected responses and captures and compares actual responses. Using about 1000
logic gates, the software embeds a controller into an ASIC or FPGA chip that
interfaces with the memory. You control memBIST-XT either through pins on the
ASIC or FPGA where the BIST logic resides or from a pc board's IEEE
1149.1-compliant, test-access-port controller. The BIST controller runs at full
system speed, allowing you to test memory at speed. Along with control logic,
memBIST-XT produces a BIST "collar," an interface between the
controller and external memories. The collar includes multiplexer logic for
switching between functional and control signals.
The memBIST-XT controller lets you input design information about the memory cluster you want to test and then automatically generates the BIST controller in Verilog or VHDL. You also get the HDL synthesis script, which the software appends to the synthesis script for the chip with the controller logic. In addition, memBIST-XT gives you a test bench to verify the functionality of the generated BIST controller and collar.
The product implements several variations of the "marching-pattern" test pattern, with user-programmable read- and write-access sequences. You can test for stuck-at faults, shorts and coupling faults for bit lines, data buses, and address lines. The controller also tests for some cell-based problems. The controller supports any read/write memory type, including SRAMs, DRAMs and SDRAMs, and can program waveforms for any memory-access type, such as fast page mode. License fees start at $20,000/design for the first three designs.
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LogicVision Inc
San Jose, CA
(408) 453-0146
Fire & Ice, for parameter
extraction, and Thunder & Lightning, for parasitic analysis, perform
full-chip, 3-D extraction on 4-million-transistor circuits in 24 hours. Dynamic
power verification and signal compliance take another 10 hours per 100 test
vectors on the same chip. Fire & Ice hierarchically extracts transistor and
RC parasitics from a GDS-II layout file. Using a built-in model-generation
process, Fire & Ice adaptively uses the models to determine parasitic
capacitance during extraction. The tool calculates interconnect capacitance,
including lumped, coupled, and distributed, and measures resistance to within 5
to 10% that of measured silicon or that calculated by Poisson field solvers.
Fire & Ice extracts area, lateral, and fringing capacitance in the presence
of multiple surrounding bodies, increasing the accuracy of signal-coupling
information. In addition, Fire & Ice stripes the chip layout and runs the
stripes on separate CPUs, letting you use the tool on large chip designs.
Thunder & Lightning provides power-grid, clock-tree and signal-integrity verification, performing dynamic analysis of multimillion-transistor chips. The tool uses vectors from a Verilog file to determine active power dissipation. Thunder & Lightning also supplies power-grid verification, including IR drop for supply-voltage degradation and current density for potential electromigration or power/ground-bounce problems. With Fire & Ice, Thunder & Lightning checks signal clock-skew compliance, coupling noise, and reliability analysis. Compliance testing includes rise and fall slew rates, signal glitches, setup-and-hold violations, and other signal-integrity problems. Thunder & Lightning and Fire & Ice cost $150,000 each.
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Simplex Solutions Inc
San Jose, CA
(408) 432-8260
QuickChange lets you
interactively specify multiple parameters for DSP functions implemented in
Atmel's dynamically reconfigurable FPGAs. Before QuickChange, the only way to
implement designs with in-circuit reconfigurable FPGAs was to do a new design
for every change. With QuickChange, you interactively specify as many DSP
parameter changes as you want with one design. With a reconfigurable FPGA, you
can use a single chip to perform different system functions or functions with
varying parameter values that change during system operation. You can also save
I/O pins, allowing you to use a smaller FPGA for some applications. Quick-Change
lets you save design time when designing systems with reconfigurable FPGAs.
After completing the design with an initial parameter set, you invoke QuickChange from Atmel's design environment. The FPGA represents changeable parameters, such as FIR- and IIR-filter taps, edge detectors, rotators, pulse-width modulators, and crosspoint switches, in binary notation. QuickChange locates, groups, and displays these parameters. You then specify any changes, and QuickChange generates the FPGA logic stream for each new parameter. Atmel's AT6000 FPGA devices store the logic stream and then retrieve and load it during system operation in response to processor instructions. Quick-Change can use the output of DSP design tools like Mentor's (Wilsonville, OR) DSP Station, Synopsys' (Mountain View, CA) COSSAP, or Alta Group's (Sunnyvale, CA) SPW. Prices start at $995.
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Atmel Corp
San Jose, CA
(408) 441-0311
Aquarius-XO is a timing-driven
layout tool for cell-based chips using as many as six layers of metal
interconnect. Tightly integrated with synthesis tools from Synopsys (Mountain
View, CA), the tool lets you simultaneously choose the best timing, wire length,
and wire congestion, reducing both chip size and total wire delay. Aquarius-XO
uses a proprietary timing-driven placement algorithm to consider all-path timing
constraints and routability for a chip. Place and route tools usually serially
perform placement, global routing, and detailed routing as separate operations.
Aquarius-XO, however, pipelines the operations to provide denser placement and
faster routing convergence. After completing global routing, the tool does
automatic 2-D compaction, preserving critical preroute patterns, such as
clock-distribution networks and power and ground lines.
Aquarius-XO uses a unique slack-graph representation that captures both timing and con-nectivity information. Avant! developed an optimization procedure that globally considers slack, sensitivity of path delay to path length, and connectivity. The procedure, based on a snapshot of current layout during place and route, suggests a minimum perturbation of the current layout to improve timing. Aquarius' slack-graph and layout optimizers alternately guide global optimization, leading to an optimal trade-off between timing and layout. The tool also has a progressive look-ahead placement and routing algorithm that produces a die size an average of 10 to 15% smaller than you get from competing place and route tools. Pricing starts at $275,000.
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Avant! Corp
Sunnyvale, CA
(408) 738-8881
Circuit Envelope lets you analyze
complex modulated-RF signals. By incorporating both time- and frequency-domain
techniques, the software overcomes some of the limitations of simulators
operating in only one domain. The runtime and memory efficiencies of Circuit
Envelope's simulation are much better than those of a time-domain simulator,
such as Spice, or a frequency-domain analysis, such as harmonic balance. Spice
uses time steps based on the RF carrier or its harmonics. Modulation bandwidth,
which is much narrower than that of the frequency carrier, dictates the time
steps required by Circuit Envelope. The narrower bandwidth results in fewer time
steps and faster runtime. Harmonic balance, a frequency-domain simulation
technique, works best for steady-state simulations. This technique needs large
amounts of memory and time to simulate digitally modulated waveforms because it
uses a sum of Fourier harmonics to represent the modulated signal.
Circuit Envelope handles a signal's amplitude and phase-modulation information in the time domain and the RF carrier and its harmonics in the frequency domain. The tool's improved runtime and memory efficiency let you simulate complex waveforms, such as those in CDMA, FSK and Pi/4DQPSK circuits. Unlike Spice, with Circuit Envelope you can output a signal's instantaneous amplitude and phase information, which is useful for analyses such as ringing severity when you vary the frequency of an oscillator. In addition, whereas Spice relies on lumped-element approximations, Circuit Envelope can also include frequency-domain models, such as s-parameter data, for more accurate simulations. Circuit Envelope costs $18,000/unit.
To vote for this entrant as EDA Product of the Year, mark the appropriate box on the ballot.
Hewlett-Packard
HP-EEsof Division
Westlake Village, CA
(818) 879-6440
The Verilog Model Compiler (VMC)
compiles a Verilog source-code model of a core, ASIC, or IC into a binary model
or object file. Although you cannot decipher or reverse-engineer it, the binary
model supports accurate simulations on a Verilog simulator. VMC thus protects
the model's proprietary design and also the core or chip vendor's intellectual
property. VMC optimizes models for fast simulation speed and low
simulator-platform memory requirements. Silicon vendors can distribute VMC
models to their customers before silicon is available, letting designers begin
chip designs earlier and reducing design-cycle times. Vendors can make models
available in days using VMC vs taking six to eight months to create a C-based
model from a chip specification. VMC-generated models run on any simulator
supporting Verilog PLI, including Viewlogic's VCS and Cadence's (San Jose, CA)
Verilog-XL.
VMC offers intellectual-property protection advantages that are unavailable with encryption, chip specifications (instead of a model), or nondisclosure agreements. Although encryption protects a source-code model, there are no current foolproof encryption methods. Giving designers chip specifications instead of a model protects intellectual property, but HDL models are more accurate than models generated from specifications. If you find a bug, it may be difficult to determine whether the bug was in the original design or in a model generated from chip specifications. Finally, non-disclosure agreements offer legal, not technical, protection of intellectual property, and obtaining them is often time-consuming. A VMC floating license costs $100,000, and the upgrade costs $60,000 if you already have a VCS floating license.
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Viewlogic Systems
Marlborough, MA
(508) 480-0881
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