Design Features February 17, 1997

The ever-evolving VMEbus adapts to user needs

Richard A Quinnell, Technical Editor

The VMEbus is still going strong 15 years after its introduction. Its secret: continued evolution to match changing user demands while maintaining backward compatibility. The latest evolutionary step, VME64x, will take place this year.

  The bus wars of the early '90s have ended. Multibus is languishing, Futurebus is a thing of the past, but the VMEbus is thriving. A major component of VMEbus's victory is its adaptability to changing application demands. The VMEbus has added numerous enhancements to its standard and doubled its top data rate while retaining compatibility between versions. More improvements are on their way with the VME64 extensions doubling data rates again and paving the way for hot-swap capability.

  The VMEbus's adaptations rest on a solid foundation. The basic bus employs a Eurocard-format circuit board with pin-and-socket connectors between board and bus backplane to meet the needs of harsh industrial applications. The connectors offer better reliability, more corrosion resistance, and more vibration resistance than card-edge connectors. The Eurocard format offers designers a choice of larger boards for more component area or smaller boards for more mechanical stiffness. A single backplane can handle as many as 21 boards.

  The system's architecture is as solid as its mechanics. The basic bus provides a master/slave relationship between boards, with asynchronous data transfers based on a four-edge interlocked handshake. This architecture allows boards of differing speeds to communicate across the bus at a maximum data rate of 40 Mbytes/sec. A centralized arbitration scheme, with the arbiter always in bus slot 1, lets the VMEbus support multiprocessing designs.

  Equal in importance to the bus structure is the VMEbus's wide acceptance. A host of suppliers provides an overwhelming array of board types, with new designs constantly arriving. This huge base of options allows designers to create systems entirely from standard products. Users can combine diverse VMEbus boards in a cage without significant compatibility problems, thanks to standardized VMEbus-interface ICs from companies such as Cypress Semiconductor and Tundra. These ICs also ease designing a VMEbus board for users needing custom capabilities. With the bus interface captured in standard silicon, users can focus custom-design efforts on the board's function, not on the VMEbus. Table 1 (pg 94) provides only a representative sample of VMEbus vendors. The VMEbus International Trade Association (VITA) lists more than 120 members on its Web site, www.vita.com.

  Supporting this vast source of VMEbus products has been a guiding principle of the VITA Standards Organization's (VSO) activities. VSO, which manages changes to the VMEbus standard, has ensured that changes to the standard maintain backward compatibility. A VMEbus board designed in the early '80s can work in the most recent VME64 backplane. Further, most new boards can work in 15-year-old systems, although some of the boards' newer features may be unavailable.

  A large installed base of compatible devices and numerous suppliers doesn't keep an architecture alive, however, without some migration path for technical upgrades. One such path built into the VMEbus specification lies hidden in the P2 connector for 6U VMEbus boards. The VMEbus specification reserves 64 pins in the P2 connector for users to define as they choose. These pins are not bused together on the backplane. Many users choose to use these pins to implement private side buses for data transfer, augmenting the general-purpose VMEbus with a special-purpose sub-bus.

  The use of sub-buses on the P2 connector has become popular enough that several such sub-buses have acquired the status of standards. For example, released standards cover both the VME Subsystem Bus (VSB) and Mercury Computer's Raceway Interlink. Sky Computer's SkyChannel is nearing completion of standards balloting. Each meets a different set of data needs.

  The VSB provides a second general-purpose 32-bit address and data bus for VMEbus cards. The sub-bus offers a single interrupt, single-level bus arbitration, and dynamic bus sizing. It performs address-only, block-transfer, and read-modify-write bus transactions at 40 Mbytes/sec. The sub-bus's speed requires use of a pc backplane, which can be a piggyback board pressed onto a standard VME backplane's pins. The IEEE/ANSI Standard 1096-1988 covers VSB.

  The high-speed Raceway Interlink data bus uses a backplane-mounted crossbar switch for data routing rather than busing all signals to all cards. Raceway-enabled cards connect through the P2 user pins to the crossbar switch, which allows several sets of boards to communicate simultaneously. Each channel through the switch can handle data at 160 Mbytes/sec.

  The total additional bandwidth that Raceway Interlink makes available to the VMEbus grows as users add channels. The number of channels available, in turn, depends on the switch's configuration. A basic setup connects four boards through a six-port crossbar, allowing three simultaneous channels. An eight-board, six-crossbar configuration is also available.

  A third sub-bus, SkyChannel, is nearing completion of its standardization efforts (see box, "Understanding standardization") and is scheduled for approval in May. The 64-bit-wide, 320-Mbyte/sec SkyChannel data bus uses a packet-switching structure. By combining a destination header with the data stream, SkyChannel avoids multistep negotiations to set up a data transfer; recipients simply take their data off the bus when sent. Packet switching's reduced overhead improves bus bandwidth usage. The packet-switching scheme also simplifies extending the bus to another chassis. Skychannel can operate in a multidrop or crossbar-switched configuration.

  In addition to these backplane sub-buses, VME has acquired a standard front-panel bus: the Front Panel Data Port (FPDP), which Interactive Circuits and Systems Ltd developed. This 32-bit synchronous bus carries data at 160 Mbytes/sec over a ribbon cable attached to the front of the VME card. Because it does not use the P2 connector, the FPDP does not exclude use of a P2 sub-bus on the card. Further, a card can have multiple FPDP buses. Interactive Circuits and Systems Ltd designed the FPDP for data transfer between a pair of boards, although it can be bused for broadcast and group-oriented data transfers. The FPDP is nearing completion of its standardization process (Table A).

  Sub-buses are not the only expansion option that the VMEbus has acquired. Card spacing in a VMEbus cage allows enough room for a VMEbus card to carry a mezzanine-type daughtercard. Such cards allow users to readily configure a baseboard with custom options, such as type and amount of memory, processor type, and I/O capabilities. The mezzanine-card method became so popular with VME that more than 20 mezzanine buses—many proprietary—have appeared (Reference 1).

  Several of the mezzanine-card buses have gained enough support to become industry standards. The PCI Mezzanine Card (PMC) is a prime example. PMC mates the PCI bus structure with the Common Mezzanine Card (CMC) physical structure, allowing PCI-based functions from the desktop-PC world to migrate to VMEbus systems. Standardized as IEEE P1386.1, PMC is available on both VMEbus and Multibus cards in a variety of functions.

  The PMC format doesn't meet all users' constraints, however, leaving market opportunities for other mezzanine-card buses. Three more buses are at various stages of standardization within the VSO. Industry Pack, M-Modules, and CXC should all reach formal standard status during 1997.

Evolution=better performance

  Mezzanine cards and sub-buses have contributed their share to VME's continued success, but the VMEbus structure itself has also evolved to adapt to application needs. The first series of changes following the VMEbus's introduction refined and clarified the specification to eliminate interoperability problems among vendors, resulting in the establishment of the ANSI/IEEE 1014-1987 standard for VMEbus. Two major modifications have since appeared as standards: VME64 and Board-Level Live Insertion (BLLI) for VME.

  VME64 is an optional series of extensions to the VMEbus that became standard in 1994. An important attribute of VME64 is that all of its changes and additions are optional and compatible with the ANSI/IEEE 1014-1987 specification. Boards built to the older specification work with VME64 boards in new or old backplanes. If two boards have some different features implemented, they interact using only their common feature set. Thus, all VME boards that conform to the older specification are "VME64-compliant." They just don't offer any of the additional features.

  The most obvious of VME64's additional features is the one that named the standard: a data-transfer mode that doubles the VMEbus bandwidth. The VMEbus uses nonmultiplexed 32-bit address and data fields for data transfers. VME64 defines a mode in which the address lines can become data lines for block transfers, making a 64-bit data bus. The achievable data rate using VME64 is, thus, 80 Mbytes/sec.

  VME64 also makes many, more subtle, changes. One is the addition of a retry signal to prevent deadlocks, especially in multiported applications, such as bus bridges. The specification also adds automatic configuration of system boards, eliminating the need for jumpers to set board addresses. Further, it adds the ability for a board to detect if it is in slot 1, the location of the system controller. A board in slot 1 can automatically add the responsibilities of the system controller to its operation. The original VMEbus specification required user-set jumpers to configure a board for slot-1 operation, resulting in system failure if boards were inserted in the wrong slots.

  VME64 changed the character of data-transfer acknowledge (DTACK) from an open-collector to a high-current, three-state signal. This change allows boards to actively rescind DTACK rather than allowing it to float. Rescinding DTACK can speed bus transfers by reducing the time DTACK needs to return to logic high following an acknowledgment.

Connectors change to 160 pins

  The standard also specifies a number of mechanical changes that set the stage for later extensions to VME64. The most significant mechanical change is the adoption of 160-pin connectors in place of standard VME's 96-pin connectors. The new connectors are compatible with older backplanes, however, and older connectors work with VME64 backplanes (Figure 1).

  The 160-pin connectors have the same three rows of pin-and-socket connections as standard VME does. They place their additional lines as metal fingers on the outside of side walls that surround the base connector. The mating socket on the backplane has a shroud with wipers that match the finger placement. A standard connector fits within the 160-pin socket's shroud but has no fingers to connect to the wipers. A 160-pin connector fits into a standard socket, which has no shroud.

  The additional pins that the new connector provides include several ground pins, easing the power limits and EMI problems that older VMEbus cards face. The additional pins also provide physical support for live-insertion needs. Several of the fingers on the board connector are extra-long, ensuring that they are the first to make an electrical connection during board insertion and the last to break during removal. The BLLI specification uses these pins for precharging the board's bus drivers to avoid loading the VMEbus when the user inserts the board into a running system.

  Most of the additional pins in the 160-pin connectors remain undefined in VME64, however. Because the larger connectors add no significant utility to VMEbus systems, most cards and backplanes do not use them. That situation may change with the formal approval of VME64 extensions, called VME64x, due for final acceptance as a standard this year. The extensions use many of the additional pins, again double the VMEbus data rate, and significantly modify the card cage, including the addition of electrostatic-discharge (ESD) protection. Also, the extensions still allow older VME boards to work in a new system.

  VME64x defines 3.3 and 48V power pins, for example, to accommodate changing logic-supply voltages. The 48V lines allow a board to use dc/dc conversion to establish virtually any logic voltage it needs. The specification also adds three more 5V pins, 35 more signal-ground-return pins, and 46 more user-defined pins on the J2 connector.

  The additional connector pins also provide geographical addressing for VME64x, allowing a board to determine in which slot it resides. This ability, missing from VME64, allows a board to adapt itself to slot-specific I/O needs, such as matching itself to backplane I/O ports.

Extensions simplify system

  Geographical addressing is one addition VME64x makes to simplify system configuration. With many VME64 systems, you must insert cards into specific cage slots to match I/O cables attached to the backplane. VME64x allows mechanical keying of the cards, with 15,625 keying combinations, to prevent insertion into the wrong slot.

  Other changes to the card cage include provision for ESD protection and the use of board inserters. Cards needing ESD protection can place conductive strips at their top or bottom edges that contact metal clips on the cage's card guides, bleeding off static charges as you insert the board. The board inserters simplify installation of boards into the backplane and can lock the board into place. The inserters can thus replace the screw-terminal board mounts used in conventional VME.

  VME64x also lets you add a third connector, J0, to a VME card bus. This additional 193five-pin, hard-metric pin-and-socket connector fits between J1 and J2 on a VMEbus board. The connector targets general-purpose I/O use and provides 95 signal lines with 19 or 38 ground lines on the outer shell.

  One of the most profound changes VME64x institutes is the use of two-edge handshaking for data transfers. VME64 uses an interlocked four-edge handshake scheme for data transfers (Figure 2a). The sending board asserts a data strobe to initiate a transfer, and the receiving board responds by asserting DTACK. The sender then rescinds the data strobe to indicate valid data on the bus, and the receiver releases DTACK to indicate receipt of the data.

  As its name implies, "two-edge VME" (2e-VME) uses only two edges (Figure 2b). A transition in data strobe indicates valid data on the bus, and transition of DTACK indicates reception. The two-edge protocol effectively doubles the data rate of VMEbus block transfers to achieve a peak of 160 Mbytes/sec.

  For 2e-VME to work at the desired speeds, VME64x changes the board bus drivers. The specification calls for enhanced-transceiver-logic (ETL) bus drivers with a 270-nH, 66 ohms, parallel-LR network in each signal line. The drivers allow the signals to use incident-wave switching while the networks slow signal rise times to prevent EMI and ringing. The resulting signals are compatible with VME64 board's signal characteristics.

  This compatibility is the main reason that VITA omitted these extensions in VME64. To ensure that 2e-VME boards would work with standard VME, VITA had to conduct a long series of simulations to prove the electrical standards. Rather than delay VME64 by waiting for the results, VITA made the 2e-VME scheme part of the extensions. Those simulations have recently concluded, allowing the VME64x specification to be released for standards balloting in early 1997. It should receive final ANSI approval later in the year.

  Although the VME64 extensions are the next step in VME's continuing evolution, they won't be the last. Work is in progress on several new hardware standards for the VMEbus, and VITA is looking into standardizing software with its Embedded Systems Software Environment (ESSE) initiative. The emerging hardware standards include defining a 9U board format, mapping PMC and Internet Protocol mezzanine card signals to the P2 and P0 connectors, blending VMEbus and Compact PCI bus structures, and defining high-availability VME (HA-VME) for systems that need fault tolerance.

  This last hardware standard is the most ambitious. HA-VME extends the existing BLLI specification to encompass system issues. Some of the attributes scheduled for HA-VME include the ability to remotely force a board's bus drivers to a high-impedance state and the definition of a serial bus for backdoor retrieval of memory contents from boards with failed VMEbus drivers. The HA-VME specification will also tackle the system-software issues that fault tolerance raises.

  The VMEbus thus continues to evolve, adding new capabilities as customers demand. It has outstripped all its direct competitors. Although a new competitor has arisen (see box, "Looking ahead"), VME's adaptability ensures that it will meet even this challenge. The continued evolution of the VMEbus promises to keep the bus thriving into the next century.

Reference

1. Quinnell, Richard A, "Mezzanine buses bring backplane benefits to the board level," EDN, March 2, 1995, pg 67.

You can reach Technical Editor Richard A Quinnell at (719) 530-0560, fax (719) 530-0560**.

| EDN Access | Feedback | Subscribe to EDN | Table of Contents |