EDN Access--02.17.97 Ensure system accuracy by analyzing instrumentation-amp settling time

Settling-time limitations in data-acquisition instrumentation amplifiers can defeat their high-performance converters
unless you understand the problem and how to overcome it.

The reliability of your measurements depends largely on the analog characteristics of the instrumentation amplifier you use in your data-acquisition hardware. Analog aspects of amplifier settling time, linearity, noise, and CMRR determine the overall accuracy of commercially available instrumentation amplifiers. Because the error is an analog problem, various error-detection techniques do not notify you of the measurement error. Linearity and CMRR are beyond your control, but you can respond to limitations in settling time.

Many factors in the instrumentation amplifier result in overall settling time. Consider a standard RC lowpass-filter-circuit design. When you apply a voltage step to an RC circuit, the signal requires a certain amount of time to rise and settle within a percentage of the voltage (V) you want. This percentage is the range of accuracy, and the time it takes for the signal to get within the specified range is the settling time.

Figure 1 shows the settling-time characteristics of a standard instrumentation amplifier. Notice the settling time, t_s , that passes before the amplified signal stabilizes within the acceptable voltage range (±%V). The amplifier output should be allowed to settle for at least t_s before the ADC samples the applied voltage. If the sampling rate exceeds 1/t_s, the sampled voltage is inaccurate.

Consider a data-acquisition board with two input signals, one at 5V and the other at 5V. This is a worst-case situation, because, when the multiplexer switches, the instrumentation amplifier sees a 10V step. If the instrumentation-amplifier settling time is 10 µsec and you are sampling at 200k samples/sec, the amplifier does not have time to settle before the multiplexer switches for the next reading. Hence, the voltages sent to the ADC for conversion are incorrect.

Multiplexing, gain, source-output impedance, and transmission-line resistance and capacitance all affect settling time. Gain and settling time typically have a direct relationship because, during amplification, the instrumentation amplifier takes longer to settle at higher gains because of decreased bandwidth and higher signal resolution.

Multiplexing can cause increased settling time when you scan more than one channel. When switching between multiple inputs connected to dc signals, the input to the instrumentation amplifier becomes a very high-frequency ac-class signal (Figure 2 ). With this input, you can see that 42 dc signals originally applied to the specific channel result in an ac signal's being input to the instrumentation amplifier. This ac signal forces the amplifier to track the voltages as quickly as the sampling rate dictates. If the sampling rate is too high, the amplifier does not have time to settle quickly enough between voltage swings, producing inaccurate data.

When scanning multiple channels at various gains, the instrumentation-amplifier settling time may increase. As the amplifier switches to a higher gain, the signal on the previous channel may be well outside the new, smaller range. For instance, suppose that a 4V signal connects to channel 0 and a 1-mV signal connects to channel 1, and suppose that the instrumentation amplifier applies a gain of one to channel 0 and a gain of 100 to channel 1. When the multiplexer switches to channel 1 and the amplifier switches to a gain of 100, the new full-scale range is 100 mV for an ADC in unipolar mode.

The approximately 4V step from 4V to 1 mV is 4000% of the new full-scale range. For a 12-bit board to settle within 0.012% (120 ppm, or 1/2 LSB) of the 100-mV full-scale range on channel 1, the input circuitry must settle to within 0.0003% (3 ppm, or 1/80 LSB) of the 4V step. This situation places severe settling requirements on the input multiplexers and the instrumentation amplifier. For a 16-bit board to settle within 0.0015% (15 ppm, or 1 LSB) of the 100-mV full-scale range on channel 1, the input circuitry must settle within 0.00004% (0.4 ppm, or 1/400 LSB) of the 4V step. Again, the multiplexer and instrumentation amplifier face severe settling requirements. In general, this extra settling time is unnecessary when the amplifier is switching to a lower gain.

The most troublesome effect on settling time comes from the combination of multiplexing and high-output impedance sources and is due to charge injection, a phenomenon in which the analog input multiplexer injects a small amount of charge into each signal source when that source is selected. The high impedance of the source combined with the charging and discharging from capacitance inherent in the multiplexer during switching can cause the data to be inaccurate when you scan multiple channels. As the current being discharged from the multiplexer seeks ground, the current passes through the high-impedance source; the current and the high-impedance source combine to produce a voltage. This voltage adds to the original signal and results in inaccurate data. If the impedance of the source is too high, the effect of the charge--a voltage error--does not decay by the time the ADC samples the signal.

Consider a data-acquisition board with 12-bit accuracy used to apply a gain of 500 to the input signals. The CMOS multiplexers typically used on such boards have about 5-pF input capacitance, 1.2-kiliohms on-resistance, and 25-pF output capacitance. In addition, the instrumentation amplifier has 5 pF more or so at its inputs. Assuming zero switching delay in the multiplexer and zero source impedance yields a 325-nsec settling time to 1/2 LSB of the 12-bit system. Both assumptions are generally invalid, and nonzero source impedance has an especially detrimental effect on settling time.

The 1-gigaohms or greater input impedance of the instrumentation amp may lead you to believe that a 10-kiliohms source resistance is acceptable, but full-scale settling increases to about 3.5 µsec. Further, these settling-time numbers fail to account for the settling times of the instrumentation amp and ADC. In fact, these numbers are optimistic. Placing the 10-kiliohms source more than a few inches from the board introduces significant capacitance in the cabling. For example, using a foot or two of cable that adds 50 pF of capacitance greatly increases scan-mode settling time, because the charge stored from the previously selected channel on the capacitance at the output of the multiplexer is shared with the input capacitance of the newly selected channel. The source now sees, as a first-order approximation, 85 pF through 10 kiliohms, and settling needs to be to 1/2 LSBx(85 pF/30 pF)=1.4 LSB, or 0.035% accuracy.

This process requires approximately eight time constants or nearly 7 µsec. If you want to filter your input with a 0.005-µF capacitor to ground, your scan-settling time increases to approximately 160 µsec. For this reason, keep source impedance lower than 1 kiliohms to perform high-speed scanning.

A typical data-acquisition application may require a programmable-gain-instrumentation amplifier (PGIA) with a gain accuracy of 0.02% and a bandwidth of 1 MHz over a 200 to 1 gain. The design of such an amplifier is not trivial: The absence of integrated products on the market demonstrates this fact. You can use various types of op amps as instrumentation amplifiers, but each involves trade-offs.

The three-op-amp configuration is the classic textbook instrumentation amp. If you use it with off-the-shelf, voltage-mode op amps, it is subject to bandwidth, linearity, and gain-accuracy degradation with gain. To obtain 0.02% gain accuracy and 1-MHz bandwidth over the 200 to 1 gain range, a three-op-amp instrumentation amplifier requires the use of unity-gain-stable op amps with open-loop gain of 10 million and bandwidth of 200 MHz. These products are not widely available.

Another drawback of the three-op-amp approach is that it requires matched resistors for accurate differential-to-single-ended conversion. Moreover, because internal nodes must swing according to both the common- and the differential-mode signal, the input common-mode voltage range decreases with output-voltage swing.

The current-feedback configuration has many characteristics of the three-op-amp configuration, such as good gain-independent settling and a large number of gains. This option does not lend itself well, however, to software-programmable-gain configurations, because any multiplexer resistance appears in series with the gain-setting resistor, introducing gain and linearity errors. In addition, the large overall feedback path tends to limit bandwidth.

The two-op-amp topology achieves wide bandwidth at high gain because it facilitates use of a decompensated op amp for the main gain stage. However, this feature is not useful if you desire programmable-gain values down to unity. Moreover, good CMRR again requires tight resistor matching. Adding gain programmability to this topology requires separate resistor networks for each gain, each of which must be sufficiently well-matched to ensure good CMRR. In most circumstances, the added complication does not justify saving one op amp.

The NI-PGIA is a software-programmable gain-instrumentation amplifier, usually packaged as a daughterboard, used on the National Instruments instrumentation-class data-acquisition products. This amp does not fall into any of the previous categories because it uses a transconductance design that combines the best characteristics of commercially available instrumentation amplifiers and overcomes their limitations. This hybrid PGIA features settling time independent of gain, 12-bit accuracy within 2 µsec, linearity independent of gain, software-programmable gain, eight gains vs four or fewer on other amplifiers, and CMRR equal to the best of any category of instrumentation amplifier. The high accuracy and fast settling time of the NI-PGIA are due largely to the fact that the input op amps operate at close to a closed-loop gain of 1, regardless of the programmed gain. This approach differs from that of most other instrumentation amplifiers, in which the input op amps operate with an increasing closed-loop gain as the programmed gain increases.

The design of the NI-PGIA allows the bandwidth and linearity to stay relatively constant as the gain increases. Thus, the settling time remains at approximately 2 µsec, even at the highest gain of 100. Nonlinearity is approximately 1.5 ppm, and the gain error for the NI-PGIA is ±0.02%. The gain-to-gain variation in gain error is due almost entirely to the ratio matching of the gain-setting resistors of the NI-PGIA. Although the dc CMRR of most instrumentation amplifiers usually decreases as gain decreases, the dc CMRR of the NI-PGIA is nearly independent of the gain. As with most standard instrumentation amplifiers, the NI-PGIA ac CMRR exhibits low gain degradation because of internal stray capacitance. The NI-PGIA incorporates transconductance design, which accurately converts differential input signals into single-ended signals, eliminating the need for well-matched resistors within the instrumentation amplifier and contributing to the high accuracy of the NI-PGIA.Figure 3 compares the settling time of the NI-PGIA to a standard off-the-shelf instrumentation amplifier. The NI-PGIA settles to 12-bit accuracy approximately five times faster than does the standard instrumentation amplifier, which the dc-signal test also reveals.

If you compare the performances of two data-acquisition boards that have the same-resolution ADCs but different instrumentation amplifiers, notice the extreme variation that differences in settling times can cause. Figure 4 shows the results of the dc-signal settling-time tests for two National Instruments multifunction, plug-in, data-acquisition boards. One board has an off-the-shelf instrumentation amplifier and settles to 1/2 LSB in 16 to 17 µsec; the other contains the NI-PGIA and settles more quickly. These tests use ±0.048V signals as inputs for channels 1 and 2 on each board at a gain of 100 and adjust the sampling rates to demonstrate the effects of settling time. You can measure settling time in two ways (see box, "Run your own settling-time test.")

Because the instrumentation amplifier is the location in which most settling-time delays occur, the most effective way to reduce settling time is to use a data-acquisition board with an instrumentation amplifier that is guaranteed to settle to the accuracy you need at all gains and rates.

One technique for handling settling-time effects is to arrange the input signals according to whether you are using continuous- or interval-channel scanning (Figure 5 ). Although signal arrangement may be impossible in all of your applications, you should initially consider this method.

To scan channels continuously as quickly as possible with the same amount of elapsed time between each channel, consider arranging the signals so that the voltage swing is constant between each channel. When it is time to sample the sequence of channels again, however, you must sample the first channel twice to give the amplifier time to settle. By repeating the first channel sample, the amplifier has the extra time to compensate for the maximum swing in voltage.

Interval scanning involves scanning all the channels as quickly as possible with a delay before you again begin to sample the first channel. This type of scanning allows for the largest voltage swing on the channels to occur between the last channel sampled and the repeat of the first channel sample, thus giving the amplifier time to settle without any extra requirements.

Due to the capacitance in cables, you can also help reduce settling-time effects by selecting the proper cabling material. Avoid selecting cables with higher capacitance because of the delay associated with charging and discharging. To reduce the amount of capacitance in a cable, keep the cable as short as possible and select cables made of an inherently low-capacitance dielectric material, such as polypropylene.

Final techniques for lowering settling-time effects are reducing the sampling rate and selecting sources that have low output impedance. Reducing the sampling rate gives the instrumentation amplifier time to settle to the accuracy you want. However, if you reduce the sampling rate to less than the Nyquist rate of twice the maximum input frequency, an undersampled waveform and inaccurate data result. When you are unable to use a device with a low output impedance, use a signal-conditioning module or amplifier with a low output impedance that acts as a buffer to the board input. With this buffer, the multiplexer receives low-impedance signals from high-impedance sources, thus reducing the settling time.

Some data-acquisition boards circumvent the settling-time problem by providing a PGIA or ADC per channel. Although some applications prefer this solution, multiplexed inputs offer some unique advantages that make scanning boards preferable for many applications. Among the advantages are extremely tight matching between channels and higher channel count. Because of the tight matching between channels, you know that each channel has basically the same offset, CMRR, and gain errors. You can measure these characteristics and use them to subtract the contributed errors from the input-signal digitized value.

Run your own settling-time test

There are two methods for determining the settling time of your data-acquisition board--one with dc signals and one with ac signals. You can use these methods to characterize the settling time of your board and to compare the results to the data sheet.

The dc settling-time tests identify the settling time of your board. To perform a dc-signal settling-time test, connect a bipolar signal to input channels 1 and 2. The input signals should be close to but not above the full-scale input range of the data-acquisition board when you apply a high gain. For example, a ±0.048V input with a gain of 100 results in a 4.8V signal, which is 0.2V less than the full-scale value of ±5V board. When running this test, you must not have an input signal greater than or equal to the full-scale value, because the amplifier saturates and results in a longer settling time.

Next, complete at least a 100-point single-channel timed data acquisition for each channel and average the results to obtain a positive and a negative reference voltage. After individually sampling the reference values, acquire 100 points at the maximum sampling rate by alternating the sampling between both channels (scanning). Average the data, and use the results to calculate the settling-time error at the maximum sampling rate. In our example, the average of the positive data is 0.04V; the average of the negative data is 0.048V.

To calculate the error, compute the maximum deviation between the reference voltages and the positive and negative averages of the scanned data. In other words, subtract the averaged scanned data from the positive and negative reference voltages, and use the maximum of the absolute values. This deviation is the amount of settling-time error in voltage at the maximum sampling rate. In our example, the positive and negative deviations are 0.01V and 0.002V, respectively, which results in a maximum settling-time error of 0.01V.

Repeat this process at different sampling rates and gains until the board settles to the specified accuracy. To plot the error in least significant bits vs time, divide the absolute value of the maximum deviation by the voltage equal to 1 LSB for the gain you apply.

Therefore, the error of 0.01V in our example equals 409.8 LSB. Invert the sampling rate to calculate the settling time with that amount of error. At a sampling rate of 100k samples/sec, for example, the settling time is 10 µsec. After the plot is complete, compare the plot to the specified board accuracy to see how long your board takes to settle to the specified accuracy.

The ac-signal settling-time tests determine the sample rate and gain at which you can accurately measure voltage inputs. To perform an ac-signal settling-time test, connect a full-scale, low-frequency ac signal to channel 1, and connect channel 2 to ground. By scanning both channels at the maximum sampling rate and performing an FFT on the data from channel 2, you can determine if the amplifier settles correctly. If any large spikes appear in the FFT plot at the frequency of the channel 1 input signal, the amplifier has not settled completely.

The magnitude of the spike is the amount of voltage error; the corresponding settling time is the inverse of the sampling rate. Using an input signal that is too high in frequency could cause crosstalk, which appears the same as a settling-time error in the channel 2 spectrum. Crosstalk is an expected phenomenon caused by the interplay between capacitance and close proximity of signals, which results in unwanted coupling of the signals. All data-acquisition boards have a measure of crosstalk.

Repeat this process with different sampling rates and gains to see how quickly the amplifier settles and with what amount of error. Reduce the voltage error indicated by the magnitude of the spike in the FFT plot to less than the equivalent of 1/2 or 1 LSB. The amplifier has settled correctly. The spike in the FFT plot never minimizes, because there is always some settling error and crosstalk. You can use this process to determine the sampling rate and gain at which you can accurately acquire data with your data-acquisition board.

1. House, Richard, "Simple tests reveal data-acq boards whose accuracies match their resolution," Personal Engineering & Instrumentation News, June 1994.
2. Kasin, Scott, "Is your data inaccurate because of instrumentation amplifier settling time?" National Instruments Application Note 045, August 1993.
3. Loewenstein, EB, "Test analog-to-digital converters for DNL," Test & Measurement World, December 1994.
4. Regier, Chris, "Avoiding pitfalls in high-speed data acquisition applications," Midcon/89 Conference Report, Sept 12 to 14, 1989.

Edward McConnell is a marketing manager for data-acquisition products at National Instruments (Austin, TX). He has a BSEE from Rice University (Houston).

Design Features

February 17, 1997

Ensure system accuracy
by analyzing instrumentation-amp settling time