Design Ideas February 17, 1997

Circuit conditions variable-duty-cycle clock

Edited by Bill Travis & Anne Watson Swager

David Albean, Thomson Consumer Electronics, Indianapolis, INA simple enhancement of an earlier Design Idea ("Delay line implements clock doubler",EDN, July 18, 1996, pg 102) implements a variable-duty-cycle clock-signal conditioner. The circuit accepts an input clock of any duty cycle and generates any desired duty cycle at the output. You need to add only one flip-flop to the earlier design to generate an arbitrary-duty-cycle output. You can use the circuit to correct a non-50% input to a 50% output or to create a non-50% output from any arbitrary input duty cycle.

The input-clock signal serves as the clock signal to a D flip-flop, which is configured as a toggle flip-flop. The flip-flop's output signal is thus a 50%-duty-cycle, half-frequency version of the input clock, independent of the input-clock duty cycle. The flip-flop's output passes through the clock-doubler circuit (from the earlier Design Idea, Figure 1b). The doubler circuit (delay element t and XOR gate) doubles the frequency. The doubling restores the output signal to the same frequency as the input (Figure 1a).

The duty cycle, however, is determined by the value of the delay, t. The output duty cycle is (t/T)·100%, where T is the period of the incoming (and now output) clock signal. You can implement delay element t as described in the earlier Design Idea, or you can use logic gates or other methods. For example, assuming an input frequency of 50 MHz, choosing t=T/2=10 nsec results in a 50% output duty cycle, independent of input duty cycle (Figure 2a). If the desired duty cycle is 30%, choose t=6 nsec (Figure 2b). If the desired duty cycle is 70%, choose t=14 nsec. You can make the delay time electronically controllable, thus allowing continuous dynamic selection of output duty cycle. (DI #1987)

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