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Leading EdgeFebruary 3, 1997 |
WHAT'S HOT IN THE DESIGN COMMUNITY
EDITED BY FRAN GRANVILLE
To run power supplies in parallel, whether for system reliability and backup or to handle an increasing load, you can't simply connect the outputs of the multiple independent units. The UC3902 load-share controller from Unitrode lets you use standard supplies--those with a remote-sense or output-voltage-adjust input--in a parallel configuration by balancing the current from each supply. Using one of these eight-pin ICs per supply automatically adjusts each supply's output current to a level proportional to the voltage on a "share" bus.
To use the load-share controller, you designate one supply as the master; this supply regulates to the highest voltage, driving the share bus with a voltage proportional to its output current. The UC3902 then trims the output voltage of the other supplies so that each provides its share of the total load current. Although each supply typically provides the same amount of current, you can use supplies of differing output-current capacity by using different current-sense resistor values.
Each UC3902 requires four external resistors and one capacitor, operates from a 2.7 to 20V supply, and contains a precision current-sense amplifier with gain of 40. The differential share bus maximizes noise immunity and compensates for the voltage drops in each supply's ground return line. User-programmable compensation of the share loop lets you tailor the loop's performance to the transient characteristics of the supplies. The $1.62 (1000) IC is available in eight-pin DIP and SOIC packages.
--by Bill Schweber
Unitrode Corp, Merrimack, NH. (603) 424-2410, www.unitrode.com.
Computer-telephony standard aimsat flexibility, interchangeability
The UC3902 load-share controller lets you use existing power supplies in a parallel configuration by adding one eight-pin IC plus a few passive components per supply.To enhance the integration of telephony-based functions with computer technology, Dialogic has announced a collection of specifications that provides a framework for independent technology and application developers' efforts. The company's DM3 resource architecture supports industry standards, such as Signal Computing Signal Architecture-selected Enterprise Computer Telephony Forum recommendations; open-computing-system standards, such as PCI, VME, and CompactPCI; and de facto standards, such as Dialogic SR4.x and GlobalCall application-programming interfaces.
DM3 goes one level below these standards and recommendations, defining hardware- and software-specific open standards. It includes firmware-based network-protocol and media-processing resources that will operate together on compatible hardware platforms.
Initially, DM3 will support Unix and Windows NT operating systems. Although not tied to a DSP IC, the first platforms will use as many as 18 Motorola 563xx systems and as many as eight PowerPC 603e devices. Initial products include a quad digital telephone interface (DTI), a quad voice with quad DTI, a quad DTI with SS7 support, fax functions, "real-time" voice-over Internet Protocol, automatic speech recognition, and text-to-speech functions. Other products will emerge throughout the year.
--by Bill Schweber
Dialogic Corp, Parsippany, NJ. (201) 993-3000, www.dialogic.com.
Software expands flash-memory storage options
Three new software-development products from Wind River Systems aid the development of flash memory as mass storage. The three products let you implement flash-based mass-storage applications without using a silicon-resident flash-memory controller. The company based one of the products, TrueFFS for Tornado, on M-Systems' TrueFFS.
TrueFFS for Wind River's Tornado development system is a 25-kbyte blocked device driver that runs under DOS or the Network File System and translates standard hard-drive commands into equivalent flash-memory operations. The software is based on M-Systems' high-level language source code, which Wind River compiles and supports as an object module for various CPU architectures--initially, x86 and 68K, with more to follow based on customer requests.
M-Systems' TrueFFS's Flash Translation Layer flash-file-system data structure, now a PCMCIA standard, is also available for the QNX and PSOS+ real-time operating systems, targeting x86 mPs, and for the Windows CE 1.0 and Windows 95 OSR.2 releases. The software manages flash-media wear leveling; increases performance via background cleanup operations; detects and maps around errors resulting from bad flash-memory blocks; and gracefully recovers from system failures, such as power loss during writes.
TrueFFS products operate with flash memories from NOR vendors AMD (Sunnyvale, CA), Fujitsu (San Jose, CA), Intel (Santa Clara, CA), and Sharp (Camas, WA) and NAND vendors National Semiconductor (Santa Clara), Samsung (San Jose), and Toshiba (Irvine, CA). The TrueFFS software also supports the Common Flash Interface; M-Systems would have to slightly modify the memory-technology driver to accommodate other architectures, such as DINOR and AND. The software will be available in March for $12,000 (50,000 or fewer target systems) or $40,000 (more than 50,000 target systems).
VxFMM for the general-purpose VxWorks operating system and IxFMM for the IxWorks operating system and the I2O initiative each use less than 10 kbytes and target low-functionality data-storage applications that do not require full disk emulation. VxFMM and IxFMM operate as standardized application-programming-interface device drivers and potentially support a range of CPUs, with the initial version of VxFMM targeting Intel's i960 mPs.
VxFMM and IxFMM currently operate with symmetrically blocked NOR flash memories. VxFMM is free and available now. IxFMM is also free; the company will ship the product with the Tornado for I2O release in the second quarter.
--by Brian Dipert
M-Systems, Santa Clara, CA. (408) 654-5820, www.m-sys.com.
Wind River Systems Inc, Alamda, CA. (510) 814-2050, www.wrs.com.
If you're considering using in-system-programmable (ISP) logic devices or integrating DSP functions in your next project, point your Web browser at Programming Silicon (www.pldsite.com) or Reconfig.Com (www.reconfig.com). These Web sites let you view the results of some industry pundits' informative and entertaining round-table discussions on various ISP and DSP issues.
ISP topics include system and support implications of ISP, silicon and software innovation's effect on future ISP capabilities, a comparison of ISP vs reconfigurable computing, and ISP-protocol standardization efforts and status. DSP topics include applications for integrating DSP into programmable logic, programmable-logic vs traditional DSP, tool requirements and capabilities, and future evolution.--by Brian Dipert
SB Associates, Los Gatos, CA. (408) 356-5119, sbaker@best.com.
The µPD98405 ATM controller from NEC integrates the asynchronous-transfer-mode (ATM) adaptation layer (AAL-5), the ATM segmentation and reassembly (SAR) function, and the synchronous-optical-network (SONET) physical layer into one chip. It also includes either a PCI- or a generic-bus interface. The device supports available bit rate (ABR), as well as constant, variable, and unspecified bit rates. The ATM controller works in designs for ATM uplinks from routers and switches and network-interface cards for servers and workstations.
The µPD98405 is the first chip to integrate a 155-Mbps SONET physical-layer function onto the SAR core. An optional Utopia interface supports other external framers. The integrated ABR scheduler and traffic-rate controller minimize host-CPU involvement in these functions. The PCI interface supports 32- and 64-bit buses and multicell bursts of as many as five cells per DMA cycle in both transmitting and receiving directions. RISC processors and other system buses use the bus interface in a generic mode.
The receiving FIFO buffer can hold as many as 96 ATM cells to minimize loss of received cells. The device also provides filtering based on destination addresses of received packets. This approach helps in the LAN-emulation function that ATM provides for using existing LAN protocols over ATM.
The µPD98405 comes in a 304-pin PQFP and will be available at an introductory price of less than $99 (1000).
--by Stephen Kempainen
NEC Electronics, Santa Clara, CA. (408) 588-6000.
Offline chargers mix programmability, precision
A stream of ICs for offline battery charging continues to flow. For example, Analog Devices' ADP3810 and ADP3811 form the controller core of a charger circuit for Li-ion, NiCd, and nickel-metal-hydride (NiMH) batteries. When you combine these ICs with a flyback, buck, or linear converter, they drive the diode side of an optocoupler and provide isolated feedback control of a primary-side pulse-width modulator in selectable constant-current or -voltage mode.
Both ICs include a precision 2V reference, undervoltage lockout, overvoltage comparators, and input and output buffers. The $2.57 (1000) ADS3810 includes resistors that yield ±1% accuracy for charging Li-ion cells, and you can program the $2.43 (1000) ADP3811 (for NiCd and NiMH cells) using external resistors. Programmable charge currents span 100 mA to 1.2A. The eight-pin SOIC devices feature 0.25% load regulation and 0.004% line regulation and operate using 2.7 to 16V supplies.
--by Bill Schweber
Analog Devices, Inc, Norwood, MA. (617) 937-1428, www.analog.com.
The 68554 HiQVision and the 68555 HiQVPro graphics-accelerator chips from Chips and Technologies incorporate a new technology that improves the color and resolution of flat-panel displays. The technology makes possible affordable notebook computers with large, high-resolution flat-panel displays and targets acceptance of flat panels as CRT replacements on desktops. The HiQColor technology with Temporal Modulated Energy Distribution (TMED) increases the color depth and image fidelity of low-cost, passive Super Twisted Nematic (STN) panels.
The HiQColor technology provides the less expensive STN panel with viewing quality comparable to that of active-matrix, thin-film-transistor (TFT) panels. Along with improvements in STN screen quality, such as reduced crosstalk and faster response, HiQColor technology expands the market for STN panels. The significant cost advantage for STN over TFT panels increases as the panel size increases.
The TMED algorithms allow the display of 16.7 million colors on STN panels without frame-rate control or dithering. This technique also eliminates shimmer, Mach banding, and other motion artifacts that are normally associated with dithering and frame-rate control. The TMED algorithm uses LCD characteristics and human retinal persistence to generate gray shades without creating static artifacts. The energy-distribution process uses the spatial domain to minimize motion artifacts. TMED creates a partial optical illusion that provides 256 gray shades per primary color, or 16.7 million colors.
The HiQVision graphics accelerator for desktop and notebook computers integrates a 64-bit bit-block-transfer engine for 2-D graphics and video. Hardware multimedia support includes a zoomed-video port, YUV-to-RGB conversion, and double buffering. The HiQVPro graphics accelerator for driving images and text on TV sets from notebook computers reduces flicker by integrating circuitry to average data from odd and even fields. It also enhances CRT viewing via an on-chip, 135-MHz RAMDAC for displaying 1280x1040 pixels on CRTs at 72 MHz and vertical interpolation for playback of 720-pixel-wide, MPEG-2 images at full screen.
Both devices come in 256-pin BGA packages. The 68554 costs $38.80 (10,000), and the 65555 will be available in March for $40 (10,000).
--by Stephen Kempainen
Chips and Technologies, San Jose, CA. (408) 434-0600.
The LT1575 family of linear low-dropout regulators from Linear Technology achieves ultrafast load-transient response. This feature lets you use low-cost output capacitors instead of more costly, very-low-ESR tantalum or several-hundred-microfarad bulk electrolytic units. The LT1575, with a single fixed 1.5, 2.8, 3.3, 3.5, or 5V output, drives an external N-channel MOSFET to supply load current as high as 15A. The companion LT1577 dual regulator is available in several fixed- and adjustable-output-pair combinations.
You can supply a 200-MHz Pentium-class µP via these regulators and achieve transient reponse of a few hundred nanoseconds using just a network of 24 1-µF capacitors. The RDS(ON) of the FETs you select determines dropout voltage. Output-voltage tolerance is ±0.6% at 25°C and ±1% over the 0 to 70ºC range; typical load regulation is 1 mV. A built-in high-side current-limiting amplifier activates a fault-protection function upon overcurrent. The single LT1575 is available in an eight-pin SOIC or PDIP for $2.40 (1000); the dual LT1577 comes in a 16-pin SOIC for $4.45 (1000.--by Bill Schweber
Linear Technology Corp, Milpitas, CA. (408) 432-1900, www.linear-tech.com.
Video op amps target consumer applications
Elantec tailored its EL2110C family of eight op amps for cost-sensitive video applications. Members of the family--comprising single, dual, triple, and quad devices--operate at 5V and can drive 150 ohms loads to 2/1V levels, with 130V/µsec slew rates; 0.1-dB bandwidth is 5 MHz.
The multichannel op amps feature interchannel isolation of at least 60 dB. Four of the op amps are stable at gain of 2 with 100-MHz gain-bandwidth product; the corresponding figures are gain of 1 and 50 MHz, respectively, for the other four op amps. Supply current is 2.4 mA at 0V output. The devices, with prices beginning at $1.33 (1000) are available in SOT23 as well as eight- and 14-pin SOIC and PDIP packages.
--by Bill Schweber
Elantec Semiconductor Inc, Milpitas, CA. (408) 945-1323, www.elantec.com.
VLIW DSP targets general-purpose applications
DSP vendors improve the performance of their devices by boosting clock frequency or architecturally redesigning cores to include deeper pipelines, more sophisticated hardware loops, and larger caches. However, very-long-instruction-word (VLIW) DSPs yield the biggest DSP-performance improvements. These devices have multiple functional units that simultaneously and independently execute different operations.
One company incorporating VLIW DSPs in its products, Texas Instruments, is the first to use the architecture in a general-purpose processor. Previously, VLIW processors, available from such companies as Philips (Sunnyvale, CA) and Chromatic Research (Mountain View, CA), targeted only PC-multimedia applications.
TI's VLIW architecture, VelociTI, or TMS320Cx, comprises dual datapaths and eight functional units, including two multipliers, six arithmetic units, and 32 32-bit shared registers. TI claims that the TMS320Cx running at 200 MHz delivers 1600 MIPS and performs a 1024-point FFT in 70 µsec. TI's first VLIW product using this architecture, the TMS320C6201, is a fixed-point implementation. The VelociTI architecture also supports floating-point implementations.
A main challenge of using any VLIW architecture is feeding it instructions quickly enough for it to efficiently run all the functional units. To combat this problem, the TMS320C6x uses instruction packing and prefetched branching to allow the processor to fetch and execute as many as eight instructions per cycle. The processor also conditionally executes all instructions, a method for reducing branching and, therefore, keeping the pipeline flowing.
The TMS320C6x has development support from 13 tool vendors, as well as TI. For example, TI offers a compiler and an assembly optimizer. The compiler determines all parallelism at programming time. Therefore, the code executes as programmed on independent functional units and eliminates the need for core features, such as out-of-order execution. The assembly optimizer simplifies assembly-language programming and automatically schedules and parallelizes instructions from serial, inline assembly code. The assembler assigns resources and reads straight line code without regard to registers or functional units.
The VelociTI architecture's deterministic operation overcomes the difficulties of developing a debugger for a VLIW processor. Deterministic operation allows the debugger to easily lockstep through the code. The debugger performs code profiling to determine how long the processor spends in various portions of your code.
The development tools for PC ($2995) and Sun ($4995) host platforms include a C6x C compiler, an assembly optimizer, a simulator, and a linker. TI also offers a hardware-emulation board that is compatible with the company's XDS510JTAG emulator interface.
Applications for the TMS320C-6201 include pooled modems, wireless base stations (for which the DSP can implement 30 enhanced, full-rate Global System for Mobile communications channels), remote-access servers, digital subscriber-loop systems, cable modems, and voice-mail systems. The device features 512 kbits of program memory; 512 kbits of data memory; a 32-bit glueless interface for SDRAM, synchronous burst SRAM, and SRAM; two enhanced, buffered serial ports with direct support for T1/E1 lines; a 16-bit host-access port; two DMA channels with boot-loading capability; and a PLL that multiplies the external clock rate by 2 or 4. The C6201 comes in a 352-lead BGA and sells for $96 (25,000).
--by Markus Levy
Texas Instruments Inc, Denver, CO. (800) 477-8924, ext 4500, www.ti.com/sc/C6x.
Vitesse's new SLX standard-cell family complements the company's ASIC gate-array products. SLX macros come in full- and half-speed versions that operate at approximately 0.13 and 0.07 µW/gate, respectively. In addition, a power-management technique powers down portions of SLX-based chips when pieces of logic are inactive. SLX also includes several megacell blocks to embed into SLX designs, including single-port SRAM as large as 64 kbits, multiport register files, PLLs, and timing verniers. Vitesse has additional megacells under development.
To use existing technology and test resources, Vitesse is building the SLX products on the five available gate-array bases of the GLX family. The company uses a modified gate-array router to route the SLX cells. You can place SLX arrays having 15,000 to 220,000 raw gates on a chip with 60 to 70% gate usage. The five SLX chip bases have 87 to 187 I/O pins. You individually configure each I/O to one of several industry-standard interfaces, including TTL, ECL, and Gunning transceiver logic. All the SLX chips come in PQFPs.
To design SLX-based products, you use Vitesse's GaAs Logic Integrated Design Environment (GLIDE). GLIDE comes with design kits for many popular EDA-tool suites, including those from Cadence (San Jose, CA), Mentor (Wilsonville, OR), Synopsys (Mountain View, CA), and Viewlogic (Marlborough, MA). Vitesse is now accepting SLX designs, with prototypes and production quantities currently available. SLX arrays sell for less than one-tenth of a cent per used gate in volume quantities; NRE charges start at approximately $30,000.
--Jim Lipman
Vitesse Semiconductor, Camarillo, CA. (805) 388-3700, fax (805) 987-5896.
For $975, Webb Laboratories' Professional Partnership Program gives you RF and microwave-simulation and synthesis tools that you can distribute freely throughout your organization. The two-part tool package comprises Circuit Analysis and Structure Synthesis (Circuit/Structure) and SystemPlus. Circuit/Structure encompasses broadband nodal-analysis software with transmission-line synthesis and analysis. The tool handles single- and coupled-planar, wire, coaxial and nontransverse-electromagnetic topologies. SystemPlus combines system gain, noise, and intermodulation analysis with other RF- and microwave-design capabilities.
The PC-based combination runs under DOS, Windows 3.1, or Windows 95. For installation, you need about 10 Mbytes of disk space. The tools also come with a users' manual.
--by Jim Lipman
Webb Laboratories, Brookfield, WI. (414) 367-6825, fax (414) 367-6824, www.webblabs.com.
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