|
Leading EdgeMarch 3, 1997 |
WHAT'S HOT IN THE DESIGN COMMUNITY
Version 4.0 of Hewlett-Packard's VEE graphical programming language speeds and simplifies programming of applications and includes a compiler that enables applications to run as much as four times faster than they would under earlier versions. The improved multiple-document graphical-programming interface conforms to Microsoft's human-interface guidelines for Windows 95, Windows NT, and Visual C/C++. As a result, VEE 4.0 Program Explorer is familiar to anyone who uses the Windows Explorer.
An Instrument Manager searches for all instruments that connect to a computer and automatically handles addressing of IEEE-488, VXI, and LAN-based devices, regardless of whether the test engineer controls instruments via drivers or directly. With V4.0, developers can also create runtime applications without additional runtime versions of VEE.
Users can now integrate objects from V4.0 into applications written in standard text-based languages, such as C. An ActiveX control encapsulates user functions for integration into applications such as Visual Basic and Excel, which comply with Microsoft's Object Linking and Embedding protocol. For C users, a library performs the same function as the ActiveX control. A source-documentation function lets users print and archive the design and structure of VEE programs.
Beginning on March 15, you can download an evaluation copy of VEE from www.hp.com/go/hpvee.com. VEE for Windows 95 and NT costs $1295. A version for HP-UX costs $2495. Besides HP, several data-acquisition hardware and software vendors also market VEE.
--by Dan Strassberg
Hewlett-Packard Co, Palo Alto, CA. (800) 452-4844.
The chip-set division of National Semiconductor (formerly, PicoPower) offers several new products that support the Socket 7 processors from AMD (Austin, TX), Cyrix (Richardson, TX), and Intel (Santa Clara, CA). The chip set targets mobile computers and comprises the PC87550 PCI-system controller (the north bridge), the PC87560 PCI system-I/O controller (south bridge), and the PC87570 keyboard and power-management controller.
The PC87550 provides the CPU-to-PCI interface and arbitration functions and enables concurrency among the CPU, level-2 cache, and main memory. It uses independent buffering at the various levels to deliver a sustained 100-Mbyte/sec data-transfer rate. This north bridge also supports SDRAM, extended-data-out mode, and fast-page mode in mixed mode with automatic detection. The PC87550 supports active and passive power management, including six power-down modes and support for L2-cache power management. The device contains a thermal controller that senses the temperature and can throttle the CPU's clock if the CPU gets too hot. The chip also supports hot, warm, and cold docking and comes in a 388-pin BGA.
The PC87560 supports PCI bus-mastering for two EIDE channels, the Universal Serial Bus, and a 4-Mbps universal infrared controller. These bus masters have scatter/gather DMA capability. The PC87560 uses deferred PCI transactions to control the lower speed system-I/O devices, such as the floppy-disk drive, 16550 serial port, and IEEE-1284 parallel port. The PC87560, which comes in a 316-pin BGA, supports the distributed-DMA and serial-interrupt-request protocols. The PC87550 and PC87560 combination sells for $45 (1000).
The PC87570 features keyboard and mouse interfaces, a real-time clock, an 8-bit ADC with an eight-channel input multiplexer and four 8-bit DACs, and as many as 76 general-purpose I/O ports. This device serves as the peripheral power-management controller and can power up and down the entire PC based on multiple internal and external event sources, such as fax/modems, keyboards, and mice. The PC87570 sells for $15 (1000).
--by Markus Levy
National Semiconductor, Santa Clara, CA. (800) 272-9959, www.national.com.
If you're looking to hold down expenditures for design-software packages, here are some resources in addition to those mentioned in "Free and almost-free PC software supports PLD/FPGA design" (EDN, Jan 16, 1997, pg 87). Some of these packages don't cost anything; others keep the cost low or let you try before you buy.
In the "free" category, Actel offers a CD-based tutorial, "The FPGA Integration Primer," which includes a copy of ACTgen Macro Builder. This tool lets you design complex macro functions, such as adders, counters, FIFO buffers and multipliers, and it suggests the best way to implement functions in an Actel FPGA. It can optimize macros for either speed or low gate count.
Some design software is "sort of free," in that you can evaluate full-featured tool sets for free to see if they meet your needs. If they do, you buy them; if they don't, you return them. Altera, for example, encourages free use of any of its software, including the top-of-the-line PLS-Magnum development tool suite when you're evaluating Altera devices for possible use in your next design. In addition, once you buy any Altera tool set for your own use, Altera allows anyone else at your site to use a basic subset of the tools' capabilities. This basic feature set, comparable to Altera's $495 PLS-ES software, supports devices with as many as 10,000 gates and includes third-party tool "hooks" and libraries.
In the "almost-free" category is Waferscale Integration's $99 PSDSoft Lite, which configures WSI's PSD3XX memory-plus-logic devices for a microcontroller interface and other design criteria. The tool ensures no conflict between programmable logic, memory, and internal microcontroller circuit addresses. It integrates WSI's version of Data I/O's Abel 6.2 for configuration of the logic array; it operates under Windows 3.x and Windows 95.
--by Brian Dipert
Actel Corp, Sunnyvale, CA. (408) 739-1010, www.actel.com.
Altera Corp, San Jose, CA. (408) 894-7000, www.altera.com.
Waferscale Integration Inc, Fremont, CA. (510) 656-5400, www.wsipsd.com.
Philips has thrown down the gauntlet--and it has landed in front of a $30,000 1997 BMW Z3 Roadster. If you are up to the challenge, your XA-family microcontroller-based design can win you the Beemer or one of three $4000 IBM Thinkpad notebooks. To participate, you need to feature the 16-bit XA microcontroller in an original design. Visit the company's Web site (www.semiconductors.philips.com) or call Matt Schroeder at (800) 447-1500, ext 1361 to acquire details on the XA architecture, available development boards, and contest rules and regulations.
Several third-party development tools are available at prices as much as 50% lower than their regular price to facilitate your design. For example, the $199, 24-MHz Ceibo P51EBXASD in-circuit emulator performs real-time emulation of the XA-G3. The emulator, which supports internal and external memory and features a 64-kbyte trace buffer, comes with a source-level debugger for both C and assembly, and includes Windows interface software. The $135 Future Designs P51XTENDSD demo board for the XA-G3 has a 256-kbyte code-memory space and a 64-kbyte data-memory space. The board, which is a target board and incapable of in-circuit emulation, features space for prototyping. It includes a users manual, schematics, and a power supply. The $99 20-MHz Macraigor P51XA DEMOSD demo board supports as much as 32 kbytes of code and 512 bytes of RAM. It comes with an assembler, a simulator, and a translator for the XA and runs under Windows. You can acquire any of these development tools directly from Philips.
Once you develop your circuit, submit a brief (500 words or fewer) hard-copy description of your design, a block diagram, a hard copy and a DOS-formatted diskette of the software programs you've written, and any other written or graphic data necessary to understand your design. All entries must be legible and complete; Philips will disqualify any incomplete entries. Finalists must submit target hardware. All entries must be postmarked by midnight Sept 30, 1997.
Judges from EDN and Philips will evaluate entries on originality, feasibility, relevance, and use of the full potential and performance of the XA microcontroller. Winners will be notified by Oct 30, 1997.
--by Michael C Markowitz
Philips Semiconductor, Sunnyvale, CA. (800) 447-1500, ext 1361, www.semiconductors.philips.com.
Microamp and milliwatt levels do not define all amplifier applications. For example, motor drives, sonar systems, weld controllers, and shake tables instead need kilowatts of power. The SA03 PWM amplifier from Apex Microtechnology can supply as much as 3000W with 30A continuous current. This hybrid device operates from 16 to 100V and includes an internal 22-kHz oscillator, or, if needed, you can provide an external oscillator signal to synchronize switching frequencies. The 3-in.2 (19-cm2) device directly drives the load via internal H-bridge drivers and MOSFETs.
The amplifier features current sensing for each half of the bridge to determine signal amplitude and direction. A protection/shutdown circuit directly monitors die temperature; a high-side current limit and a programmable low-side current limit protect the amplifier from supply, ground, and load shorts. You can shut down the SA03's bridge drivers via an external signal. The 12-pin PWM amplifier costs $345 (100).
For lower power applications, the $295 (1000) SA02 PWM amplifier delivers 10A from supplies as high as 80V with efficiency as great as 94%. This 800W amplifier switches at 250 kHz and provides 25-kHz bandwidth; its thermal and short-circuit protections are similar to those of the higher power sibling.
--by Bill Schweber
Apex Microtechnology Corp, Tucson, AZ. (520) 690-8600, www.teamapex.com.
New PC-based instruments from National Instruments--two function generators, three two-channel DSOs, and a 51/2-digit DMM--offer an array of packaging options. You can buy a DAQScope DSO as a PCI board ($1195), an ISA board ($995), or a PCMCIA card ($1195). A DAQ-Arb function generator is available as a PCI board or an ISA board (each $2995), and a DAQMeter DMM is available as a PCMCIA card ($695).
Although the term "data acquisition" normally suggests gathering of experimental data or monitoring of automated manufacturing processes, these products' specs suggest different applications. The DSOs and the DMM target users making general-purpose measurements, particularly in field service, whereas the function generators are ideal for automatic-test setups. Also, although you can use the DAQArbs as true arbitrary-waveform generators (ARBs), the products will probably see greater use as function synthesizers that, technically, are not ARBs.
Specifications rival those of costlier rack-and-stack and VXI units. Key specs of the DSOs include simultaneous sampling on two channels, real-time capture to 20M samples/sec, random-repetitive equivalent sampling for repetitive signals to 1G samples/sec, 15-MHz bandwidth; memory depth of 662k samples, and ac and dc coupling. The DMM features voltage ranges from ±20 mV to ±250V dc and 20 mV to 250V isolated true rms ac (20 Hz to 25 kHz), resistance ranges from 200 ohms to 20 megohms, as may as 60 readings/sec, and dc voltage error of ±0.02%. Waveform generators offer one channel; as much as ±10V analog output; 0M samples/sec; 12-bit resolution; 16-bit digital-pattern output; waveform memory of 2M samples, expandable to 8M; waveform linking and looping; and 32-bit direct digital synthesis that generates waveforms with fundamental frequencies as high as 16 MHz. All six products come with VirtualBench software, so you can use them without writing programs.
--by Dan Strassberg
National Instruments, Austin, TX. (800) 258-7022, fax (512) 794-8411, www.natinst.com.
LSI Logic has joined IBM Microelectronics (Essex Junction, VT) and Texas Instruments (Dallas) in announcing libraries for CMOS-process chips fabricated at a 0.18-µm effective channel length.
With its new G11 process, LSI offers a standard-cell library of more than 1000 cells for either low power at 1.8V or high performance at 2.5V. Unlike the company's previous 0.25-µm G10 family, LSI has only one base-fabrication process for both types of designs. This feature allows you to mix and match high-performance and low-power blocks on a chip. According to LSI, logic blocks fabricated in the G11 process have as much as 30% less intrinsic delay and as little as one-fourth the power dissipation of comparable blocks in the G10 process.
LSI estimates that a G11-processed chip can have as many as 8.1 million gates of logic and 8 Mbits of memory. Five metal layers are available for interconnect. The first three metal layers have a close metal pitch, resulting in a routing-usage factor greater than 80%. The top two layers--for clock, power, ground, and critical global signal routing--have twice the width and thickness of the first three layers, resulting in less interconnect resistance and delay. I/O options for connection outside the chip include low-voltage differential signal as high as 1.2 GHz.
LSI is accepting designs for G11 processing. Chip prototypes will be available in third quarter, with initial and full production scheduled for the fourth quarter and 1998, respectively.
--by Jim Lipman
LSI Logic, Milpitas, CA. (800) 574-4286, www.lsilogic.com.
Announcements from Actel and Xilinx give you more options and the ability to integrate more discrete logic and memory in high-density PLD designs. Actel's 30,000-gate A32300DX antifuse FPGA, the latest member of the Integrator series, offers logic capacity comparable to 70,000-gate SRAM-based FPGAs using common industry gate-count benchmarks, according to Actel. Antifuse FPGAs typically contain an abundance of routing resources, minimizing or eliminating pin reallocation and performance degradation due to last-minute redesigns. The A32300DX provides pin compatibility with previous family members, offering a density-upgrade path without pc-board changes.
Each device features an onboard, dual-port, 3072-bit SRAM, offering 100-MHz FIFO-buffer operation and a fast, wide decoder module that performs 35-bit 7.5-nsec internal and 15-nsec pin-to-pin decodes. These features match the ever-increasing performance needs of networking and other high-bandwidth applications. Price is $299 (5000), and packaging options include 208- and 240-pin QFPs.
In a first for Xilinx, the XC4062XL SRAM-based FPGA, currently sampling, claims to break the elusive 100,000-gate barrier. The 3.3V device offers 40,000 to 130,000 implementable gates, depending on whether you use each of 5472 logic blocks as single- or dual-port SRAM as large as 73,728 bits or as logic functions. Applications such as PCI-bus-based networking exploit the device's maximum 100-MHz performance and high-speed internal FIFO buffers. The XC4062XL's segmented signal routing couples with place-and-route software to lower power consumption, a critical issue for designs that strive to eliminate fans due to noise and reliability. Projected price is $295 (25,000), and packaging options include QFP, BGA, and PGA with a maximum I/O count of 384.
--by Brian Dipert
Actel Corp, Sunnyvale, CA. (408) 739-1010.
Xilinx Inc, San Jose, CA. (408) 559-7778.
A new processor/chip-set module from Intel may "evolutionize" the way in which OEMs design mobile computers. Intel's Mobile Module integrates a 150- or 166-MHz P55C; a new 430TX chip set; a 256-kbyte, level 2 cache; a system clock; and voltage regulation. The module also includes a common thermal interface that allows an OEM to attach a cooling device, such as a heat sink or fan.
Mechanically, the module connects to the motherboard using three mounting holes. Electrically, the module connects to the motherboard through the system-memory bus, PCI bus, and north-to-south-bridge sideband signals. The FCC-certified module allows a mobile-computer OEM to use one basic system design for several generations of processors. The module, minus the µP and chip set, sells for $71.80. The 430TX chip set is also available separately for $32.50 (1000); this price includes the north and south bridges. Both chips come in a 324-pin BGA package.
Besides the standard Intel chip-set features, the 430TX supports enhanced-SDRAM operation, Ultra DMA, and two Universal Serial Bus ports. The SDRAM controller includes more speculative timing features than do previous chips and allows access to 64-Mbit devices.
The 430TX also supports Intel's "dynamic power-management architecture," which lets you choose among built-in power management, user-directed power management, and the Advanced Configuration and Power Interface. Using the built-in power management, the TX consumes as much as 75% less power than its predecessor. The chip set monitors bus activity and automatically shuts down when the bus is idle. This power-management scheme incurs no wake-up latency. The user-directed scheme allows a user to indirectly program registers that support a range of power-down modes.
Along with the module and chip set, Intel is also announcing the 380FB chips for docking-station connections. The 380FB chips comprise PCI-to-ISA and PCI-to-PCI bridges. Both chips come in 208-lead SQFPs, and the set sells for $28 (1000). The 380FB set supports Windows 95 hot-docking for four 100-Mbyte/sec PCI slots and three ISA slots.
--by Markus Levy
Intel Corp, Santa Clara, CA. (800) 356-3600, www.intel.com.
Test equipment designed for R&D is often too complex, expensive, and bulky for field use, and much of this equipment can't take the electrical and mechanical punishment that service tools must routinely withstand. Therefore, Fluke is targeting the Model 123 ScopeMeter test tool at users who service and maintain the products and systems you design. If you influence the selection of test equipment for service and maintenance, you may want to consider this product.
Like the other members of the family, the Model 123 combines DSO and DMM functions. The same test leads act as meter and scope inputs. The unit has two channels, and the back-lit display always presents both channels' 5000-count-resolution meter readings (true-rms for ac). In addition, one channel can function as an ohmmeter, a diode tester, and a capacitance meter. To simplify the user interface, Fluke eliminates cursor measurements; to keep the price less than $1000, the signal bandwidth is 20 MHz. Unlike older ScopeMeters, though, the Model 123 has a separate 25M-sample/sec ADC for each channel. At sweep speeds lower than 1 µsec/div, the unit samples in real time. At higher sweep speeds, it uses random-repetitive sampling.
The 123's automatic triggering uses an ASIC with a 68000-series µP core. This embedded intelligence lets the unit present a stable display of such challenging waveforms as pulse bursts. Moreover, the unit autotriggers on waveforms whose fundamental frequency is as low as 1 Hz. Reliable autotriggering below 15 Hz is unusual. For added reliability, the unit uses no relays to select ranges, modes, or sweep speeds.
The unit's optically isolated RS-232C port continuously withstands 600V, letting you use the Model 123 with a notebook PC as a portable data logger. Even without the PC, you can capture many days' worth of data at low sweep speeds and download the data to a PC for analysis after the meter's memory is full. Even at low sweep speeds, the unit captures, retains, and time-stamps each channel's highest and lowest readings. The unit's internal batteries supply power for five hours, and the unit can run indefinitely from ac power.
--by Dan Strassberg
Fluke Corp, Everett, WA. (800) 443-5853, fax (800) 358-5342, fluke-info@tc.fluke.com, www.fluke.com.
Two new ICs for SCSI and memory-line termination offer speed and power improvements to designers striving to enhance previously unexamined aspects of their designs. One such IC, the UC5619 from Unitrode, provides 27 lines of active SCSI termination with a supply current of 100 µA during disconnect. Channel capacitance is 2.5 pF, signal integrity of which minimizes the effect on disconnected can source 900 mA terminations at interim bus points. The IC, which and sink 500 power-amplifier stage that can mA for active negation, contains a simultaneously The 4 to 7V SSOP-36 device supply full current levels to all lines. is meets hot-plug SCSI trimmed to provide 110 ohms termination impedance. It specifications, and costs $4.75 (1000). features a 10-nA hot-swap channel current,
Another IC, Micro Linear's ML-6550, aims to improve memory-bus termination. The eight-lead SOIC actively terminates as many as 40 lines by enforcing a 2.5V output for 5V systems or a 1.65V output for 3.3V designs. Compared to passive-resistor terminations, which always consume power, this termination uses power only when needed and thus typically reduces power consumption by a factor of 100, from 62.5 mW/line (2.5W total) to 0.625 mW/line (25 mW total). The active terminators also reduce bus noise as well as increase bus speed by about 10%. The device is well-suited for use with the series stub-terminated logic interface characterized by a 500-mV logic high/low difference, which memory buses clocked at faster than 100 MHz are now using. The ML6550 costs $2.03 (1000).
--by Bill Schweber
Unitrode Corp, Merrimack, NH. (603) 424-2410, www.unitrode.com.
Micro Linear Corp, San Jose, CA. (408) 433-5200, www.microlinear.com.
Until now, if you needed a less-than-$30,000 color-display DSO that could acquire 50k-point records of 1-GHz signals, you had few choices. The best known is Tektronix’s TDS 784A. Now, however, two of the three models in LeCroy’s new LC574 series offer additional choices. Although LeCroy has offered 4G-sample/sec monochrome-display DSOs for more than a year, the color-display models introduced six months ago take a maximum of 2G samples/sec. In the single-channel mode, the LC574 units raise that rate to 4G samples/sec—fast enough to capture a 1-GHz signal in real time. The $26,490 LC574A costs about 12% less than the basic TDS 784A and offers eight times the single-channel-mode capture-memory depth. What’s more, the LC574AM, which, at $29,490, still costs $505 less than the TDS 784A, multiplies the LC574A’s memory depth by a factor of five. The LeCroy scopes lack the TDS 784A’s patented InstaVu feature, however. InstaVu enables some Tek scopes to dramatically reduce the percentage of time they are “blind” to incoming signals. Also, the TDS 784A’s $2995 option 1M increases that scope’s single-channel-mode memory depth to 500k points. The LC574 series also offers some features that the Tek scopes lack and that are extra-cost options in other LeCroy scopes. One such feature is an internal printer. Another is a histogram capability that LeCroy considers to be unmatched and that, more than any other DSO feature, provides information that designers find useful in troubleshooting elusive problems, according to LeCroy. LeCroy DSOs include processor memories that are even larger than their capture memories. This feature permits much higher resolution FFTs than competitive scopes offer—to more than 6 million points. The top-of-the-line LC574-series unit, the $37,490 LC574AL, incorporates a 64-Mbyte processor memory. The other LC574 scopes offer 8 Mbytes of processor memory, expandable to 64 Mbytes. The LC574AL also includes 2M samples/channel of capture memory, which becomes an 8M-sample capture memory in the single-channel mode. In addition, all LeCroy color-display scopes use a PowerPC 603 RISC µP, which provides much quicker response to control and signal changes than do the processors of most other scopes.
—by Dan Strassberg
LeCroy Corp, Chestnut Ridge, NY. (914) 578-6020, fax (914) 578-5985, www.lecroy.com.
Tektronix Inc, Beaverton, OR. (800) 426-2200, www.tek.com
"Challengers to Intel Revisited" focuses on Intel's competitors and their threat to the leader's position in the µP market. The meeting will take place at the Santa Clara, CA, Westin Hotel at 6 pm on March 13. MicroDesign Resources sponsors the event, which features a presentation by MicroDesign founder Michael Slater, who is also publisher and editorial director of Microprocessor Report. Slater will evaluate Intel's competitors, including AMD, Cyrix, Digital, IBM, and Motorola. The event includes dinner and costs $99.
--by Kasey Clark
MicroDesign Resources, Sebastopol, CA. (800) 527-0288.
Cascade's Silicon-Intelligent CMOS standard-cell libraries include datapath and memory compilers along with core and I/O cells. The company designed each library for a specific foundry and technology. In addition, you can specify a library tuned for area, speed, or power dissipation, and you can get libraries designed for specific place-and-route tools. Each library has Verilog and VHDL HDL descriptions, a script for Synopsys (Mountain View, CA) synthesis, Spice models, and GDSII layout files.
Silicon-Intelligent includes IntelliCell core cells, IntelliPad I/O cells, IntelliMem memory compilers, and IntelliPath datapath compilers. IntelliCell core cells target place-and-route tools, covering channel- and area-based routers. The channel-based IntelliCell cells for area, power, or speed optimization work with either Cascade's Epoch physical-design tool or Cadence's (San Jose, CA) Cell Ensemble. The area-based cells for power or speed optimization work with Cadence's Cell3 or Avanti's (Sunnyvale, CA) Aquarius BV or XO place-and-route tools. You can use the IntelliPad I/O cells in many design-tool environments. The IntelliMem memory compilers use process information and your configuration specification to produce the desired memory block. Cascade has 11 IntelliMem compilers, covering single-port and multiport RAMs, high-speed and low-power RAMs, and several ROMs. The IntelliPath datapath compiler comes with cell libraries, a place-and-route tool, postlayout-floorplanning tool, and a timing verifier for the datapath blocks.
The libraries, covering approximately 70 processes from more that 20 IC vendors, will be available in the second quarter. The libraries range in minimum feature size from 0.35 to 1 µm. Prices for IntelliCell libraries for use with Epoch and Cell Ensemble start at $54,000. Prices of IntelliCell libraries for use with Cell3 and both Aquarius tools start at $100,000. Prices for IntelliPad libraries start at $57,000. IntelliMem memory compilers range in price from $36,000 to $130,000. Prices for IntelliPath datapath compilers start at $135,000.
--by Jim Lipman
Cascade Design Automation, Bellevue, WA. (206) 643-0200, fax (206) 649-7600, www.cdac.com.
The Inventor's Notebook: Second Edition by Fred Grissom and attorney David Pressman provides the tools to organize and legally protect an invention. The $19.95 paperback workbook (ISBN: 0-87337-365-0) contains instructions, worksheets, and agreements to guide entrepreneurs through the critical phases of an invention--conception, building and testing, legal protection, and marketing and financing.
Readers learn how to evaluate and refine an invention, calculate needed capital, assess the invention's commercial marketability, and create a legal record to prove they are the first and true inventor. This edition includes a section on using the Internet to develop and promote an invention, three new agreements, and a comprehensive glossary of patent terms. The book also contains numbered pages on acid-free paper to show that pages have not been inserted; shaded entry blocks to prove that entries have not been altered; and special dating, signing, and witnessing sections.
--by Beth Morrison
Nolo Press, Berkeley, CA. (800) 992-6656.
| March 10 to 12 |
| Embedded Systems Conference East, Boston, offers a comprehensive program with exhibits covering development tools, hardware, and services for embedded design. Conference costs $895. Miller Freeman Inc, Canton, MA. (617) 821-9210. |
| March 17 to 18 |
| Intellectual Property in Electronics Conference, Santa Clara, CA, addresses issues surrounding design reuse and its impact on the electronic-component and -product industry. Sessions include encryption mechanisms for intellectual property, design for reuse and resale, and emerging engineering standards for intellectual-property exchange. One-day admission costs $395; two-day cost is $650. Miller Freeman Inc, San Francisco. (415) 278-5280. |
| March 17 to 21 |
| PCB Design Conference, Santa Clara, CA, focuses on education to keep you at the forefront of pc-board design technology. The conference showcases tools, technologies, and services and costs $795. PCB Design Conference, Canton, MA. (617) 828-9185. |
| March 31 to April 2 |
| International Verilog HDL Conference (IVC-97), Santa Clara, CA, targets designers at all levels of Verilog-HDL use. The event includes sessions addressing emerging Verilog-related standards and issues relating to mixed high-level-design environments. MP Associates, Boulder, CO. (303) 530-4562. |
| EDN Access | Feedback | Subscribe to EDN | Table of Contents |