Leading Edge

March 3, 1997

EDN Europe

WHAT'S HOT IN THE DESIGN COMMUNITY

DECT processor embodies 32-bit RISC

The VWS23101 is the first in VLSI Technology's second-generation Vega family of single-chip ICs that handle all the baseband processing required for a DECT product. (DECT used to stand for "Digital European Cordless Telephone," but, because of DECT's data-communications potential--and proving that even acro-nyms can enjoy a second generation--DECT has been redefined as "Digital Enhanced Cordless Tele-communications.")

Vega devices optimise DECT baseband functionality for handsets, single-line base stations, and wireless-local-loop (WLL) terminal applications. Vega devices include a common software and hardware architecture to reduce product-development time and also double-slot functionality to support high-speed data and integrated services digital network (ISDN). Additionally, low-level medium-access-control source code eases software development and porting.

Using burst-mode logic, the Vega VWS23101 processor integrates full slot-by-slot programmability, hardware T-multiplexer functions, and support for mixed slot sizes in a single TDMA frame. The processor also enables repeater applications by being able to transmit and receive in the same half frame. In addition to core logic, the processor includes a 32-bit ARM7TDMI RISC that features low power and efficient 8-bit memory interfacing. The processor can address up to 1 Mbyte of memory, a significant advance over earlier 64-kbyte limits, and opens the path to easier development and compatibility with imminent generic-access-profile (GAP) requirements. (GAP ensures compatibility among different vendors' parts.) Vega also includes a pulse-code-modulation/adaptive differential pulse-code modulation (PCM/ADPCM) transcoder, an audio codec, and an interface for connection to any radio architecture.

The VWS23101 processor suits both terminal and base-station applications. Echo cancellation avoids the need for an external DSP, and a line hybrid links to the analogue codec or the PCM interface. The IC's core logic supports half, full, and double slots for variable data rates, and it allows your design to mix these slot types within a single DECT frame. On-chip peripherals include a UART, a keypad interface, a ringer driver, an EEPROM interface, and a PWM output for clock frequency correction.

The 100- or 128-pin TQFP IC operates on a 2.7 to 3.3V supply and consumes less than 13 mA on 3V at 32 kbps.

--by Brian Kerridge

VLSI Technology, Munich, Germany. +49 89 627060.

8-bit fuzzy-logic coprocessor interfaces with popular µPs

The 8-bit STFLWARP20/PL fuzzy-logic coprocessor--called Weight Associative Rule Processor (WARP) 2.0--allows you to exploit a fuzzy-logic design approach to high-level control systems without employing a high-performance µC or DSP. The WARP 2.0 operates as a coprocessor by interfacing with all popular µPs or as a stand-alone unit. The device suits applications such as motor control, thermal control, signal and image processing, industrial automation, and consumer products.

The WARP 2.0 includes input-fuzzification and output-defuzzification stages, a fast inferencing unit, memory for rule storage, antecedents and consequents, and control logic for downloading rules and variables. The 40-MHz device accommodates eight inputs, four outputs, and 256 rules. A key (patented) feature stores membership functions in dedicated on-chip memories, which allows the device to compute a complete (eight inputs, four outputs, 256 rules) fuzzy process in 200 µsec.

Performance also benefits from an architecture that optimises data structures to computation stage. This arrangement overcomes the limitation whereby data structures that suit fuzzification do not suit defuzzification and vice versa. WARP 2.0 costs $10 (500).

You can obtain design support for the WARP 2.0 by using the Fuzzystudio 2.0 development system, which uses graphical-design techniques and includes advanced editing, debugging, and compiling tools.

--by Brian Kerridge

SGS-Thomson Microelectronics, St Genis Pouilly, France. +33 50 40 25 58.

Single-chip echo canceller has 32 channels

The TECO3264 echo-cancellation IC is the first in a new family of ICs for synchronous-digital-hierarchy/synchronous-optical-network systems working on line data rates from T1/E1 (1.554/2.048 Mbps) to STM-4/OC-12 (622 Mbps). The device provides 32 channels of echo cancellation with an echo- return-loss enhancement of 34 dB and can accommodate tail-end delays up to 64 msec. The IC particularly suits central office subsystems and digital wireless base-station applications and can replace existing individually controlled channel designs based on multiple DSPs and ASICs.

The echo canceller provides fast and slow convergence modes to achieve rapid cancellation followed by stable control of the echo estimate to prevent divergence. You can program gain and non- linear processor attack in each mode. The nonlinear processor itself has immediate and soft modes. Immediate mode instantly substitutes noise-matching samples for the echo sample. The soft mode ramps in loss at a programmable rate and level prior to full noise matching; operate time is programmable from 0 to 128 msec in 125-µsec steps.

The IC operates with Intel or Motorola mP interfaces and has optional serial-control inputs. I/O conforms to the concentration highway interface standard, in 2.048- or 4.096-Mbps mode and has programmable bit and time-slot offsets.

The TECO3264 consumes less than 30 mW/ channel (available in production volume by April).

--by Brian Kerridge

Lucent Technologies, Bracknell, UK. +44 1344 865910.