March 14, 1997

Growing your own IC clock tree

Jim Lipman, Technical Editor

Defining the clock-distribution network is one of the most difficult aspects of high-speed, system-on-a-chip design. Employing the right design methodology helps you "beat the clock."

The design of a good clock-distribution network, or "tree," for a high-performance chip requires good IC-engineering skills. You define your chip's specifications for speed, power, and other factors and then integrate the clock-tree design into your normal chip-design flow. Although you need to define the kind of tree you want up front, there are some EDA tools available to synthesize the tree and verify its performance before committing the design to silicon.

The art of designing clock-distribution networks for high-speed chips is far more complex than just meeting timing specifications. Achieving clock latency and skew goals is difficult enough when you have clock signals of 100 MHz or more transversing the chip, but there are other factors besides speed. Because the clock network is one of the most power-hungry nets on a chip, you need to design with power dissipation in mind, particularly for chips used in portable equipment. The dynamic-switching current flow that causes high power dissipation can also lead to interconnect reliability problems, so you have to consider clock-tree wire widths. As if all these considerations were not enough, there is also the potential for clock-to-signal-net coupling that may result in excessive on-chip noise.

Clock-tree basics

The major task of clock-tree design is developing the interconnect geometry that connects the clock to all the cells on the chip that use a clock. These cells consist of latches, flip-flops, and other logic elements that you need to synchronize with the system clock. For clock-tree design, your major concerns are minimizing clock skew and optimizing clock buffers to meet skew specifications and minimize clock-tree power dissipation.

Variations in the clock signal's arrival time at the clock inputs of various logic elements cause clock skew. The skew is a function of two parameters: the loading of logic being clocked and the RC delay of the clock-line interconnect (Figure 1). The primary job of clock-synthesis place-and-route tools is to vary routing paths and placement of the clocked cells and clock buffers to meet maximum skew specifications.

You can choose from various clock-tree structures, including the H tree, clock grid, and balanced tree (Figure 2). You manually design the H tree, used mostly in custom layouts, and vary tree interconnect-segment widths to balance skew throughout the chip. The clock grid, also manually designed, is the simplest clock-distribution structure and has the advantage of being easy to design for low skew. However, it is area-inefficient and, even worse, power-hungry because of the large amount of clock interconnect it needs. Still, some chip vendors are using this clock structure; Digital Equipment Corp (Hudson, MA) uses a clock grid for its 300-MHz Alpha 21164 processor (Reference 1). You can implement the balanced tree, the most common clock-distribution network for high-performance chips, with the aid of clock-synthesis tools.

For a balanced tree without buffers, the clock lines' capacitance increases exponentially as you move from the leaf cell (clocked element) to the root of the tree (clock input). The extra capacitance results from the wider metal needed to carry current to the branching segments. The extra metal also results in additional chip area to accommodate the extra clock-line width. Adding buffers at the branching points of the tree significantly lowers clock-interconnect capacitance, because you can reduce clock-line width toward the root (Figure 3).

Clock-tree design considerations

When designing a clock tree, you need to consider performance specifications that are timing-related and that affect other chip-design goals. Clock-tree timing specifications include clock latency, skew, and jitter. Nontiming specifications include power dissipation (static and dynamic), signal integrity (noise due to clock-to-signal coupling), and reliability (primarily due to electromigration effects in clock lines). Many clock-design issues affect multiple performance parameters; for example, adding clock buffers to balance clock lines and decrease skew may result in additional clock-tree power dissipation.

Clock-induced delay, or clock latency, lengthens hold times and stretches clock-to-data-out times. Although designing for a maximum clock latency is important, you also need to consider a minimum latency for multiclock chips to minimize skew across clocks. (Some clocks may have much less latency than do others.) Most high-performance chips use a PLL between the clock input and a reference point on the chip (one of the clocked elements) to minimize latency. You use the PLL to shift, not "create" time, so you can reduce latency to the reference point, but you cannot affect clock skew with the PLL.

Looking at a balanced-tree clock-distribution network in more detail (Figure 4), you see buffers, which may be several layers below the main clock input, driving the clocked elements. Each split of the tree interconnect, or branch, results in an additional clock-tree-buffering layer. As a clock-tree designer, you need to specify the clocked-element cluster size and number of clock-tree levels. You also need to match the drive of a clock driver to the elements it is driving (either additional clock-tree interconnect segments and buffers or the chip's clocked elements). Typically, you need no more than three or four clock-buffer layers to design a balanced tree using a good clock-synthesis tool. Figure 4 also shows clocked-element clustering (with a cluster size of two in this figure), with a clock buffer of adequate drive strength driving each cluster.

Because the biggest problem you face in designing clock trees is skew minimization, you should be aware of how significant the problem has become for today's leading-edge chips. The factors that contribute to clock skew include loading mismatch at the clocked elements, mismatch in RC delay due to clock-line segment-width and -length variations, and process variations induced during chip fabrication.

Clock skew adds to cycle times, reducing the clock rate at which a chip can operate. Typically, skew should be 10% or less of a chip's clock cycle, meaning that for a 100-MHz clock, skew must be 1 nsec or less. High-performance µPs may require skew to be 5% of the clock cycle, or 250 psec at a 200-MHz clock rate.

Data-dependent skew is another problem. How data flows throughout, as well as on and off, the chip determines the level of on-chip switching activity. Switching activity is particularly critical for output drivers sending signals off chip, because the drivers draw a lot of current. As output buffers switch, they cause fluctuations in the current flowing through the chip's power and ground buses. These current variations affect logic-cell performance, including clock buffers whose delay and drive strength can vary with shifts in V_DD and ground. Thus, clock skew can change because of on-chip data activity. Improving the robustness of your power grid can help eliminate any data-dependent skew problems. Similarly, packages with "stiffer" power and ground metallization can also help. This stiffer metallization is why PGA and similar packages minimize data-dependent skew better than do less expensive QFPs.

Clock-design methodology

Many ASIC and chip companies have comprehensive clock-network- design strategies that they use on their customers' chips. IBM Microelectronics designs many chips that require leading-edge clock-tree designs, for which the company takes a two-pronged, clock-tree-design approach. IBM engineers first use a tool called Clock Pro to develop the clock-tree skeleton (Reference 2). Clock Pro takes designer-supplied constraints, such as maximum clock skew and latency; performance parameters of available clock-driver cells; and external chip information, such as worst-case temperature and voltage. With this information, Clock Pro outputs all clock-tree combinations, sorted by latency, that can meet timing constraints. To help balance the tree and reduce skew, the tool can also include single-pin terminator cells that come in four capacitance "sizes." In addition, Clock Pro varies terminator-cell capacitance and location for balance control (Figure 5).

IBM uses Clock Pro on chips with multiple clock domains. IBM engineers see an average of 10 clock domains fed by one clock tree on a single chip. Multiple clock domains on a chip have become more prevalent with the increase in core-based chip designs, because each core may have its own clock. Besides including additional complexity to skew control over the entire chip, you may need to synchronize some clocks to the master (system) clock, but with a "late" or "early" factor added. You can synchronize those clocks by inserting fixed delays into some portions of the clock tree.

IBM's chip customers select the desired clock tree, taking into consideration clock-tree depth, latency, total buffers added, and power dissipation. The customer then synthesizes the tree using an internal IBM synthesis tool. After synthesis and during placement and routing of the clock-tree elements, the customer optimizes the tree with another IBM tool to drive the clocked elements with minimum interconnect length, skew, and latency. Clock-tree targets for IBM engineers are skew of 5% or less of clock-cycle time, a tree that drives as many as 150,000 clocked elements on a chip, and clock frequencies as high as or higher than 300 MHz. For final verification, a 3-D extraction tool based on a proprietary algorithm extracts the clock tree's RC parasitics. The customer then simulates the extracted database to verify that the tree meets timing specifications.

Motorola uses the Clock Generator tool along with Avanti or Cadence place-and-route tools. The tool combination produces a tree with minimum insertion delay, a minimum number of buffers, and maximum fan-out based on customer-input edge-rate specification. Typical skew is less than 300 psec. Most designs require a two-level clock tree; none needs more than four levels. Most of Motorola's customers' chips have four to 10 clock domains, although the company has designed chips with as many as 56 domains. Clock Generator estimates wire lengths using a process-technology file and a statistical wire-load model. Motorola plans to integrate clock-tree tools into its floorplanning tools to get better wire-length estimates.

After generation of the clock tree, the output from the place-and-route tool is flat, meaning that the design hierarchy is lost. Motorola has Merge DB, a tool that re-creates the hierarchical database, including the clock tree. A hierarchical database speeds design verification with extraction and timing tools.

Toshiba uses its Clock Tree Synthesis (CTS) tool with Cadence's Gate Ensemble or Cell3 place-and-route tools to do automatic clock-tree synthesis and placement for customers' chips. CTS clusters the clocked cells and matches interconnect-RC delay for balanced-tree routing, creating an output file annotated to the circuit file that the router uses (Figure 6). Toshiba typically achieves a clock skew of less than 100 psec when using CTS on chips with maximum clock frequencies of 100 to 125 MHz.

Clock-tree design is an important part of chip design for these and other high-performance chip vendors and ASIC suppliers. Although each company uses a different combination of third-party and internal tools and design styles, all integrate clock-tree design into the overall chip-design flow. Results for today's leading-edge chips are satisfactory. But with 500-MHz clocks and 0.18-mm process technology on the horizon, semiconductor and EDA vendors will have to make advances in software and design techniques to successfully manage clock-distribution networks for tomorrow's chips.

References

1. Desai, Madhav, Radenko Cvijeic, and James Jensen, "Sizing of clock dis-tribution networks for high perform-ance CPU chips," Design Automation Conference Proceedings, June 1996, pg 389.
2. Rincon, Ann Marie, Michael Trick, and Thomas Guzowski, "A proven methodology for designing one-million-gate ASICs," Custom Inte-grated Circuit Conference Proceedings, May 1996, pg 45.
3. Lipman, Jim, "EDA tools let you track and control CMOS power dissipation," EDN, Nov 23, 1995, pg 65.
4. Tanizawa, Tetsu and Sigeki Kawahara, "Clock driven design method (CDDM) for deep sub-micron ASICs," ASIC Conference and Exposition, September 1995, pg 241.
5. Pullela, Satyamurthy, Noel Menezes, and Lawrence Pillage, "Low power IC clock tree design," Custom Integrated Circuit Conference Proceedings, May 1995, pg 263.
6. Wu, Qing, Massoud Pedram, and Xunwei Wu, "Clock-gating and its application to low power design of sequential circuits," Custom Integrated Circuit Conference Proceedings, May 1997.

Acknowledgments

Thanks to Gopi Ganapathy of Silicon Valley Research for his discussion and white paper on clock-tree synthesis and to Rob Mathews of Frequency Technology for his material on interconnect inductance effects.

Jim Lipman, Technical Editor You can reach Jim Lipman at (510) 606-1370, fax (510) 606-1563, ednlipman@mcimail.com.

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