March 14, 1997

PLL SYNTHESIZERS
make channel-hopping swift and sure

BILL SCHWEBER, TECHNICAL EDITOR

Wireless systems for cellular and PCS applications must quickly and accurately switch channel assignments. New PLLs minimize some of the traditional trade-offs involved.

Some PLL frequency synthesizers have it easier than others do. PLLs for fixed-frequency operation, such as PC clock generation or data-link clock recovery, have it easiest. PLLs for channel selection in standard broadcast-band TV or AM or FM radio have a harder time, but these PLLs have wide channel spacings, infrequent changes, and reasonable accuracy tolerances. Also, settling times to the new carrier frequency can be tens or hundreds of milliseconds.

In contrast, PLL synthesizers for wireless applications have a much harder time. These PLLs include models for cellular phones--whether AMPS (Advanced Mobile Phone Service), TDMA (time-division multiple access), CDMA (code-division multiple access), or GSM (Global System for Mobile Communications)--or frequency-hopping spread-spectrum links. Channel spacings are close, tolerances are critical in the gigahertz region in which the PLL synthesizers operate, and channel assignments dynamically change during an established call or link, so lock-in performance must be quick--within milliseconds or less--yet with minimal overshoot.

The basic problem is that your requirements for accuracy and low noise (however you define them in your application) fundamentally conflict with the need for fast switching to, and locking at, the new carrier frequency. Meeting the conflicting requirements for these applications requires careful PLL-synthesizer design and integration. To achieve your goals, you can implement the PLL in a discrete design of individual functional blocks in one IC with a few external components or embedded within a larger system IC.

Start with analysis

The PLL is a relatively old function in electronics, dating back to the 1920s and '30s (see box, "Basics are timeless"). You can model and mathematically analyze the PLL in detail as a closed-loop control system (References 1 and 2), which is both good and bad news. Dozens of books and hundreds of academic papers are available on every aspect and subtlety of PLL architecture and operation, covering common and unusual approaches, signal types, and noise. Unfortunately, many of these analyses deal with PLLs as abstract or theoretical functions, and they rarely show any actual circuit schematics or the component values you need to build these devices. In these analyses, the authors determined the results' validity by simulation rather than by circuitry, test equipment, and measurement.

This fact doesn't mean that you should skip the analysis or classical control-system techniques (Reference 3). Bode plots illuminate the trade-offs in phase noise, and Laplace transforms show the dynamics of lock-in time; both can show the effect of noise in the system.

However, you need to produce a circuit that works. For your application, begin by defining operating frequencies, step size (frequency spacing between adjacent synthesized values), maximum phase and spurious noise that you can accept, and required time to lock when the synthesizer jumps to a new frequency.

Build, buy, or avoid a PLL

You can achieve the best overall performance but at the highest cost in components and design time, if you build a PLL from distinct functional blocks. This approach provides you with the most versatility in component selection, the greatest flexibility in architecture, and the best opportunity to manage trade-offs. You can, for example, use a VCO that is highly linear over a wider range than you can with a VCO that is part of a larger IC. However, your analysis becomes complex, and you need thorough static and dynamic specifications for each device. You then take these specifications and build a model of the PLL design, so you can explore the trade-offs, especially as you factor in real-world shortcomings, nonlinearities, and noise.

As an alternative, you can use more highly integrated PLL components that offer more functions and greater overall system-performance characterization, but with fewer degrees of freedom (which is not necessarily a bad thing). Many of these PLLs are designed with frequency range, step size, and performance tailored to the requirements of a communication application (Figure 1). Although these PLLs are usually noisier than are more discrete designs, their performance may be sufficient, and their power consumption is far less than these other designs.

Recognize that the integrated PLL may be incomplete, requiring a few passive components for full operation. You almost certainly have to add the loop filter, because integrated filters have lower Qs than discrete passives offer. Check carefully to see what active devices you need to add to the PLL IC, in addition to the passive devices. Though integrated PLLs have many of the necessary active functional blocks, they may forgo some others, such as the VCO, which is especially sensitive to thermal, 1/f, and power-supply noise. These noise sources modulate the VCO's uncorrected, open-loop frequency, and the frequencies of the resulting disturbances may be outside the loop's ability to correct.

Although highly integrated ICs may not perform as well as the carefully constructed discrete designs, they may be all you need for many communication applications. Unlike test applications, for example, in which improved performance in the synthesizer block is usually desirable, communication applications usually don't benefit from exceeding a mandated specification.

The easiest PLL synthesizer for you to use is one that embeds the PLL function within a larger, usually digital, IC. This PLL needs no external components or, at most, only a few passive ones. Unfortunately, although such a PLL is effective for fixed-frequency applications, such as timing recovery or clock generation, its performance is usually inadequate for the stringent needs of most cellular, spread-spectrum, and similar systems. Whether you choose to build with discrete ICs or use complete PLL ICs, be aware of different architectures (see box, "Consult an architect before building").

The trend toward lower voltage and 3V operation has had a mixed impact on PLLs. The lower power of these circuits helps reduce noise levels and, thus, has the potential to improve performance. However, the reduced voltage also makes tuning the VCO over a wide range more difficult unless you increase the loop and VCO gain. Gain increases, in turn, increase noise and system sensitivity to VCO and charge- pump nonlinearities and may increase phase noise. Short lock time, another desirable feature, usually requires increased slew and charge-pump rates, which are harder to achieve at lower voltages; however, some of the newer process technologies and circuit topologies have overcome this constraint.

New parts rewrite old rules

The PLL's traditional performance trade-offs are under attack by high levels of integration coupled with new processes. Consider power consumption, which has fallen to about one-tenth of its previous value in just a few years. For example, Fujitsu's MB15E03L 2.5-GHz device requires just 3.2V at 2.5 mA, and you can get high-performance PLLs that operate at 1.5V for use in pagers.

Many PLLs now offer a sleep mode, which reduces consumption to a few microamperes. This option is useful for equipment such as cellular phones, in which the receive channel is always on but the transmit channel is needed only when a call is in process.

Vendors are also simplifying the PLL's interface to the system processor and reducing the size of the more integrated PLLs. They are accomplishing these goals by incorporating serial ports that allow direct control over key loop parameters, such as the divide ratio, and adding synchronization circuitry that prevents spurious PLL-output values during transitions from one value to another.

Dual PLLs that incorporate independent PLLs--one for the RF-tuning stage and the other for the IF stage--are available from several vendors. The dual devices reduce power consumption and size by sharing a control interface as well as some other internal functions. Although crosstalk between PLLs in a dual device can degrade perform-ance, this problem is much smaller in the newest ICs; their performance below approximately 1 GHz compares to that of many single PLLs. The LMX233x trio of dual synthesizers from National Semiconductor Corp (with an RF PLL at 1.2, 2.0, or 2.5 GHz and a second PLL at 510 MHz) features a phase-noise floor of ­169 dBc/Hz, compared with ­160 dBc/Hz for the company's single versions.

Vendors have also addressed the long-standing conflict between phase noise and lock time. Dual loop-time-constant designs are not new; they use a wider bandwidth filter during the step period and then switch to a narrower filter to reduce noise once they reach the final value. However, there is more to proper operation than simply switching filters, because you have to know when to switch filters as well as maintain loop gain at a constant value. PLLs in the LMX233x series automatically switch from a wideband filter to a narrow filter after a preset time; simultaneously, these PLLs switch the phase-detector gain, thus maintaining the same overall loop gain and phase margin, which eliminates switching errors.

Vendors are also looking at ways to achieve increased integration beyond the PLL synthesizer, yet with minimal performance compromise. Fujitsu's Versi-Tile macro array contains PLLs, a VCO transistor, and other analog blocks for RF and IF stages, which let you incorporate more of the system functions in one IC.

Fortunately, to support the PLL's virtues and irreplaceable features, IC vendors supplement circuitry with supporting documentation, application notes, and real-world designs. For example, Motorola offers application notes that look at design analysis and architectures (Reference 4). Further, Motorola offers Excel templates that let you set up spreadsheets for interactive frequency planning (DK305/D) and lock-in-time analysis (DK306/D). Fujitsu Microelectronics offers an evaluation combination of RF boards for various PLLs, a digital interface board, and DOS software. You can then load and operate the PLL from the PC's parallel port via the interface board, changing channels and measuring lock-in times, phase noise, and current drain.

Companies other than PLL-device vendors support analysis as well. Hewlett-Packard EEsof Division de-signed the HP 85148A Circuit Envelope Simulator to overcome the difficulties of modeling PLLs. Time-domain simulators require many steps and, thus, long simulation times for the combination of high frequencies, long time constants, and phase comparison of arbitrary signals; frequency-domain simulators are ill-suited for PLL transients. The HP software combines proprietary modeling techniques to handle modulated and feedback signals, such as those in PLL designs.

References

1. Gardner, FM, Phase Lock Techniques, Wiley & Sons, New York, 1967.
2. Viterbi, Andrew J, Principles of Coherent Communications, McGraw-Hill, New York, 1966.
3. Nash, Garth, "Phase-locked loop design fundamentals," Motorola Application Note AN535, July 1993.
4. Smith, Morris, "An improved PLL design method without lowercase omega_n and lowercase zeta," Motorola Application Note AN1253, May 1995.
5. Smith, Morris, "Offset reference PLLs for fine resolution or fast hopping," Motorola Application Note AN1277, July 1996.

Acknowledgments

Thanks to Dan Clementi of Focus Semiconductor, John Salvey of Fujitsu Microelectronics, Robert Hall of Motorola Semiconductor, and Bill Keese of National Semiconductor Co for their insight and comments.

BILL SCHWEBER, TECHNICAL EDITOR You can reach Bill Schweber at (617) 558-4484, fax (617) 558-4470, e-mail bill.schweber@cahners.com

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