March 14, 1997

FIFO memories supply the glue for high-speed systems

Markus Levy, Technical Editor

System designers have long used FIFO memories to couple subsystems with disparate data-transfer rates. Recently, new types of these devices--with new capabilities--have emerged. Know your FIFO choices before you start "gluing" your next system together.

Although lacking the glamour of µPs and DSPs, buffers are essential for providing the glue logic that binds high-performance systems. These systems use buffers to delay data streams between two asynchronously operating subsystems. FIFO memories appear in many applications, including telecommunications, digital signal processing, medicine, printing, and networking systems. For example, a FIFO buffer can hold analog-to-digital samples before a DSP processes them. Alternatively, a host processor can use a FIFO buffer for passing instructions to a DSP or a coprocessor. In addition, a network system can use a FIFO buffer to hold a data packet before interrupting the host processor.

A FIFO buffer is a self-addressing, data-storage device whose incoming data rate typically differs from the outgoing data rate. Vendors describe a FIFO buffer's basic architecture as data depth×data width. Modern FIFOs use dual-port SRAMs with internal organizations as circular buffers with separate read and write pointers that count up to the FIFO's depth. Even if the FIFO-memory array is not a dual port, the device must still function as a dual-port device because reads and writes must occur simultaneously to enable true asynchronous operation. Although a modern FIFO offers many performance benefits, its dual-port design limits its density to about one-quarter of an equal-sized standard SRAM.

The number of discrete FIFO-memory choices can be overwhelming (Figure 1). FIFO vendors offer a variety of depths, widths, speeds, and features (Table 1). However, the most important criterion when selecting a FIFO device is depth. Generally, the deeper the FIFO, the lower the cost per byte, but this situation is not always true. Often, the technology, speed, feature set, packaging, and other product aspects have a key influence on price. Regardless of price, you must choose the FIFO depth to match the incoming and outgoing data rates. A FIFO that is too small for the application can overflow and cause data loss. FIFO depths range from 64 bytes to 32 kbytes.

Another criterion is width. Standard widths range from 9 to 36 bits, although a few FIFO devices come in 1-, 4-, and 5-bit widths. In many applications, the datapath widths differ on each side of the FIFO memory. Some vendors implement a bus-matching feature on a few of their high-end, non-industry-standard FIFO buffers. Bus matching, or funneling, lets you use pins on the device to select a bandwidth. For example, using this feature, you can select the FIFO's data input to be 36 bits wide and its output to be 9 or 18 bits wide. If you're set on using industry-standard FIFO buffers, you can implement a bus-matching feature by alternating between two FIFO devices. However, this approach requires extra control logic.

You must hardwire bus-width selection for most bus-matching devices. However, with some devices, such as Texas Instruments' internetworking FIFO buffers, you can dynamically select a 9-, 18-, or 36-bit bandwidth. You must make the bus-size selection one cycle before the selection takes effect. This one-cycle latency lets the FIFO set up the control logic before the next transfer, resulting in shorter setup and hold times for these inputs. The latency also allows the device to compare the previous bus-size input state to determine whether your system actually requested a bus-size change or whether the pins toggled because of noise.

Other choices you must make when selecting a FIFO device include the number and direction of datapaths. Vendors typically specify the direction of data flow as unidirectional or bidirectional. Higher integration is making it easier for vendors to include more than one FIFO buffer within a device. Dual FIFOs are common. Integrated Device Technology (IDT) recently announced a triple-FIFO product that contains one 36-bit, bidirectional FIFO buffer and two 36-bit, unidirectional buses.

Data-transfer mechanisms are also important when choosing a buffer. Generally, vendors classify the FIFO data-transfer mechanisms as asynchronous, synchronous (or clocked), or strobed. Except in low-performance systems, synchronous devices have all but replaced their asynchronous counterparts, because synchronous devices offer far better noise immunity than do the asynchronous versions.

In systems lacking a clock, designers can use strobed FIFO devices, which accept or output a data word at every rising or falling edge of the write or read clock, respectively. During writes, a Full signal indicates whether the memory has space for another data word. Similarly, an Empty signal indicates whether your system can read a data word. The disadvantage of a strobed FIFO device is that it cannot fully synchronize the status signals with the corresponding clock signals.

Most clocked FIFOs require separate, free-running read and write clocks; a system uses the read- and write-enable signals to control reading and writing. The input- and output-ready status signals indicate the internal state of the FIFO. The two free-running clock signals enable the FIFO to internally synchronize all the status signals. Some FIFO devices, such as the synchronous line buffers from Motorola, have only one clock. Although these line buffers have separate read and write counters, they don't offer flag support or other FIFO functions and serve mainly as inexpensive data buffers.

Although, theoretically, clocked FIFOs are also synchronous, TI makes a subtle distinction between the two types. The company's synchronous FIFOs write (read) data on the rising edge of the write (read) clock when the system asserts the write (read) enable input and the input (output) ready flag is not asserted. Furthermore, the full (empty) flag is single-stage synchronized to the write (read) clock. Clocked FIFOs are similar, except that during writes or reads the system sometimes (depending on the device) asserts the chip select, and the input (output) flag is multistage synchronized to the write (read) clock. Clocked FIFOs also support the first-word fall-through feature, whereas synchronous FIFOs delay reads of the first word written to a previously empty FIFO by one clock cycle.

FIFO flags

FIFO devices also use flags to indicate internal status. The full flag (FF) and empty flag (EF) are the most common status signals available on most FIFOs. Other flags include almost-full (AF), half-full (HF) (though some people see the FIFO as half-empty), and almost-empty (AE).

On some FIFO buffers, you can program the position of the AF and AE flags. You can use these flags to warn when data is approaching underflow or overflow conditions. The level you set should provide the system with ample time to react. You can also use the programmable AF and HF flags as block-length counters or to schedule DMA operations; the flags interrupt the system µP or DSP when a data packet is available for transfer or when space is available to receive a packet transfer.

You can perform the DMA operation with fixed- or variable-length packets. For fixed packet length, you must set the programmable FIFO flags to show when the FIFO is ready to transmit or receive a packet. For variable-length packets, your system hardware generally needs to use DMA synchronization for FIFO control. In this case, the programmable flags indicate when the FIFO has stored a portion of the data packet or when a portion is available in the FIFO. This DMA synchronization prevents FIFO overflow and underflow but requires several processor interrupt lines.

One flag-related issue may arise if a system violates setup and hold times on a FIFO device. This situation may generate a metastable condition. Although most FIFO buffers rely on single-stage synchronization for reducing metastable events, TI, IDT, and Sharp FIFOs include multistage synchronization in which the FIFO synchronizes its status flags to the clock through two or three flip-flop stages. If the first synchronizer does not resolve the metastable condition because of violation of setup and hold times, then the second and third stages are more likely to resolve it.

Thus, from a theoretical perspective, multistage synchronization helps improve system reliability, although from a practical perspective, single-stage flag buffering provides adequate performance. Additionally, some FIFO vendors question whether the added benefit of multistage synchronization is worth the extra cycle of delay.

On clocked FIFOs that support first-word fall-through (FWFT), the FIFO asserts its output-ready (EF) signal when the data latches onto the output bus. With FWFT, a word in an empty FIFO automatically shifts to the FIFO's output register. This approach allows the processor to read the data without incurring wait states, increasing overall FIFO throughput with burst data. On FIFO devices without FWFT, the FIFO asserts its output-ready signal before data is available at the output; the processor may have to wait one or more cycles.

Sometimes, a system must provide a repeated data sequence to a processor, such as when a DSP performs a FIR filter. Several FIFO memories let you reread stored data. When the FIFO enters the retransmit mode, the device prevents ongoing FIFO operations from overwriting existing data. The retransmit feature of some devices allows you to begin a reread only at physical-address zero. However, others, including some from Motorola, Sharp, and TI, let you mark a logical-location zero to which the FIFO automatically returns. When a FIFO supports no retransmission ability, a software programmer has to write many copies into the FIFO to duplicate the data.

FIFO devices are available in many depths and widths, and you can further expand those options by combining FIFO devices to create deeper or wider datapaths (Figure 2). You can create deeper datapaths, called "cascading," or "depth cascading," using either two-wire token passing or pipelining--also called "handclasping."

Sharp's LH5402×5 and IDT's 722-×5B FIFOs use the two-wire, token-passing method. You must combine the input and output data buses; however, you can simultaneously write or read from only one of the paralleled FIFOs. A data word passing through the FIFO subsystem passes through only one physical FIFO device, which handles the word just once. A single-clock latency is the advantage of this method, whereas the disadvantage is the electrical pin loading due to tying the buses together.

The SN74ACT7801 from TI and the LH5402×5 from Sharp use the pipelining method, combining two or more devices in series. The devices use a cross-coupled handclasp-signaling scheme between successive FIFOs that allows them to properly coordinate operations with each other. This scheme ensures that the upstream FIFO device does not attempt to force another data word upon the downstream FIFO device when the downstream device is full and vice versa for reads when the device is empty. The dis-advantage of this scheme is that a data word must pass through every physical device. The overall latency is the sum of the latency through each FIFO.

You can create wider datapaths by "width cascading," putting two or more FIFO devices in parallel. For example, Sharp's LH5402×5 supports an interlocked paralleling scheme in which two side-by-side FIFOs operate in lock step.

Mailbox-bypass register

Several FIFO devices contain mailboxes that sit in parallel with the datapath. You can use these mailboxes to store messages, such as status, commands, and configuration information. These FIFO devices must also include a flag to indicate when mail is available. In addition, when the FIFO sets a mail flag, the device should ignore attempted writes to the corresponding mail register.

Another feature, byte swapping, allows a FIFO to support big- and little-endian formats by taking 18- or 36-bit data and swapping the bytes.

Besides offering discrete FIFO devices, some manufacturers hide FIFOs within ASICs such as PC chip sets, PCI-to-PCI bridges, network controllers, and many more. You can also integrate a FIFO into a custom ASIC or FPGA if the logic gates are available. This approach is especially useful if you need only a small FIFO and have board-space constraints. However, the FIFO control logic, especially flag support, may present a design challenge. To assist you in designing an integrated FIFO, companies such as VLSI Libraries provide synthesizable Verilog code for various memory models. You can wrap controller logic around one of these Verilog models, a dual-port memory, to create the FIFO features that you need.

Improving process technologies allow vendors to continue to provide higher density, faster, and more highly integrated FIFOs. However, some vendors are taking the opposite route and are "de-featuring" their FIFOs to lower costs. But, regardless of the FIFO implementation, these devices will become increasingly important in designs as data-transfer rates between asynchronously operating subsystems continue to increase.

References

1. High-Performance FIFO Memories, Designer's Handbook, Texas Instruments, 1996.
2. Application Notes, Sharp, 1994.

Markus Levy, Technical Editor You can reach Markus Levy at (916) 939-1642, fax (916) 939-1650, markuslevy@aol.com.

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