March 14, 1997

WHAT'S HOT IN THE DESIGN COMMUNITY

Edited By Fran Granville

Imaging system displays temperatures as full-motion videos

Designers of ICs, multichip modules, and pc boards often need to know how hot regions or elements get during the critical milliseconds after power turn-on. A new thermal-imaging system from Flir Systems provides that information in full-motion video with better resolution than was previously possible. The system transforms temperatures into user-defined colors. Time-lapse techniques can slow the action to provide thermal-stress data that is not otherwise obtainable.

Flir built the system around off-the-shelf PC hardware running Windows 95. The Tracer system uses this hardware to provide temperature resolution as fine as 0.1°C at 30°C and to capture data at 60 frames/sec--double the rate of earlier systems. Moreover, prices begin at $69,000 for a system that includes a focal-plane- sensor-based IR camera, thermal-analysis software, and a 166-MHz Pentium PC with hard-disk capacity of 4 to 18 Gbytes or more. An 18-Gbyte system can record more than 20 minutes of uncompressed 12-bit data at 60 frames/sec. Although Flir offers portable (lunch-box) and desktop configurations, the company has seen the greatest interest in the portables.

--by Dan Strassberg

Flir Systems, Portland, OR. (503) 684-3731, fax (503) 884-3207, www.flir.com.

LVDS drivers/receivers hit 400 Mbps

To provide high-speed, low-power data links over dedicated paths at distances as great as 10m, designers are moving beyond single-ended TTL/CMOS and RS-4xx-compatible links. Low-voltage differential-signaling (LVDS) serial interfaces (ANSI/TIA/EIA-644) with ±350-mV output swing can achieve speeds of 400 Mbps and higher, depending on distance, media, and drive.

A family of LVDS drivers/receivers from National Semiconductor targets applications such as intraboard, interboard, and interbox interfaces for digital video links; high-speed printers; flat-panel displays; and point-to-point router and hub links. The 5V DS90C401 dual driver and DS90C402 dual receiver for speeds greater than 155 Mbps, along with the 3V DS90LV017 single receiver and DS90C27 dual receiver for speeds as high as 100 Mbps, transition between onboard TTL-level circuitry and LVDS paths. The receivers feature a fail-safe input design to prevent oscillation of an unplugged input. Prices for the eight-lead SOICs begin at $1.40 (1000) for the 3V single receiver.

Not all applications require such high rates, however, but they do need low-voltage operation. National's DS26LV31 and DS34LV86 ICs quad drivers and receivers, respectively, comply with the RS-422 standard and operate from a 3V supply. They can interface with the more common 5V RS-422 devices and provide data rates as high as 32 Mbps. Each $1.10 (1000) driver requires 500 µA of supply current, and each $1.55 (1000) receiver requires 8 mA.

--by Bill Schweber

National Semiconductor Corp, Santa Clara, CA. (800) 272-9959, www.national.com.

Bandwidth busters meet the DRAM market

Announcements from Mosel Vitelic and Samsung Semiconductor show that each targets a price/performance convergence point in striving to meet the needs of today's high-bandwidth code and data applications. Mosel Vitelic's 256-kbit V53-C16258H extended-data-out (EDO) DRAM has a ×16 datapath and offers page-mode access as fast as 12 nsec (equating to an 83-MHz clock rate), roughly twice as fast as today's mainstream EDO DRAMs.

Equally significant, the memory's random-access time is 30 nsec. Consecutive code fetches are often highly sequential, making burst-mode cache-line fills effective. However, data reads and writes exhibit significant randomness, lowering the page-mode performance potential of DRAM, SDRAM, and synchronous graphics RAM (SGRAM). Data-intensive buffer applications include 3-D PC graphics, CD-ROM, hard-disk-drive caches, set-top-box MPEG video streams, and networking. The manufacturer claims that, in such designs, the 83-MHz V53C16258H is a higher bandwidth, more cost-effective alternative to 100-MHz SDRAM and SGRAM. Package options include 40-pin SOJs and 40- and 44-pin TSOPs; price is $4 (1000).

Samsung Semiconductor pioneered SDRAM-II, which delivers data on both the rising and the falling edges of the memory bus clock, thereby doubling effective bandwidth at a given frequency (Table 1). This approach, "double-data rate," extends the performance of today's SDRAM via targets of 1.6 Gbytes/sec at 100 MHz and 2.4 Gbytes/sec at 150 MHz with a 64-bit data bus and page-mode accesses.

SDRAM-II leverages semiconductor technology and test-and-assembly techniques, packages, and pinouts, resulting in aggressive pricing and relatively smooth design migrations. Samsung positions SDRAM-II as an open architecture without royalties, has presented it to the Joint Electronics Device Engineering Council (JEDEC), and hopes to receive standardization this year. First samples of the 64-Mbit SDRAM-II in TSOP-II and BGA packages should emerge in the fourth quarter of this year, targeting mid-1998 PC and embedded-system designs.

--by Brian Dipert

Mosel Vitelic, San Jose, CA. (408) 433-6000.

Samsung Semiconductor, San Jose, CA. (408) 954-7000.

Building the “right” PowerPC

PowerPC developers Motorola and IBM are still hoping to deliver the "perfect" product. Toward that end, the team announced the G3 PowerPC at February's International Solid State Circuits Conference (ISSCC) in San Francisco (see related story below). Although the G3 series includes new architectural features, it also shares some characteristics of the earlier 603e and 604e. The new product's developers target high performance using the smallest possible dice: The first G3 device has a die size of 67 mm² compared to the 603e's 79 mm².

The G3 series executes two instructions per cycle with a four-stage pipeline; a double-path, floating-point unit that uses two clocks to perform a double-precision calculation; dual 32-kbyte, eight-way set-associative caches; and a level-two cache controller. To speed branch performance, designers used a 64-entry, four-way set-associative branch-target-instruction cache. Unlike the 604, which uses a branch-target-address cache, the G3 series stores the branch instruction and shaves one cycle.

The G3 series also features an on-chip thermal-management-assist unit, which monitors the junction temperature and compares it against user-programmable values. The unit is useful in mobile applications in which battery power and heat buildup are critical. Motorola and IBM expect the first G3 µP to dissipate 5W at 2.5V while running at 250 MHz.

Although the G3 will be unavailable until midyear, OEMs will find the product easy to design-in because it has a 255-pin BGA, backward-compatible pinout with the 603e. However, the new version lacks the L2 cache controller. Another G3 series version has the L2 cache controller but comes in a 360-pin BGA.

--by Markus Levy

IBM Corp, Mount Prospect, IL. (415) 855-4121, www.chips.ibm.com.

Motorola, Austin, TX. (512) 434-1502, www.mot.com/PowerPC.

Trends toward faster, bigger, lower power designs emerge at ISSCC

The IEEE's International Solid State Circuits Conference (ISSCC), which took place in San Francisco last month, is an engineer's equivalent of a kid in candy shop: so much to see; so little time. Although most of the concepts ISSCC presents take at least a few years to turn into real-life products that you can use in your designs, they give an exciting glimpse into technology's future trends. The theme of this year's conference, multimedia, reflected such achievements as faster processing; bigger and higher bandwidth memories for storing and manipulating ever-richer data types, and lower voltage operation for power-conscious applications.

In the "faster" category, Intel's paper described the 300-MHz P6-class Klamath (now known as Pentium II) µP with multimedia-extension (MMX) instructions. In addition to MMX support, the Pentium II µP differs from the Pentium Pro µP in the Pentium II's 32-kbyte L1 cache and external L2 cache design. The company implemented the Pentium II µP, with 7.5 million transistors and rated at 12.0 SPECint95 at 300 MHz, on a 0.35-µm, four-layer metal process.

The conference also held its fair share of surprises. Between the time Intel submitted the paper and the day of the conference, the company cranked up the internal clock frequency to 400 MHz. The demonstration platform was a standard Pentium Pro-based PC with the system clock frequency raised to 95 MHz (with the help of a cleverly concealed external cooling unit) and directly connected standard VGA and 3-D-graphics cards to maximize performance. Much of the system's 128 Mbytes of DRAM served as a fast RAM drive for the various demo files. The company showed a variety of high-performance, graphics-intensive demonstrations, including 3-D games; the obligatory Photoshop filter suite; and a full-screen, full-color, 30-frame/sec MPEG video stream rendered without separate MPEG board assistance.

Intel Senior Vice President Albert Yu admitted that the demo was graphics-focused and didn't necessarily represent a more typical, balanced system. However, he pointed to future innovations, such as the Accelerated Graphics Port, as the means of further increasing graphics-subsystem performance and freeing processor bandwidth for other tasks.

Other companies announced notable processor innovations as well. AMD unveiled its sixth-generation x86 CPU with multimedia extensions, also referred to as "MMX" (although Intel might disagree). Product details were sketchy, although the company revealed that the processor contains 8.8 million transistors and runs at 233 MHz. Meanwhile, Exponential Technology took the PowerPC architecture to new heights with a 533-MHz µP implemented in a 0.5-µm BiCMOS process. This 2 million-transistor CPU also delivers a 12.0 SPECint95 rating, using two on-chip, 2-kbyte L1 caches and assuming a 66-MHz system clock and a 1-Mbyte, off-chip L2 cache.

Sun Microsystems and Texas Instruments showcased a 533-MHz, four-way-superscalar SPARC Version 9 64-bit processor with 5.4 million transistors, fabricated on a 0.28-µm process. IBM's 400-MHz processor implements the S/390 architecture, and Digital Equipment's and Mitsubishi's 550-MHz Alpha architecture processor focuses on MPEG-II encoding and decoding support. Digital's second Alpha takes the 1997 ISSCC processor-frequency record at 600 MHz and an estimated 40 SPECint95 and 60 SPECfp95. With 15.2 million transistors (a six-layer-metal, 0.35-µm process) and 72W average power dissipation, this one probably won't show up in portable workstations anytime soon.

Unfortunately, there were fewer memory papers this time around than in past years. However, lack of quantity had no impact on quality--at least for DRAM. NEC's 4-Gbit DRAM, manufactured on a 0.15-µm process, exemplifies the "bigger" trend at the conference. One chip can store six hours of CD-ROM quality audio. Looking beyond the technical achievement of its raw size, this DRAM also leverages the multilevel-cell technique popular with flash memory over the last few years. NEC's two-bank, ´64 memory uses a 2-bit-per-cell approach, approximately halving the array size and potentially alleviating some of the spiraling process-development and product costs facing DRAM manufacturers. Surprisingly, the multilevel-cell architecture does not significantly decrease performance; the 2.2V DRAM operates at 125 MHz with a maximum burst length of 128 accesses, although the additional sensing may impact random-access time compared with a 1-bit-per-cell counterpart.

Fujitsu takes top honors for "fastest" memory with a 256-Mbit, double-data-rate SDRAM that bursts data as fast as 200 MHz. (For more on double-data-rate SDRAM, see "Bandwidth busters meet the DRAM market," pg 14.) The memory regulates 3.3V externally to 2.5V internally and specs current draw at 135 mA in active mode. Two Mitsubishi papers focused on lower voltage: a 32-Mbit DRAM on a 0.25-µm process that operates as low as 1.2V externally and 0.8V internally and a 1V, 46-nsec, random-access, 16-Mbit memory that uses a 0.5-µm silicon-on-insulator process. Fi-nally, a variety of papers directly or indirectly discussed integrating and testing DRAM with logic, such as processor cores and ASIC gates.

Manufacturers also presented papers on flash memory and SRAM--again, in far smaller quantity than in years past. SGS-Thomson described a 2.5V flash memory with 1 million-cycle endurance and 20-Mbyte/sec read speed, and Samsung discussed how it adapted its NAND flash technology to design a 16-Mbit memory with a DRAM-compatible interface. The focus for SRAM was multihundred-megahertz speed for cache and look-up tables, as papers from Mitsubishi, Hitachi, IBM, NEC, and others showed. You can get all the details about this year's show and next year's plans at the ISSCC home page: www.sscs.org/isscc, or call (415) 494-7115.

--by Brian Dipert

Digital Equipment Corp, Maynard, MA. (508) 493-5111, www.digital.com.

Exponential Technology, San Jose, CA. (408) 441-6050, www.exp.com.

Fujitsu Microelectronics, San Jose, CA. (408) 436-7010, www.fujitsumicro.com.

Hitachi America Ltd, Brisbane, CA. (415) 244-7848, www.hitachi.com.

IBM Corp, Armonk, NY. (914) 765-1900, www.ibm.com.

Intel Corp, Santa Clara, CA. (408) 765-8080, www.intel.com.

Mitsubishi Electronics America Inc, Sunnyvale, CA. (408) 730-5900, www.mitsubishi.com.

NEC Electronics Inc, Santa Clara, CA. (408) 986-1020. www.nec.com.

Samsung Semiconductor, San Jose, CA. (408) 434-5400, www.samsung.com.

SGS-Thomson Microelectronics, Carrollton, TX. (972) 466-6000, www.st.com.

Sun Microsystems Inc, Mountain View, CA. (415) 786-7737, www.sun.com.

Video encoder/decoder handles NTSC and PAL signals

The new NTSC/PAL video chip set from Harris Semiconductor includes the HMP8112 decoder and HMP8156 encoder ICs. The set targets applications such as frame-grabber boards, VCR-to-PC editing systems, teleconferencing systems, and digital video-disk players. The decoder offers several innovations, including a comb filter that, relative to bandpass or chroma-tap filters, optimizes luminance/color (Y/C) separation without losing vertical detail. Moreover, an integrated sample-rate converter allows the decoder to use any available clock, and a digital PLL ensures steady images even in low-cost, PC-based, image-editing applications. The HMP8112 costs $13.95 (10,000)--about half the price of other video decoders with comb filters. The encoder accepts data in RGB or YCrCb format and outputs either an NTSC or a PAL signal. It costs $8.95 (10,000), and both ICs are available now.

--by Maury Wright

Harris Semiconductor, Melbourne, FL. (800) 442-7747.

Processor slashes system costs

Cyrix's MediaGX--at $79 and $99 for the 120- and 133-MHz versions, respectively--gives new meaning to the phrase "low-cost PC processor." What's more, these prices include the companion chip set, video drivers, and BIOS extensions that drive the GX. Cyrix also plans a 180-MHz version that supports Intel's multimedia-extension technology. Cyrix claims that the GX matches the performance of Pentiums at the same speed.

However, GX's real value comes from its integration: The CPU performs all standard north-bridge functions. Specifically, the MediaGX performs the functions of the PC's graphics controller, audio chip set, memory controller, and CPU-to-PCI bridge. Rather than using only transistors to perform these functions, Cyrix developed its Virtual System Architecture (VSA). VSA supports the graphics- and audio-hardware functions through software. At first glance, it might seem that VSA is yet another marketing angle for native signal processing, but Cyrix designers used an innovative approach.

VSA uses the MediaGX's system-management interrupt (SMI) to capture any application's accesses to the memory or I/O address ranges of the graphics and audio functions. Once the processor enters system-management mode, it executes Cyrix-supplied drivers to perform the appropriate function. One reason that VSA must use the SMM is to allow the software drivers to take advantage of new "hardware-accelerating" instructions that the GX supports. The SMM makes VSA operation transparent to Windows and DOS applications.

The graphics portion of VSA, XpressGraphics, uses compression technology and buffering to reduce the bandwidth contention of traditional unified-memory architectures. The VGA-compatible XpressGraphics accelerates the Windows graphical user interface and allows the CPU to directly drive the output to the display device. The GX performs most of the graphics in software but provides hardware support for lossless compression. The hardware simultaneously runs four compression algorithms, seeking the best one for a particular data type. After determining the most efficiently compressed data, the hardware stores the data in memory and tags it with the algorithm ID with which the hardware decompresses the data.

Some new GX instructions include block read/write from and to the cache's or graphics controller's virtual memory. In contrast, other processors typically transfer blocks of data with a string operation, using instructions such as MOVSD. However, this type of string operation repeatedly switches between reading and writing two possibly different locations in memory, requiring the DRAM bus to constantly switch directions and incur a bus-turnaround time. Also, if the read and write memory locations are far apart from each other, the DRAM array continuously switches between pages. Furthermore, every read caches the data and evicts something else from the cache. Moreover, you want the data cached at the destination of the writes--not during the writes--so that the subsequent instructions can rapidly access the data.

To solve these problems, another new GX instruction, MEM_BB, reads data from any location in memory, but the data goes to the "blit buffer," a dedicated region of the Level 1 cache. MEM_BB appears to the core as a sequence of read operations; the L1 cache automatically grabs the data as it enters the chip and places it in the blit buffer. When the µP completes the operation, the L1 cache's contents, except for the blit buffer, remain un-changed. The DRAM bus sees no writes during the MEM_BB instruction and, therefore, incurs no turnaround-time penalties.

XpressGraphics uses the MEM_BB instruction to grab bit-map or compressed video data and place it in the blit buffer. Once the data reaches the blit buffer, the core or the graphics accelerator can independently work on the data. You can load a bit map from virtual memory into a blit buffer and then have the graphics pipeline transfer that bit map to the screen. The graphics pipeline can expand or transform the bit map as it traverses the pipeline.

The GX uses Cyrix's XpressRAM technology to achieve main-memory performance comparable to accessing L2 cache. XpressRAM allows the GX to directly access memory at 35 nsec because the CPU immediately begins driving the address rather than through external buffers and a memory controller. The GX can also interleave or keep banks open in different memory devices. The GX supports as much as 128 Mbytes of extended-data-out (EDO) DRAM in four banks.

The remaining question: How low in price can PC manufacturers integrating the GX into their products go? One such company, Compaq Computer (Houston), integrates the device in the Presario 2100. The unit comes with a 133-MHz GX, 24 Mbytes of EDO DRAM, a 2-Gbyte hard drive, 8X CD-ROM, 33.6-kbps data/fax modem, speakers, and Windows 95. It sells for $995, and there's reason to believe Compaq left plenty of margin in that price.

--by Markus Levy

Cyrix Corp, Richardson, TX. (214) 994-8388, www.cyrix.com.

Book explores ins and outs of Pentium Pro

In Pentium Pro System Architecture (ISBN 0-201-47953-2), Tom Shanley of MindShare Inc (Richardson, TX) delivers an information-packed, easy-to-read book. The book describes the hardware and software characteristics of the Pentium Pro, the bus protocol it uses to communicate with the system, and the overall machine architecture. The book's 26 chapters detail the fetch, decode, and execution engine; the processor caches; bus transactions and transaction deferral; instruction-set enhancements; multimedia extensions; chip sets; and more. The $34.95 book is worth checking out if you're planning any designs that include the Pentium Pro processor or just want some good reading.

--by Markus Levy

Addison-Wesley, Reading, MA. (617) 944-3700, www.aw.com.

Low-cost digital thermometer tells you when to cool down

You design hot stuff that can also be too cool. When your product's temperature gets too far from its optimal range, the less-than-$1.25 (10,000) DS1720 Econo-digital thermometer and thermostat can help make it right. The thermostat has three user-programmable thermal-alarm outputs: T_HIGH, T_LOW, and T_COM, which stay high after a device exceeds a high-temperature threshold until the temperature falls below a low threshold.

The thermometer/thermostat measures temperatures from ­25 to +85°C in 0.5° increments with an algorithm that uses the effect of temperature on current flow in silicon. The user-defined temperature thresholds are stored on-chip in nonvolatile memory and are programmed before insertion in the system. These threshold values, as well as the output temperatures once the thermometer is operational, are written to or read from a three-wire serial interface that conserves pins on the eight-pin SOIC. The device communicates temperature as a 9-bit value.

--by Michael C Markowitz

Dallas Semiconductor, Dallas, TX. (972) 371-4000, fax (972) 371-3715, www.dalsemi.com.

CALENDAR

March 24 to 26

Communication Design Engineering Conference (CDEC), Washington, addresses data-communications systems and techniques and tools for hardware and software design. Miller Freeman Inc, San Francisco, CA. (415) 278-5231.

March 26 to 28

DSP World Spring Design Conference, Washington, a new event, addresses the on-the-job educational needs of engineers working with DSP technologies. More than 60 tutorials and classes are available. Miller Freeman Inc, San Francisco, CA. (415) 278-5231.

March 26 to 28

Conference on Advanced Communications and Competition in the Asia-Pacific, Bali, Indonesia, highlights the impact of new technologies and demand for components, cable, and operations and maintenance systems in fiber-optic satellite and wireless systems. Registration fee for the conference is $1495. KMI Corp, Newport, RI. (401) 849-6771.

New tools offer full-chip design verification

Two new EDA tools, Vampire RCX and ConcICe from Cadence, verify multimillion-transistor chip designs. Vampire RCX, a hierarchical, 3-D-formula-based extraction engine, provides accuracy approaching that of 3-D field solvers but with faster execution times. In one benchmark test, the vendor performed an RC-parasitic extraction of a 10 million-transistor chip in less than 12 hours. ConcICe, a parasitic-reduction tool, minimizes the size of extracted databases to speed analysis. The tool can reduce RC networks by as much as 90%, retaining an accuracy within 1% of the original database. You use Vampire RCX and ConcICe for final full-chip performance verification before actual chip fabrication.

The formula-based Vampire RCX reads a library of expected topological patterns for an IC-fabrication process, along with a process-technology file. With the data, the tool uses a 3-D field solver to generate coefficients for equations describing the resultant RC parasitics from specific geometries, such as wire overlaps and coupling between adjacent wires. Vampire RCX then applies these equations during extraction to analyze similar topologies. With Vampire RCX, you can also view extracted structures on a workstation screen, assisting identification and analysis of potential parasitic-induced problems. Vampire RCX outputs its data in both Distributed Standard Parasitic Format (DSPF) and Spice. ConcICe outputs its reduced RC-network database in reduced-form versions of DSPF and Spice.

Cadence sells Vampire RCX as a $110,000 stand-alone tool within the Vampire design-verification tool suite. You get ConcICe as a $25,000 option to Cadence's Vampire and Dracula suites. Both Vampire and ConcICe run on Unix-based workstations.--by Jim Lipman

Cadence Design Systems, San Jose, CA. (408) 943-1234, fax (408) 943-0513, www.cadence.com.

USB power-management IC combats shorts, overtemperature, undervoltage

The TPS2014 and similar TPS2015 from Texas Instruments protects PCs and peripherals on the Universal Serial Bus (USB) against surges, shorts, overcurrent, and overtemperature situations. When the devices sense out-of-bounds conditions, they protect the system and provide a fault indication to the system interface. The ICs eliminate the need for other protective devices and meet all USB requirements for current management; they also incorporate a MOSFET power switch that meets the USB limitations on voltage drop and regulation.

The TPS2014 senses over-temperature, usually due to excessive current flow, and shuts down current flow to prevent damage; it also automatically limits bus current to a safe value. Its undervoltage- lockout function inhibits power distribution if the supply rail falls lower than 4V to ensure that only those USB devices with sufficient supply are engaged. The eight-pin SOIC/DIP devices cost $0.97 (1000).

--by Bill Schweber

Texas Instruments, Dallas, TX. (800) 477-8924, ext 4500, www.ti.com.

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