March 14, 1997

Simplifying your ALU design

I just read Clive Maxfield's article, "A minus B=A+NOT(B)+1 (Part 2)" (EDN, Jan 2, 1997, pg 119), in which he makes a good argument for simplifying your ALU design for the "A­B" case by implementing a 1's complement function only and relying on setting the CI input on the subsequent add operation.

But wouldn't this design penalize someone who wants to change the sign (simple negation) of a value when a subsequent addition would not need to occur? Is your design attempting to optimize for the more common case?

Greg Schmidt
via the Internet

(Editor's note): Thank you for your e-mail and your interesting question. The beauty of computers is that the things that initially appear complex often turn out to be simple, and vice versa. In fact, the technique I described (which is the way ALUs are implemented in the real world) in no way penalizes someone wishing to change the sign (taking the 2's complement) of a value.

First, the simplest way to generate the 2's complement of a value is to invert that value and add 1 to the result--I don't know of a commonly used hardware technique that avoids this addition step.

Second, if you have a value x that you wish to negate to form ­x, then one way to do it is to subtract x from 0 (that is, 0­x= ­x). So, all you have to do is load the accumulator with 0 and subtract the value under consideration from 0. As I discussed in the article, the way you subtract one number from another is to take the 2's complement of the value to be subtracted and add this value to the other value; the way you take the 2's complement of a value is to invert all of the bits and add 1. This step brings you back to the solution in the article, which first inverted the value to be subtracted and then performed the addition by simply forcing the carry-in to the adder in the core ALU to a logic 1.

Last but not least, I showed the complementor block as comprising the eight inverters and an 8-bit-wide, 2-to-1 multiplexer. In fact, this whole block of logic could be compressed into eight two-input XOR gates. You would just take the select signal that we used to control the original multiplexer in the complementor block and feed this signal into one input of each of the XORs--a logic 0 on this signal would allow the eight data bits to pass through the XORs unmodified, and a logic 1 would cause the data bits to be inverted. Pretty sneaky, huh?

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