Growing
your own IC clock tree Defining the
clock-distribution network is one of the
most difficult aspects of high-speed,
system-on-a-chip design. Employing the right design
methodology helps you "beat the clock." —Jim Lipman,
Technical Editor
Design
Features
PLL
synthesizers make channel-hopping swift and sure Wireless
systems for cellular and PCS applications must
quickly and accurately switch channel
assignments. New PLLs minimize some of the traditional
trade-offs involved. —Bill Schweber,
Technical Editor
FIFO memories
supply the glue for high-speed systems System designers
have long used FIFO memories to couple subsystems
with disparate data-transfer rates.
Recently, new types of these devices—with new
capabilities—have emerged. Know your
FIFO choices before you start "gluing" your
next system together. —Markus Levy,
Technical Editor
Using
multiline models in dual- and single-point
grounding configurations When using connector multiline
models, choose your simulation's ground connections with
care. Single-point grounding
configurations inaccurately predict connector
propagation delay, impedance, and crosstalk noise. —Timothy
R Minnick and Hank Herrmann, Amp Incorporated
Switching RISC
architectures theeasy way Performance demands and
discontinued product families can force
you to switch RISC processors for your next-generation
product. Choosing the right replacement can ease the
pain of the resulting hardware and software
redesign. —John Canosa,
Questra Consulting, SES Technology R&D Group
