Table 1—Representative FIFO devices1
  Major
characteristics &
special features		 Depth
range		 Width
range
(bits)		 Maximum
frequency
(MHz)		 Retransmit
feature		 Status
flags2		 First-word
fall-through		 Special noise-control
features		 Cascading
methods		 Approximate
price per
kilobyte3		 Second
sources
Cypress Small, asynchronous/
unidirectional, parity generate and check		 64 bytes 4/5/8/9 20 No HF, AFE No Output slew-rate control Serial and parallel $80 AMD, IDT
  Asynchronous/
unidirectional, parity generate and check		 256 bytes to 32 kbytes 9 100 Read pointer resets to 0 EF, FF, HF on 42×/3×/6×, add AE, AF on 47× No Output slew-rate control Serial and parallel, single token $25 (256 bytes)/
$0.75 (32 kbytes)		 AMD, IDT, TI, Quality Semiconductor
  Clocked/unidirectional, parity generate and check 512 bytes to 4 kbytes 9/18 83 No EF, FF, HF on 46×, add AE, AF on 47× No Output slew-rate control Serial and parallel, single token $15 (512 bytes)/
$5 (4 kbytes)		 No
  Synchronous/
unidirectional, parity generate and check		 64 bytes to 8 kbytes 9/18 100 On ×18s read pointer resets to 0 EF, FF, AE, AF, add HF on ×18s No Output slew-rate control Serial and parallel on ×18s, no on ×9s $75 (64 bytes)/
$1.90 (8 kbytes)		 IDT, TI, Quality, Semiconductor, Sharp
  Deep synchronous/
unidirectional, parity generate and check		 8 to 32 kbytes 9/18 100 On ×18s read pointer resets to 0 EF, FF, AE, AF, add HF on ×18's No, but only 2.5 cycles latency Output slew-rate control Serial and parallel on ×18s (two token), no on ×9s $1.30 (16 kbytes)/
$0.85 (32 kbytes)		 No
  Double synchronous/
unidirectional, parity generate and check		 256 bytes to 8 kbytes 9 100 No EF, FF, AE, AF, HF No Output slew-rate control Parallel support only $30 (256 bytes)/
$3.25 (8 kbytes)		 IDT
Integrated Device Technology Synchronous unidirectional and bidirectional, mailbox-bypass register, byte swapping, dynamic bus matching, parity generate and check on 64-bit depth only 64 bytes to 1 kbyte 36 67 No FF, AF, AE, EF Yes Input blanking circuitry desensitizes input noise Parallel and serial using first-word fall-through with no need for external logic, gate similar flags from different FIFOs $2 Some
  Synchronous, bidirectional 256 and 512 bytes 18 50 Pointer resets to 0, extra counter bit prevents pointer from getting ahead of write FF, HF, AF, AE, EF No Input blanking circuitry desensitizes input noise No $1 No
  Supersynchronous 8 and 16 kbytes 9 or 18 100 Pointer resets to 0, extra counter bit prevents pointer from getting ahead of write FF, HF, AF, AE, EF Yes Input blanking circuitry desensitizes input noise Parallel and serial using first-word fall-through with no need for external logic, gate similar flags from different FIFOs $0.76 No
  Synchronous triple port, dynamic bus matching 64 bytes to 1 kbyte 9/18/36 67 No FF, AF, AE, EF Yes Input blanking circuitry desensitizes input noise Parallel and serial using first-word fall-through with no need for external logic, gate similar flags from different FIFOs $2 No
Motorola Synchronous, unidirectional, dual-ported CMOS line buffer with a single clock 8 kbytes 8 50 Programmable read and write pointers NA No Unnecessary Expansion to eight chips by assigning unique 3-bit value to each device’s control register $0.60 No
NEC Asynchronous line buffer, unidirectional 5 kbytes and 10 bytes 8/16 40 Read pointer resets to 0 None No None Serial only using single-wire $3 per unit No
Sharp Asynchronous, unidirectional 512 bytes to 8 kbytes 9 100 Read pointer resets to 0 FF, EF, HF Yes Output slew-rate control Serial and parallel, single-wire token-passing, use external logic to derive composite flags $3.10 Industry standard
  Synchronous, unidirectional 512 bytes to 4 kbytes 18 50 Programmable read pointer FF, EF, HF, AF, AE, HF synchronized to either clock (selectable) No Output slew-rate control Default is two-wire token passing, with optional pipelined mode, uses second read/write enables and delayed flag $7.20 Quality Semiconductor, TI, IDT
  Synchronous, unidirectional, mailbox-bypass register, byte swapping, dynamic bus matching, parity generate and check 1 kbyte 36 50 Read pointer resets to 0 FF, EF, HF, AF, AE, HF synchronized to either clock (selectable) No Output slew-rate control Pipelined, cross-connecting flags and enables provided for interlocked width expansion $8.20 Quality Semiconductor
  Synchronous, bidirectional, mailbox-bypass register, byte swapping, dynamic bus matching (512 and larger), parity generate and check 256 bytes to 1 kbyte 36 55 Read pointer resets to 0 FF, EF, HF, AF, AE, HF synchronized to either clock (selectable) No Output slew-rate control and series resistor None $12.80 Quality Semiconductor
Synergy Single-clock, synchronous, very high speed, parity generate and check 64 bytes 18 200 Yes FF, HF, EF, overflow, underflow No Proprietary bipolar ECL technology plus voltage and temperature compensation None $1536 to $2048 No
Texas Instruments4 ACT, clocked, strobed, asynchronous, synchronous/
unidirectional, bidirectional		 256 bytes to 16 kbytes 1/4/5/8/9 67 Some FF, AF, HF, AE, EF All clocked devices TI's output-edge control Depth and width, FF and EF logically AND connected $1 to $154 Some
  ABT, clocked, strobed, bidirectional 512 bytes 18 80 No FF, AF, AE, EF All clocked devices TI's output-edge control Depth and width, FF and EF logically AND connected $61 to $154 No
  ACT, clocked, strobed, unidirectional 64 bytes to 1 kbyte 18 67 No FF, AF, HF, AE, EF All clocked devices TI's output-edge control Depth and width, FF and EF logically AND connected $2 to $205 No
  ALV, clocked, strobed, unidirectional 64 to 512 bytes 18 50 No FF, AF, HF, AE, EF All clocked devices TI's output-edge control Depth and width, FF and EF logically AND connected $5 to $154 No
  ABT, clocked, unidirectional, bidirectional, mailbox-bypass register, byte swapping, dynamic bus matching, parity generate and check 64 bytes 32/36 67 No FF, AF, AE, EF All clocked devices TI's output-edge control Depth and width, FF and EF logically AND connected $20.50 to $51 Some
  ACT, clocked, unidirectional, bidirectional, mailbox-bypass register 256 bytes to 2 kbytes 32/36 67 Yes FF, AF, AE, EF All clocked devices TI's output-edge control Depth and width, FF and EF logically AND connected $5 to $51 Some

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