March 27, 1997

EDN Hands-On Project: Demystifying ADCs

Bill Travis, Senior Technical Editor

Hands-on testing demonstrates that high-speed A/D converters don't always perform up to spec. Are they faulty or just susceptible to misapplication?

The current generation of high-speed ADCs would have provided a subject for science fiction only a few short years ago. Big, expensive hybrids struggled to eke out 12-bit performance at 10-MHz sampling rates. Now, we have 12-bit monolithic devices that accommodate sampling rates as high as 48 MHz. Today's ADCs form the heart of data-acquisition systems for such applications as radar, audio and vibration analysis, wireless communications, and high-speed test equipment.

These devices are not easy to apply, however. Any deficiencies in driving, clocking, grounding, bypassing, and powering converters can result in severe degradation of high-speed parameters. To see just how and why performance degrades, EDN ran some high-performance ADCs through some rather rigorous exercises. The results? Among other things, this finding: To get the most out of a high-speed ADC, you have to treat it right; performance parameters specified by manufacturers often are valid only under ideal conditions--if then.

That last "if" condition is what most disturbed us. Some ADCs, to our surprise, didn't even come close to meeting their specs, even allowing for nonidealized test conditions. Was our testing faulty? We don't think so. We were assisted by one of the premier ADC experts in North America, Muneeb Khalid of Gage Applied Sciences. Were the devices faulty? We don't know yet; we're just now beginning a dialogue with their manufacturers to get to the bottom of the problem. We'll report our findings in a future issue.

What we're sure about for now, after extensive testing, is that some ADCs probably can meet their specs if you test them under conditions that allow them to work at their very best. Our tests weren't that elaborate, but we still believe that manufacturers of these devices aren't misrepresenting their products--just presenting them in the best possible light. In the pages that follow, we discuss our tests of those devices, including both good and "bad" (nonideal) results.

Bear in mind, when you read our accounts of "bad" performance, that we're discussing ADCs that, for the most part, performed well. Our intention is not, and never was, to unmask subpar ADCs, but to illustrate how nonideal conditions degrade ADC performance. In short, as our headline says, we want to "demystify" ADCs. Our intent is to help you understand how to design with them to get maximum performance.

We did uncover apparent problems in quite a few ADCs, however, and we're not ignoring those problems. We'll give you the details in a future article, as soon as we get to the bottom of the situation. Frankly, we were surprised to find as many problems as we did, so we're double-checking our procedures and consulting with ADC manufacturers before we attribute blame to any particular devices or companies. We're not dodging responsibility by temporarily withholding information, just acting responsibly and making sure our information is right. We'll keep you informed. In the meantime, see what lessons you can learn from the work we've done so far.

Drawing on expertise

We had a pretty good idea, going into our test project, of how ADC performance degrades under nonideal conditions. We also thought we knew how to treat (or, for the purposes of experiments, mistreat) an ADC to demonstrate that degradation. Nevertheless, we needed expert help and expert equipment to actually put ADCs through their paces. For that, we turned to Gage Applied Sciences (Montreal, PQ, Canada), a company that specializes in high-speed data-acquisition systems and thus has considerable insight into the workings of high-speed ADCs. Gage founder and president Muneeb Khalid performed the actual tests for our hands-on study and also contributed expert knowledge.

Khalid's expertise with ADCs is matched by few designers anywhere, as demonstrated in his design of a Gage ISA-bus card that offers 12-bit, 100-MHz operation. The card uses two 50-MHz ADCs (selected from 40-MHz devices) operating in "pingpong" fashion. Designing such a system--that actually works--is a prodigious feat. It's roughly akin to hitching a ride between two tractor-trailer trucks, one foot on each running board, with the trucks rolling at 100 mph. Any deviations in linearity (direction) or dynamic performance (speed), and you present an interesting cleanup challenge to a road crew. Corresponding mismatches in the pingponged ADCs result in nonmonotonic performance (code reversals), missing codes, and degraded dynamic specs.

Our tests, drawing on Khalid's expertise in high-speed applications, concentrated on dynamic parameters. Static parameters, such as differential and integral linearity, offset, and gain are of interest principally in dc and low-frequency applications. In high-speed systems, these parameters are of interest only insofar as they affect dynamic performance. Differential nonlinearity, for example, increases SNR, missing codes raise the noise floor in the converter's spectrum, and integral nonlinearity produces harmonic distortion.

And, of course, we concentrated on high speed. After all, anyone who selects a high-speed converter probably has a high-speed application in mind. Specifically, we focused on ADCs with resolution of 10 bits or more and sampling rates of 10 MHz or higher. You wouldn't choose one of these speed demons for application in a weighing scale.

In applying these speed demons, Khalid has some words of wisdom. For example, he says, if you're contemplating designing a high-speed ADC into a system, don't even think about starting from scratch with the unadorned converter. Instead, get an evaluation board from the manufacturer. The company that designed the converter knows its quirks and idiosyncrasies and knows how to squeeze the last possible drop of performance from the device. The evaluation board incorporates the optimum driving, clocking, grounding, and powering methods for the converter at hand. For example, some converters don't like ground planes, some like split (analog and digital) ground planes, and some like solid ones. Some prefer a common analog and digital supply; some prefer separate power planes.

An evaluation board may cost you, of course, but you save money in the long run. ADC manufacturers invest a lot of engineering hours into their optimized hookups, so why should you reinvent the wheel by expending a comparable effort? (Besides, there's no guarantee that you'll come up with an optimum configuration.) Probably the best reason for investing in an evaluation board is the possibility of plagiarizing it (with the manufacturer's blessing). You can emulate the board's driving, clocking, grounding, decoupling, pc-trace routing, and powering techniques in your application and thereby save countless hours of frustrating debugging and redesign.

No analog testing, thanks

You might think you can test an ADC by connecting a "perfect" D/A converter to its output. You feed in an input waveform and then measure the reconstructed output waveform for distortion products. Khalid quickly pointed out pitfalls in this approach, however. First, no "perfect" DAC exists. Second, anything you insert in the conversion path introduces errors. Third, all-digital testing is fast, easy, and accurate, thanks to the wide availability of software utilities for waveform analysis.

In the test setup we constructed at Gage, both the input signal source and the power supplies are linear units (Figure 1 and Table 1). Khalid explains that a DSS (direct-digital-synthesis) generator--as desirable as its attributes are--does produce noise components that could compromise an ADC's measured performance. The same is true for switching power supplies.

To produce an even cleaner sine-wave input, our test setup used a seven-pole Chebyshev filter. The seven-pole response essentially inserts a "brick wall" in the way of unwanted harmonics. The less-than-ideal phase response of the Chebyshev characteristic is inconsequential, because our tests involved only single-frequency signals. By the way, you should bear in mind that a single-frequency test is less stressful to converters than is a multiple-frequency test. If a converter can't pass a single-frequency test, imagine what would happen with dual or multitone inputs.

The Gage CompuScope 8012/DIM in Figure 1, a 100-MHz data-acquisition system occupies two slots in an ISA-bus computer. In our hands-on tests, we used only the DIM (digital-input-module) portion of the system, shown to the right of the broken line in Figure 2. This module accepts 24 bits of differential ECL or CMOS data and one differential ECL or CMOS clock; 24 high-speed comparators convert the input data and clock to CMOS levels for storage in a 1M×24-bit bank of static RAM. The input connector is a 3M (Minneapolis) 2560-5002UB IDC header; the mating female connector is a 3M 3334-6000 or equivalent. The maximum speed of the differential clock is 52 MHz, with a rise time of 1 nsec or shorter.

Our test methodology, briefly, was to apply a sine-wave analog input to an ADC, capture its digital-output words in static RAM, and then analyze the captured, digitized waveform with a software utility. The software we used is GageScope, a graphics and analysis utility that controls Gage's family of oscilloscope and data-acquisition cards (notably, the CompuScope 8012/DIM). For the analysis, Khalid chose a 2048-point FFT with an Exact Blackman windowing function.

Use of a windowing function was necessary in our tests to avoid errors from spectral leakage (Reference 1). These errors arise when an FFT transforms discontinuities that result from sampling less than a whole number of periods of the input. Windowing is unnecessary if the analog-input frequency is an exact (coherent) submultiple of the sampling frequency. Unfortunately, just synchronizing the analog input and clock wouldn't work in this case, because it would give rise to jitter, or phase noise. The slew rate of the sine wave is relatively slow, so any aperture uncertainty in the comparator at the clock generator's sync input would produce unacceptable jitter.

Before getting into our test results, it might be useful to define the following terms. References 1 and 2 provide more detailed definitions:

• SNR is a measure of the broadband noise introduced into the signal from the ADC and the sampling process. SNR compares the magnitude of the input sine wave to the sum of all other frequencies, except those representing harmonics of the fundamental.
• Total harmonic distortion (THD) is the ratio of the fundamental to the sum of the harmonics.
• SNR and distortion (SINAD) is the ratio of the power in the fundamental frequency bin to that in all other bins, including harmonics.
• Spurious-free dynamic range (SFDR) is the difference in magnitudes of the fundamental and the highest spur.
• Static noise is the number of bits of instability in the output code with the analog input held at a constant dc level.

President Ray Oushani of Edge Technology, one of the companies whose converters we tested, provides some insight into the significance of these parameters as a function of application. High SNR is crucial in Doppler-radar applications, Oushani says, and radar designers are willing to accept relatively low SFDR figures to obtain high SNR. Conversely, high SFDR is of prime importance in communications applications. Digital wireless systems can falsely recognize spurs as channels. The way to obtain high SFDR at the expense of SNR is to restrict the full-scale input range. Designers of data-acquisition and automatic test systems are principally interested in THD, because it's a measure of the integral linearity of the transfer function. High SINAD is important in medical systems and automatic test equipment.

Our first tests involved an AD9042, a 12-bit, 41-MHz converter from Analog Devices. Figure 3 shows the GageScope screen grab for an 898-kHz input at a 20-MHz sampling rate. Figure 4 shows the screen grab for a 19.1-MHz input at a 40.96-MHz sampling rate. As you can see, the "noise floor"--the band of spurious stuff at the bottom of each plot--is higher in the higher frequency plot (Figure 4) than in the lower frequency plot (Figure 3), giving rise to lower SNR and SINAD figures. In both cases, the screen grabs reveal much lower SFDR than the 90-dB typical figure in the product's data sheet. Note, though, that this "discrepancy" isn't really a discrepancy; the 90-dB spec reflects "dithering" the analog input by a few millivolts to randomize coherent spurs generated in the converter (Reference 3). In the digital-radio applications that the AD9042 targets, dithering is a popular technique for increasing sensitivity.

It is interesting that our testing revealed better parameters with a 40.96-MHz clock than with a 20-MHz clock (Table 2); this result is contrary to what you'd normally expect. What it probably means is that the converter is optimized or tweaked for the 41-MHz sampling rate. To appreciate the complexity of applying high-speed ADCs, note that nine pages of the AD9042's 24-pg data sheet are devoted to application advice. One important piece of advice is that you ac-couple the input signal to the ADC. If you use dc amplifiers to level-shift the input to the 2.4V offset inherent in the AD9042, you'll probably see degradations in the dynamic performance.

If you apply a dc voltage to the input of an A/D converter, you probably expect the output code to vary no more than 1 LSB. But that's not so with these high-speed devices. The code varies around the correct one by several least significant bits. The worst case for this static noise is at the major transition, where one and all zeros change to zero and all ones. This wavering is of little concern in high-speed applications, because they don't usually deal with dc signals. The AD9042 exhibited 5 LSBs of static noise with a 40.96-MHz clock and 7 LSBs with a 50-MHz clock. This result was not at the major transition; it wasn't possible to bias the ac-coupled input for that operating point.

As stated earlier, anything can degrade the dynamic performance of these high-speed devices. One possible source of problems is the power supply, as illustrated by our tests of the 5V-only AD9042. When we measured performance with a 1.9-MHz input and a 40.96-MHz sampling rate, we used both a bench-quality linear supply and a low-cost switching supply from a PC-compatible computer. The results are as follows:

The results for SNR and SINAD are within expectations: The switching noise from the PC-type supply increases the measured noise. However, the improved SFDR is surprising. We surmise that the PC-type supply is providing "dither," causing noise to concentrate in the first megahertz or so of the band, thereby increasing noise and simultaneously improving the THD and the SFDR. Khalid explains that, in his experience, placing an ADC in a computer environment (ISA, VME, or PCI, for example) degrades the specs of the converter by 3 to 7 dB, depending on the power-supply rejection ratio of the ADC and its driving amplifier.

Moving to 14 bits

Recently, 14-bit ADCs have cracked the 10-MHz barrier and are now readily available (Table 3). Factors that contribute to parameter degradation have even more pronounced effects at this higher resolution. Clock jitter is one of the culprits. To study its effects on dynamic performance, we tested the 14-bit, 10-MHz AD9240 ADC from Analog Devices. The evaluation board for this device makes it easy to induce jitter. The input stage on the board takes a high-slew-rate sine or square wave, which drives a 74HC14 Schmitt-trigger inverter, which in turn clocks the ADC. To induce jitter, you need only reduce the slew rate at the clock input by reducing the amplitude of the sine wave. (The use of a sine-wave clock source is atypical; we use it here simply to simulate the effects of a jittery clock.)

Figure 5 shows the result of using a 1V, 10-MHz sine wave from the 2018A signal generator to trigger the clock. The 1.914-MHz signal source is a Hewlett-Packard (Santa Clara, CA) HP652A generator. The clock jitter arising from this slow-slewing trigger source produces enormous side lobes, reducing the SFDR to a meager 58 dB. Under these artificial conditions, the converter wouldn't even qualify as a 12-bit device,--much less a 14-bitter. Swapping the 2018A and the HP652A yields the same result, essentially showing that the jitter comes not from the sinusoidal sources, but from the aperture uncertainty in the clock circuitry on the evaluation board. A 5-MHz sampling rate yielded the same huge side lobes, and the SFDR is even worse: 56.1 dB.

We observed a remarkable improvement, however, when we increased the 10-MHz sine-wave amplitude to a more typical 5V (Figure 6). The SFDR increases dramatically to 76.6 dB, and the offending side lobes disappear. SNR, THD, and SINAD with the 1.743-MHz input signal are 69, 84, and 67 dB, respectively. Using a 5V square-wave clock source further improves the SFDR to 82 dB. Although our test didn't obtain the 90-dB SFDR presented in the AD9240's data sheet, Paul Hendriks, an application engineer at Analog Devices, has at least a partial explanation. Analog Devices doesn't use windowed FFTs in testing, Hendriks says, although that fact alone should not have such an influence on SFDR.

What Analog Devices does do is to use two low-phase-noise HP8644A signal generators, locked (synchronized) together. The signal generator used for the clock is set at 320 MHz; an HP clock divider reduces this rate to 10 MHz. The jitter for this configuration is less than 3 psec rms. Analog Devices' measured SNR for a 5V full-scale input is 80 dB; for a 2V span, it's 74 dB. Analog Devices uses a nonwindowed 4096-point FFT.

The kind of device testing that Analog Devices performs is expensive. The HP8644A costs more than $40,000, and the cost of the clock divider isn't trivial, either. Also, Analog Devices uses coherent signals, which you don't usually encounter in real applications. Still, the company's measurements do reflect how well devices can perform; just remember that in your own work, you probably won't encounter the ideal conditions that make such stellar performance possible.

In addition to dynamic specs (Table 3), another parameter of interest is effective number of bits (ENOB). This parameter is a measure of how many usable bits of resolution a converter offers, taking account of its S/N ratio. A simple formula for ENOB is (SNR­1.76)/6.02 (Reference 1). The 56.1 dB measured with a jittery clock for the AD9240, for example, yields an ENOB of only 9 bits for the 14-bit converter, whereas Analog Devices' measured 80 dB yields 13 bits. Another way to derive ENOB uses curve fitting rather than SNR (Reference 4).

You can encounter quirky and sometimes inexplicable behavior when testing high-speed, high-resolution converters. Our testing of the 14-bit, 20-MHz ET2473 ADC from Edge Technology provides an example of the mysterious phenomena that can crop up. With a 20-MHz clock and a 1.9-MHz, full-scale input, the unit provides approximately 86.7-dB SFDR. The FFT screen grab shows that the second harmonic, at ­98.5 dB, determines the SFDR. An identical measurement, made seconds later, yields 82.9-dB SFDR. The second harmonic, for no apparent reason, showed an increase of almost 4 dB. When queried about this peculiarity, Edge's Lot Khani, application manager, attributed the change to the cabling linking the converter to the PC. He explained that just touching the cable can cause performance changes. Gremlins? A slight change in atmospheric pressure?

More strange behavior becomes evident when the input-signal level changes. Figure 7 shows the result of reducing the input signal to 20 dB below full-scale (200 mV p-p). Some fairly serious spurious activity becomes visible at the third, fourth, fifth, and sixth harmonics. With a full-scale input, these harmonics were insignificant. No one could explain this seeming anomaly. Figure 8, which shows the result of reducing the input to almost 60 dB below full-scale, reveals another surprise. Almost all spurious activity disappears, leaving an impeccably clean FFT screen grab, with a very low noise floor and with all spurs at least 95 dB below full-scale.

Though they have 16 times lower resolution than 14-bit ADCs, even 10-bit converters are not immune to mysterious and perplexing behavior in a testing environment. In our tests, such behavior arose when we exercised the Philips TDA8762, a 10-bit, 80-MHz ADC. We should point out, though, that this device comes on an evaluation board that is not exactly amenable to high-speed dynamic testing, because the board lacks buffered data outputs. As a result, the ADC chip itself must drive the cable (with its inherent inductance and capacitance) in the test setup. The board does incorporate a reconstruction D/A converter that's useful for checking basic operation but inadequate for dynamic ADC testing.

With a 10-MHz clock and a 1.9-MHz input signal, the TDA8762 yielded the respectable SFDR and SNR figures of 66.7 and 56.8 dB, respectively. Increasing the clock rate to 40 MHz, however, produced an unexpected result--significant glitches in the output waveform (Figure 9). Khalid suspected some kind of data-latching problem. To rule out the possibility that the digital-output cable load caused the glitching, we disconnected the cable. The onboard DAC, however, showed that the glitching persisted. When we increased the clock rate to its maximum 80-MHz rate, the glitching disappeared. SFDR ranged from 61 to 65 dB, but SNR was only 44.3 dB. Khalid suspected some kind of transmission-line problem that may cause some of the least significant bits to latch improperly, thereby degrading SNR.

Our tests of several converters from other manufacturers supported, to a great degree, the main point that emerged from testing the AD9042 and AD9240 devices: The dynamic specs in ADC data sheets are optimum figures that manufacturers obtain by testing with optimum test setups. They demonstrate what a device is capable of doing, but it's difficult to realize such performance in practice. What real-world system has a perfect, jitterless clock; a perfect, no-phase-noise, analog driving source; and perfect, noise-free power supplies?

We did encounter quite a few situations, though, in which measured performance wasn't even close to specified performance. We even tested some converters that just plain didn't work. In one case, an ADC evaluation board contained an inexplicably self-incinerating op amp. We'd like to know why those problems occurred, so we're continuing our investigations. Stay tuned for a future update.

In the meantime, consider some lessons from our hands-on testing and several years of school-of-hard-knocks experience. Our technical consultant for this project, Khalid, has these words of advice for those planning to design with high-speed ADCs:

• Don't expect to obtain n-bit performance from an n-bit converter at high speeds. If you absolutely need 12-bit dynamic range, for example, you'd do well to overkill and use a 14-bit device. Its SNR, THD, and SFDR are--theoretically, at least--vastly better than those of a 12-bit ADC, so you obtain a dynamic range that befits a 12-bit system. Overkill also applies to the clock rate. Unless you tweak an ADC for optimum performance at its maximum specified clock rate, you usually obtain better performance at lower rates.
• Keep your analog-input section simple and clean. Any amplifiers you add to the signal path add signal noise, phase noise, and harmonic distortion. The evaluation boards we received all have 50 ohms coaxial inputs. You have to account for the transmission-line impedance of your system and match it to the input impedance of the ADC to avoid reflections. If your analog-input line has a high impedance, keep it away from fast-slewing clock signals and other digital lines to avoid coupled noise.
• Use a clock source that's as jitter-free as possible. If your ADC accepts a sine-wave clock signal, use the greatest possible amplitude to obtain a high slew rate at the trig gering threshold. Insert as few gates as possible in the clock path; every logic circuit adds jitter. According to Khalid, low-power Schottky logic is especially guilty.
• Use linear power supplies whenever possible. Even if the ADC specifies separate supplies for its analog and digital sections, you'll often do better to power both sections from the clean, linear analog supply than from the usually noisy digital supply found in most systems. If you want to convert a higher voltage bus locally at the converter, use a linear regulator rather than a switching dc/dc converter. You waste some power this way, but you avoid switching noise that could compromise ADC parameters. If the power wastage is unacceptable, you can use a two-step approach: Use a dc/dc converter for a first conversion and then a low-dropout regulator to power the ADC.
• Use multilayer ground and power planes in your pc-board layout. The evaluation board for your converter of choice incorporates the optimum grounding, powering, and decoupling configurations for that ADC; you'd do well to emulate its design as closely as possible.

References

1. Demler, Michael, High-Speed Analog-to-Digital Conversion, Academic Press Inc.
2. Product Catalog Glossary, Gage Applied Sciences, Montreal, PQ, Canada.
3. Brannon, Brad, "Wide-dynamic-range A/D converters pave the way for wideband digital-radio receivers," EDN, Nov 7, 1996, pg 187.
4. Brannon, Brad, "Calculate an ADC's Effective Bits," Test & Measurement World, May, 1996, pg 17.

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