March 27, 1997

Technology initiatives stimulate 3-D graphics

Maury Wright, Technical Editor

Three technologies--MMX, AGP, and Talisman--along with ICs that accelerate the 3-D pipeline--should make compelling 3-D graphics widely available. This year, however, promises to be a rocky one for system designers and vendors that must meld hardware designs with volatile APIs and application software.

Applications ranging from low-cost simulators and virtual-reality systems to compelling games for consumers beg for ubiquitous, affordable 3-D graphics systems. From a hardware perspective, IC vendors have raced to develop ICs that can accelerate portions or all of the 3-D pipeline and fit into a PC price profile. Meanwhile, hardware-oriented technology initiatives, including Intel's Pentium-class µPs with multimedia extensions (MMX), Intel's Accelerated Graphics Port (AGP), and Microsoft's (Redmond, WA) Talisman, promise to further proliferate and accelerate 3-D implementations. Software and hardware designers should closely evaluate the effect these technologies will have on 3-D architectures. Despite these advances, however, evolving and sometimes-unreliable 3-D application-programming interfaces (APIs) could delay the move to ubiquitous 3-D systems.

A year ago, EDN predicted that a number of vendors would enter the potentially lucrative market for 3-D-accelerator ICs late last year and early this year (Reference 1). More than 20 vendors either now offer such products or will debut such products in the next three months. The magnitude of IC vendors' interest is amazing, considering that three or four vendors have traditionally controlled about 90% of the market for PC graphics accelerators. History suggests that only around a half-dozen vendors will achieve significant market success selling 3-D-accelerator ICs into the mainstream-PC market.

The capabilities of the installed base of 3-D ICs vary widely (Table 1). At the mainstream PC end of things, combination 2- and 3-D ICs from such companies as ATI and S3 primarily accelerate rendering and rasterization. At the high end, companies such as 3DFX offer 3-D-only ICs that can handle substantial parts of the geometry stage. These ICs require a separate 2-D IC and ultimately target devoted game enthusiasts. The flood of new products and vendors will soon yield more choices in features and performance relative to price. For example, Tritech's just-announced Pyramid 3D IC handles the full geometry stage yet targets mainstream PCs. Many other offerings will handle the triangle-setup task at the back end of the geometry stage. Figure 1 provides a granular view of the 3-D pipeline and the range of operations that a 3-D accelerator can capture.

Obstacles to 3-D ubiquity

Low-cost graphics-accelerator ICs, however, will fill just one of several voids on the path to ubiquitous and compelling 3-D graphics. The graphics ICs also need faster access to more memory. However, the industry first faces the old chicken-and-the-egg problem: Consumers have been slow to invest in premium-priced 3-D systems because of a lack of compelling content, whereas independent software vendors (ISVs) have been slow to invest heavily in 3-D applications. The ISVs fear that not many systems can run such applications with acceptable performance and also would prefer one dominant API that would allow 3-D applications to operate across a variety of systems with little or no modification (see box, "Direct3D: panacea or poison?").

Intel believes its MMX-equipped µPs will encourage ISVs to accelerate developments in the 3-D graphics arena as well as in other multimedia areas, including video and audio. Presumably, the MMX instructions will allow systems to provide a baseline ability to run multimedia applications, regardless of whether hardware is present to accelerate the 3-D, video, audio, or other media streams.

In the case of 3-D graphics, MMX can improve performance in a system without hardware-3-D-acceleration features (Reference 2). MMX-enabled µPs feature an additional execution unit with a single-instruction, multiple-data (SIMD) architecture that can simultaneously process four or even eight data items. The MMX execution unit, however, is only 64 bits wide, so it limits precision to 8 bits when applying an instruction to eight parallel arguments. Moreover, MMX instructions can't perform floating-point operations, and you cannot interleave MMX and floating-point instructions, because the MMX and floating-point units share the same registers. Switching between MMX and floating-point instructions incurs latencies as long as 50 clock cycles so that the µP can save and restore register states.

The geometry stage of the 3-D pipeline relies heavily on floating-point calculation, so MMX instructions prove to be a liability in the early parts of the pipeline. You can effectively apply MMX instructions to rendering and rasterization. Intel claims that MMX can double 3-D performance in a system without a 3-D hardware accelerator. Presumably, this increase in performance would establish a credible 3-D baseline and encourage development in the ISV community.

In reality, MMX will have little impact on the 3-D community. The installed base will be more likely to buy a new 3-D graphics board than an MMX-µP upgrade. New systems that ship with an MMX µP will almost certainly ship with a 3-D hardware accelerator. The current market-share leaders in graphics ICs--S3 and ATI--have added 3-D functions to their commodity 2-D-accelerator ICs. The doubled level-one cache on the MMX Pentium µPs will provide a more compelling performance boost in 3-D graphics than will the new instructions. MMX will also provide value in other areas, however, because the SIMD architecture could shine in applications such as video or audio codecs.

Although MMX's value in 3-D architectures may be lacking, AGP and Talisman both seek to solve the two technological obstacles to compelling graphics: the need for a lot of memory and a fast highway to that memory. But, AGP and Talisman approach the problems differently: AGP provides a fast path to system memory so that graphics accelerators can augment the local frame buffer with the typically much-larger system-storage space. Talisman, meanwhile, seeks to fundamentally change the way a system composes and renders 3-D scenes, thereby minimizing the amount of required memory and the need for a fast bus to auxiliary memory.

It should follow, therefore, that Talisman could significantly reduce the price of a capable 3-D graphics system, thus making the technology widely available. Although it might seem that AGP and Talisman wouldn't fit together in a system, closer examination shows how the technologies could fit together. Certainly, Talisman might not need the speed that AGP affords, but Microsoft and Intel are touting the two as potentially symbiotic technologies.

AGP quadruples PCI-bus speeds

Intel proposes AGP as a new point-to-point interface between PC core-logic chip sets and the graphics subsystem (Figure 2). Of the many attributes of AGP, increased data rates have garnered the most attention. Even if you think of AGP as a faster PCI bus, the technology has significant value when you realize that video and 2- and 3-D graphics data all pass over the bus in today's multimedia systems. AGP also provides a dedicated link to the graphics subsystem, although you often find disk controllers, LAN adapters, and other assorted peripherals sharing PCI- bus bandwidth with the graphics controller.

AGP does build on the PCI-bus architecture using a similar signaling scheme. At a minimum, the 32-bit AGP interface operates at 66 MHz, whereas most PCI implementations operate at 33 MHz. AGP also includes a bevy of optional features that all host-side implementations must support but that graphics-IC AGP interfaces can implement as needed. For starters, data transfers can occur on both leading and trailing edges of the clock--essentially doubling the clock speed again to 133 MHz. Whereas the PCI bus multiplexes address and data information using the same signals, AGP can optionally operate in a demultiplexed mode using sideband signals to convey address information.

Intel also developed a pipelining feature that works similarly to the way the Pentium Pro processor defers cycles on memory accesses. The pipelining scheme allows a graphics processor to issue multiple memory accesses across the AGP interface without waiting for the core logic to resolve the first request.

Theoretically, the AGP concept will allow a graphics controller to share main memory with the main CPU. Altogether, the AGP features can boost peak data rates to more than 500 Mbytes/sec, making access to main memory almost as fast as accesses to local frame buffers using synchronous DRAM. Intel has no plans for using AGP in a unified-memory architecture (UMA), in which the graphics subsystem has no local memory, although such implementations could be technically feasible. Instead, AGP enables a shared-memory architecture, and the host memory would serve primarily to store 3-D textures. Texture mapping proves to be a crucial feature in producing realistic 3-D images. For example, ISVs working on games would like to have 10 Mbytes or more of textures stored for ready access but often are limited to 600 kbytes or less in today's systems.

AGP sounds like a sure bet for implementation in PCs because it increases 3-D-accelerator performance. Moreover, the industry should be able to deploy AGP more quickly than the more radical Talisman architecture. Still, several hardware and software obstacles stand in the way of widespread AGP adoption this year.

Obviously, AGP can go nowhere until core-logic chip sets implement the new interface. Intel plans at midyear to ship AGP support in a chip set targeting the MMX-enabled, Pentium-Pro-class µP, code-named "Klamath." Intel plans no support of AGP in Pentium chip sets, claiming that the older µPs handle 3-D geometry calculations too slowly to warrant such support. Intel's position doesn't necessarily stand up to technical scrutiny because graphics accelerators can boost 3-D performance in Pentium systems and because relatively simple 3-D accelerators can handle texture mapping. Intel's position could have more to do with moving the bar up and establishing the Pentium Pro as the µP of choice for the masses.

Other chip-set vendors, such as Via Technologies (Fremont, CA), Opti (Santa Clara, CA), and Acer (Santa Clara, CA), hint that they may offer Pentium-class chip sets with AGP support. They have not announced such products, however, and history indicates that the market for Pentium µPs will shrink dramatically once Intel focuses its energies on the Pentium Pro. On the other hand, it could be a year or more before Intel can ship Klamath chips at Pentium price levels, especially given competition from AMD (Sunnyvale, CA) and Cyrix (Richardson, TX), which are both selling Pentium-class products. Moreover, AMD and Cyrix will likely offer Pentium-Pro-class µPs with Pentium pinouts.

From the 3-D-graphics-accelerator side, a few companies have already announced plans for AGP-enabled ICs, and you can expect virtually all of the players to support the new interface. Microsoft will host its annual Windows Hardware Engineering Conference (WinHEC) from April 8 to 10 in San Francisco, and you can expect more announcements around that time. Check the Leading Edge section of EDN in the April 10 issue for an update on AGP ICs.

In February, Cirrus Logic announced that it began sampling the CL-GD5465, an AGP version of its Laguna family of 3-D accelerators. The initial offering will operate at 66 MHz, and production volumes will ship next quarter for $29.50 (10,000). ATI Technologies has also announced its next-generation Rage III, which will be available in PCI and AGP flavors. In fact, ATI will offer both a low-end, 66-MHz version and a fully configured, 133-MHz version supporting all AGP options. In December, ATI publicly stated its opinion that any system storing textures in main memory would need a full AGP implementation.

Intel will finally enter the graphics-accelerator market with its Model 740 AGP chip. The company will ship the long-rumored device, code-named "Auburn," sometime after it ships the Klamath chip set. Auburn will include 2-D acceleration technology licensed from Chips and Technologies and 3-D acceleration technology licensed from the Real 3D division of Lockheed Martin.

AGP software requirements

Hardware, however, is only half the story with AGP. Even if you have host and graphics-IC AGP silicon in hand, you can at best use the interface as a fast PCI bus. To get the full benefits of AGP, you need new drivers for your operating system of choice, and Windows 95 is at the center of most AGP efforts.

Today, a Windows 95 application can't dynamically allocate memory and ensure that the graphics accelerator has access to the memory. Specifically, the graphics IC has no memory-management facilities that can keep track of a memory array that Windows might map into segments throughout the system memory. To take advantage of shared memory, a graphics accelerator must reserve a fixed and contiguous section of memory at boot time. Until Windows includes AGP support, companies that have experience loading textures from main memory could enjoy a significant advantage. For example, Cirrus Logic includes a 1-kbyte texture cache on its Laguna chip and has developed drivers that can allocate system memory at boot time to store textures.

Microsoft indicates that it will release AGP software along with Windows 97, code-named "Memphis," around midyear. The details of the AGP support are available to developers. Applications will use an extension to the DirectDraw API to dynamically allocate memory. At first glance, the AGP-software scenario seems to have no "gotchas" that could delay AGP deployment. Unfortunately, however, the fact that Microsoft has tied AGP support to a major Windows release could delay AGP. Microsoft has a poor record for shipping software on time, and Windows 97 supposedly includes major changes, including integration of Internet Explorer as the primary user interface.

Even in a worst-case scenario, AGP should appear before Talisman. Microsoft indicates that a Talisman reference design will be available late this year. Assuming that Microsoft and its partners hit that target, production implementations should lag behind the reference design by 12 to 18 months. The delay could be even greater, considering that Talisman fundamentally changes the approach to 3-D graphics and that several ICs from different vendors will comprise the reference design.

Microsoft based Talisman on the premise of coherence between successive frames or scenes. In other words, little changes between successive frames in a 3-D application. An object may move in the foreground, for example, while all other parts of an image remain static. Traditional 3-D graphics architectures render an entire scene 30 times/sec or more. Talisman will harness four key concepts--compositing, image compression, "chunking," and multipass rendering--to take advantage of coherence, presumably reducing memory and bandwidth requirements and, therefore, costs.

Talisman requires no traditional frame buffer. Instead, it stores each object in a scene in separate image layers that the systems can then composite to form the final image. Moreover, the compositing operation occurs in real time at the full video rate. The independent layers allow the graphics subsystem to update each object independently and only when an object changes. Moreover, the architecture lets a system simulate many typical 3-D transformations, such as scaling and rotation, using 2-D operations on the rendered object. The layering and compositing scheme ensures that image-layer transformations, such as motion, happen at 72 to 85 Hz, assuring fluid movement. The scheme does not guarantee fast layer updates, so it can at times trade geometric detail for the higher animation rates.

To ensure that geometric detail remains suitable, Talisman uses compression on both objects and textures. A JPEG-like technique, Texture and Rendering Engine Compression (TREC), handles the compression. Compression isn't a new idea, but graphics systems that use a conventional frame buffer can't process the entire image quickly enough to make compression feasible. Talisman skirts this roadblock using "chunking." Talisman breaks each image layer into 32×32-pixel chunks. The system renders all objects for one screen chunk before proceeding to the next and, therefore, requires a small Z-buffer. Moreover, the controller can apply sophisticated antialiasing filters and image compression in real time.

Chunking and compression combine to provide small memory requirements and allow a small shared-memory array to store all texture and image-layer data. The availability of such data allows the rendered data to feed back through the texture processor for use in rendering a new image layer. Such multipass rendering can generate special effects, such as shadows from multiple light sources, fog, underwater simulation, and waves.

Figure 3 depicts the reference design for Talisman. The Philips Trimedia processor will fill the role of Media DSP. It can handle floating-point 3-D geometry calculations, as well as other multimedia streams, such as compressed audio or video. Cirrus Logic is developing the Polygon Object Processor, and Samsung, Fujitsu, and Silicon Reality are also working on portions of the reference design. Microsoft believes that Talisman can reduce memory-bandwidth requirements by a factor of 60 and also support other multimedia functions.

Considering the breadth of Talisman, most 3-D-accelerator vendors believe that designers will at first employ portions of the technology to enhance traditional architectures. Some industry observers doubt that the entire Talisman model will ever be feasible. Don't dismiss Talisman too quickly, however, because Microsoft has invested significant resources to develop the technology. Moreover, Microsoft is targeting Direct3D to support a Talismanlike architecture, and Microsoft seems determined to force Direct3D on the PC community, whether you like it or not.

References

1. Quinnell, Richard A, "PC graphics struggle to incorporate 3-D," EDN, March 14, 1996, pg 61.
2. McComas, Bert, "MMX as a Direct3D Accelerator," InQuest, Gilbert, AZ, (602) 813-7785.

Acknowledgment

I would like to sincerely thank Bert McComas of InQuest (Gilbert, AZ) for his help in understanding 3-D hardware and software issues, and for the box he contributed to this article.

Maury Wright, Technical Editor You can reach Maury Wright at (619) 748-6785, fax (619) 679-1861, ednwright@mcimail.com.

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