March 27, 1997

Dynamic clock provides for zero wait states

Mike Nelson, Polaris Communications Inc, Portland, OR

The clock controller in Figure 1, which you can implement in a PLD, dynamically manipulates the timing of synchronous FIFO clock and control signals to provide for zero-wait-state accesses. These zero wait states would be otherwise impossible with a fixed clock design. This concept initially was developed for an embedded application that uses a RISC processor running at 25 MHz. The design goal was to make all the critical operations zero wait states, including SRAM and FIFO accesses and flyby DMA. After analyzing the constraints, achieving this goal was impossible using only one FIFO clock phase.

The solution involves dynamically switching the FIFO clock phase depending on whether the operation is a read or write. The synchronous FIFO also has enable and read/write inputs, and you must dynamically switch the timing of these inputs depending on the operation.

You first need a PLL clock buffer with programmable skew outputs, a feature that allows you to advance or retard clocks. A +4-nsec delayed FIFO read clock and a ­10-nsec early FIFO write clock provide the necessary timing to center setup and hold margins. For this design, a CY7B991 (Cypress Semiconductor, San Jose, CA) generates the 4-nsec delayed clock (+4 CLK) and the 10-nsec early clock (­10 CLK) in Figure 1.

While still in the address phase of the bus cycle, the FIFO controller must determine if the operation is a read or write in time to select the proper clock and enable timing. The ­10 CLK samples the bus address, WRITE, ADS (address-strobe), and BLAST (burst-last) control signals (Figure 1). The controller defaults to three-stating the FIFO outputs by normally keeping the FIFO in WRITE mode but not enabled. To meet system timing requirements, the controller also must default to the read-clock phase (+4 CLK).

For burst-read operations, the FIFO clock remains at the read-clock phasing for the whole burst bus cycle (Figure 2). Using the ­10 CLK, the FIFO controller samples the bus's address and control lines and determines that the operation is a FIFO read. The controller quickly asserts the FIFO enable and sets the FIFO READ/WRITE signal to read in time to meet the FIFO setup time. The FIFO then performs the read operation on the next edge of the +4 CLK. The FIFO controller continues to monitor the bus and waits for the BLAST signal indicating the end of the cycle. The controller continues asserting enable and read signals until the FIFO detects BLAST. When this happens, the controller quickly deasserts the FIFO enable, preventing the next FIFO read.

For the FIFO in this application, a 74ABT3614, the read signal is also an asynchronous output enable. If you deassert the read signal at the same time that you disable the FIFO enable, the FIFO three-states its outputs before the data meets the hold spec of the SRAM (or mP). For this reason, you need to continue to enable the FIFO outputs until after 4 nsec.

For burst-write operations, the controller uses the slow-enable turn-on path (+4 CLK), which asserts the enable after the +4-nsec read clock (Figure 3). This action prevents a FIFO-write operation on the read-clock phase, at which time the SRAM or mP data is not yet valid. The FIFO clock dynamically switches from read-clock timing (+4 CLK) to write-clock timing (­10 CLK) after the first read clock. The FIFO controller monitors the bus for the BLAST signal, which indicates the last FIFO write. After the FIFO controller detects BLAST, the controller deasserts the FIFO enable using the +4-CLK write turnoff path. The FIFO controller also switches the FIFO clock back to the read clock (using a +4-CLK control path) after it detects BLAST.

To prevent glitches, the FIFO-clock controller changes clock sources only when the currently selected clock and new clock are both high. When the clock phase switches, the pulse width and period of the FIFO clock change. You need to analyze the timing to ensure that the width and period do not violate your FIFO's clock specs.

The clock controller switches clocks at +4 nsec. When switching from the +4 CLK to the ­10 CLK, both clocks are high. In this case, the +4 CLK just went high and will remain high for 24 nsec. The ­10 CLK has been high longer and will remain high for 10 nsec. The result is a minimum high-clock-pulse width of 6 nsec. The minimum clock period is 26 nsec when switching from +4 CLK to ­10 CLK.

When the clocks switch from the ­10 CLK to the +4 CLK, the period and the pulse widths are larger instead of smaller. It is preferable to have no 6-nsec clock pulses, even though this pulse width does not violate the FIFO's clock spec. Incorporating clock-pulse shaping logic (which Figure 1's simplified schematic omits) increases the minimum clock-pulse width to 9 nsec with no additional timing skew.

Finally, this clock controller has "guard" terms that are similar in function to the "cover" terms in latches. Different delay paths inside a PLD can result in a situation in which neither clock source is selected when switching sources. The result can be an undesirable low-going glitch on the FIFO clock. The circuit in Figure 1 prevents this type of glitch by ORing fast turn-on paths with slow turnoff paths to produce the FIFO CLK output. (DI #2003)

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