March 27, 1997

WHAT'S HOT IN THE DESIGN COMMUNITY

Edited By Fran Granville

Near-field recording promises 10-times areal-density increase

Near-field recording could produce rotating storage devices one year hence that store 10 times as much data on one surface as today's optical or magnetic disk drives. Moreover, the hy-brid magnetic/optical technology promises to overcome price and per- formance obstacles that have stymied growth in magneto-optical (MO) drives. Terastor Corp has pledged to produce such products within one year, and the start-up company lists as principals some of the founders of storage-industry stalwarts Quantum (Milpitas, CA) and Maxtor (San Jose, CA). The company has also acquired licenses to key patents from Quantum and Stanford University (Stanford, CA).

Near-field disk drives will operate similarly to MO drives. A focused laser heats a spot, or "bit cell," on the rotating media while a magnetic field changes the state of the spot. An optical read element can detect the magnetic orientation of each stored bit via the polarization of reflected light. Near-field drives, however, will cost significantly less to build than do MO drives. MO drives use a costly, servo-based laser-focusing mechanism that has kept prices high, limited bit density, and prohibited the development of multiplatter or even double-sided drives.

Based on quantum rather than classical physics, Terastor's near-field technology leverages characteristics of light during a fraction of the first wavelength from the source to focus a laser. A solid immersion lens handles the focusing chore and results in significantly smaller bit cells than does MO technology. Moreover, the entire magnetic/optical head assembly will fly just like traditional Winchester disk heads, and the controlled flying height will ensure accurate laser focus. Prisms and mirrors will channel the laser energy to the head in multiplatter or double-sided drives, and subminiature lasers may eventually be mounted directly on each head. Together, the flying head and increased bit densities should allow near-field drives to match or exceed Winchester drives in seek time, rotational speed, and data-transfer rate.

Assuming that Terastor can deliver the flying-head technology at a price near that of Winchester heads, little stands in the way of near-field devices. The media should cost less than does traditional Winchester media because the near-field media can use a plastic substrate. The drives can use standard Winchester read channels, although the 10-times areal-density boost will allow near-field drives to take advantage of much faster read channels than are currently available. In short, the drives could challenge tape drives, removable disk drives, and standard hard drives for market share.

Terastor doesn't describe its initial product plans but insists that products will be on retail shelves in one year. You might envision a 3.5-in. removable disk drive like the 1-Gbyte Jaz from Iomega (Roy, UT), except that the near-field drive could store 10 Gbytes. Moreover, Jaz cartridges cost around $100. Based on current MO pricing, it's conceivable that the near-field cartridge could cost less than $20. Terastor also plans to license the technology to other data-storage vendors, so a plethora of product types could emerge in the next few years.

--by Maury Wright

Terastor Corp, San Jose, CA. (408) 324-2143, www.terastor.com.

Online service matches product developers to suppliers

Say you've got a great idea for a new product. Say you also need to get that product to market yesterday. For free information on companies that can help in all phases of product development, log onto www.developages.com, where you'll have access to the site's database of more than 12,000 companies that supply services to the OEM market. You can investigate business services (planning, legal, venture capital, recruiting), design services (electronic, graphic, industrial, packaging, testing), materials services (adhesives, plastics, packaging), manufacturing services (printing, molding), and sales and logisitics.

The site was designed for OEMs, but anyone can use it for free. A questionnaire helps you zero in on the appropriate suppliers. Service providers pay nothing to be listed, but they can also pay a fee to upgrade their profiles to include information on their full capabilities. Fees ranges from $300 to $1500/year for the first listing and $100 for each additional listing.

--by Joan Lynch

SupplyBase, San Francisco, CA. (415) 977-1290, fax (415) 977-1298, www.developages.com.

Trim your analog circuit via electrical programming

You can custom-trim an analog function to produce a desired current source, voltage source, or voltage-controlled resistor value--and thereby avoid trimming potentiometers or calibration circuitry and software--using electrically programmable analog devices (EPADs) from Advanced Linear Devices. The EPADs are CMOS FETs. They have adjustable threshold (bias) voltages that you set via a stored, nonvolatile charge; increasing the threshold voltage also corresponds to lowering the drain on current as a function of a given input bias current. You can set the threshold to 0.1-mV resolution over a 2000-mV range. Applications for these devices include adjustable filters, low-temperature-coefficient bias circuits, programmable-gain amplifiers, and sensor-interface circuits.

You program each EPAD, the quad ALD1108E and the dual ALD1110E, outside your final system by plugging the device into a DOS/Windows PC-based programming adapter, or "in-system," using the specified application circuit and algorithm. Although you can only increase--not decrease--the threshold voltage (and you can reprogram the device to a higher value), you can use different circuit configurations to implement designs that need both raised and lowered channel voltages. In volume quantities, EPAD devices cost less than $1; the programmer base unit costs $498, and programming adapter modules cost $149 and $199, depending on type.

--by Bill Schweber

Advanced Linear Devices Inc, Sunnyvale, CA. (408) 747-1155, www.aldinc.com.

Chip set lets both old and new sounds ride PCI bus

You can now provide both wave-table and MIDI (musical-instrument digital-interface) sound support on the PC via the PCI bus, as well as play existing "legacy" software, using a chip set from Ensoniq. The ES1370 chip set, comprising the AK4531 codec and ES1370 PCI-bus digital-audio and music controller, lets you build a lower cost sound board by eliminating the need for a wave-table ROM, because you use system RAM to hold MIDI sounds.

This chip set's AudioPCI architecture lets you still play DOS-mode games designed for the ISA bus. Although the PCI bus lacks the ISA bus's interrupt-request and DMA signals, a sound board using the Ensoniq ICs functions as if the signals were present and at the full speed of the PCI bus. The technology also allows software to implement sound-enhancement algorithms, such as reverberation, chorus, and spatial expansion, via the host processor and a multimedia-extension-enabled processor if present.

The chip set costs less than $20 (OEM). The 3V sound board using the chip set, the S5016, takes less than 4 in.² (26 cm²) of board space and costs less than $50 (OEM). The board provides wave-table sound; 16 MIDI channels; 16-bit record and playback; and standard microphone, joystick, speaker, and auxiliary connections.

--by Bill Schweber

Ensoniq Corp, Malvern, PA. (610) 647-3930, www.ensoniq.com.

Data-acquisition system looks like a DSO

Nicolet's four-channel Integra 20 looks like a scope. Indeed, the vendor calls it a scope. But the unit offers 12-bit resolution; modular, plug-in signal conditioning; differential inputs; real-time sampling only; and a maximum sampling rate of 1M samples/sec. So, a comparison with DSOs is unfair. Most DSOs sample much faster than do data-acquisition systems but offer lower resolution and much different features. The Integra 20's target application is physical measurements. For some researchers, the alternative products are PC plug-in data-acquisition boards--not scopes.

The unit captures as much as 2M samples/sec/channel in battery-backed memory and offers an integral chart recorder. An optional hard disk stores more than 500 Mbytes. Waveform-math features perform more than 50 functions. A slow-fast-slow acquisition mode lets you sample signals at a low rate to avoid using more memory than necessary. But you can temporarily increase the sampling rate when a phenomenon occurs that indicates the onset of a condition requiring more detailed sampling. Prices start at $11,500. Price for the Integra 10, a unit with memory of 200k samples/channel, starts at $6950.--by Dan Strassberg

Nicolet Instrument Technologies Inc, Madison, WI. (608) 276-5600, fax (608) 273-5061, www.test.nicolet.com.

Picture this: an HDL-to-graphics translator

If you believe that a picture is worth a thousand words, consider a new product from Summit Design. Visual HDL, the company's mixed textual/graphical VHDL design-entry tool, now has text-to-graphics capability. This option converts textual HDL-based electronic-system designs into graphical speci- fications.

You start the conversion by loading a VHDL file of any length into the Visual HDL database. You then invoke the text-to-graphics function, and the tool interprets the code and converts it into structural block diagrams (with hierarchy), state diagrams, and flow charts. The conversion preserves all embedded documentation and comments in the original code. You then edit, view, and modify the graphical version of the design in the same way as you would work on graphical files entered directly into Visual HDL. The text-to-graphics conversion eases graphical documentation of a design and provides a more intuitive way of visualizing and understanding design intent.

Text-to-graphics for Visual HDL, running on either PCs or workstations, will be available late in the second quarter for $10,000. Visual HDL prices start at $18,000. The same conversion capability for Visual Verilog, Summit's textual/graphical Verilog design-entry tool, will be available in the third quarter at a starting price of $18,000.

--by Jim Lipman

Summit Design, Beaverton, OR. (800) 661-4333, fax (503) 646-4954, www.summit-design.com.

Flash-memory architecture targets data, file storage

With voice, music, images, and video streams quickly "going digital," a variety of flash-memory manufacturers are aiming their products at this booming market. Atmel becomes the latest in that trend with the Serial DataFlash memory family. Data- and file-storage applications can tolerate serial interfaces and slow read cycles. In contrast, most flash memories sold today go into traditional code storage, or EPROM-replacement, applications. These de-signs require a parallel data-bus interface and fast read-access times but rarely exploit such flash-memory features as high write performance, fine-grained blocking, and extended cycling.

Perhaps the most notable feature of Atmel's new architecture is the 264-byte block, including 8 bytes for system-level error detection and correction in extended-cycling use. Fine- grained blocking simplifies the system's flash-file-system software and is compatible with small data samples, such as short voice messages. You can also hardware-lock the first 256 blocks via the write-protect pin. This feature is useful, for example, in digital answering machines that might want to secure the outgoing messages.

Two integrated RAM page buffers enable 264-byte or smaller read and write sequences as fast as 5 MHz via the flash memory's serial interface. If the system's data-write profile has 264-byte or smaller packets, interleaving between the buffers can hide the slower buffer-to-flash array write-transfer delay. The page buffers also allow simultaneous reads from one block and writes to another block. Again using the answering-machine example, this feature might allow for answering the phone (outputting the outgoing message) during background file-system-write cleanup operations. On-chip automation enables block comparisons with page-buffer data, reports progress of all operations via a status register and open-drain RDY/BSY# output, and can, if desired, automatically erase the block before writing it.

Many data- and file-storage systems are also portable, so low power consumption is important to maximize battery life. Atmel's Serial DataFlash memories operate as low as 2.7V; at that voltage, typical read, write/erase, and standby power-consumption specifications are 10.8 mW, 40.5 mW, and 32.4 mW, respectively. Typical page-program times, with and without automatic pre-erase, are 10 and 5 msec, respectively, at both 2.7 and 5V. Serial DataFlash memories typically transfer data from an array block to a page buffer in 120 msec in response to a system command.

The 4.5 to 5.5V AT45D041 and 2.7 to 3.6V AT45DB041, both 4 Mbits, are in production, and 2-Mbit devices are sampling. Atmel plans to provide a family of products from 1 to 16 Mbits by midyear to address varying application-density needs. Package options include 28-lead SOICs and TSOPs. Thanks to the serial interface, Data-Flash memories have lower pin counts and smaller pc-board footprints than do memories with parallel interfaces, and the family of densities will be pinout-compatible with each other. Atmel also plans to offer both commercial- and extended-temperature options. Price for the 5V commercial-temperature AT45D041 is $6.71 (1000) in the SOIC package.

--by Brian Dipert

Atmel Corp, San Jose, CA. (408) 441-0311, www.atmel.com.

Deeper submicron lifts your chip-design capabilities

NEC Electronics is offering three new ASIC products designed with its 0.25-mm drawn (0.18-mm effective) channel-length CMOS technology. You can design your system on a chip using CB-C10 cell-based, CMOS-10 gate-array, or EA-10 embedded-array (gate array with embedded cell-based blocks) technology. NEC is sweetening the deal with a range of digital and mixed-signal cores and a selection of high-pin-density packages.

The new gate and embedded arrays let you design chips with as many as 7 million gates. If you take a cell-based design approach, you can squeeze as many as 20 million gates onto your chip. Along with very high density, your chip can run with a clock rate as fast as 300 MHz. The ASIC library cells are power-stingy, with a dissipation of 0.04 mW/MHz/gate under nominal conditions. NEC has optimized the fabrication process for 2.5V and plans a future generation of ASIC cell families for 1.8V. NEC provides five metal-interconnect layers to build chips: the first for intracell routing and the next three for routing between cells and embedded cores. Flip-chip packaging consumes the fifth layer if you choose to use that package option.

NEC offers many types of cores and macrocells. You can mix and match proprietary and third-party RISC processors, DSP cores, bus controllers, networking blocks, and graphics cores. The arrays also give you the option of using both SRAM and DRAM, including a 32-Mbit synchronous DRAM that operates as fast as 150 MHz. For your memory requirements, you can select RAM blocks as large as 64 Mbits. For high-density designs, you need a way to get many I/O signals into and out of the chip. NEC gives you five packaging options, including plastic and tape BGA, QFP, a chip-scale package, and a flip-chip package with as many as 2000 pins.

Engineering samples of 0.25-mm products will be available in the second quarter, and production is scheduled before year-end. Prices depend on design complexity and package type. For example, a 3 million-gate, cell-based, 0.25-mm chip in a 420-pin tape BGA package will cost about $390 (10,000).

--by Jim Lipman

NEC Electronics, Santa Clara, CA. (408) 366-9782, fax (800) 366-9792, www.nec.com.

A/D pushes resolution, speed limits

A/D converter users want it all: higher resolution, faster sampling rates, and lower power. The 250-mW CMOS ADS7815 from Burr-Brown takes another step toward the "ideal" converter with 16-bit resolution while sampling at 250k samples/sec. This successive-approximation-architecture device includes a 2.5V reference, a sample/hold circuit, a sampling clock, and parallel three-state data output.

The converter targets ±2.5-input signal spans and operates from dual 5V supplies. THD is ­98 dB (typical) and ­96 dB (maximum) for a 100-kHz input signal; minimum SFDR (spurious-free dynamic range) is 96 dB with the same input, and SINAD (SNR and distortion) is 84 dB or better. The 28-lead SOIC costs $20 (1000).

--by Bill Schweber

Burr-Brown Corp, Tucson, AZ. (800) 548-6132, www.burr-brown.com.

Motherboards dig embedded applications

Motorola's Computer Group has augmented its mining the embedded market with two new motherboard families. The MTX family is an embedded version of the industry-standard ATX motherboard. The MBX family is a small motherboard with PC/104+- and PCMCIA-expansion capability. Both product lines should be in production during the second quarter.

The MTX family puts the PowerPC processor into a PC-motherboard form factor. The board offers standard PC-I/O capability, including PS/2 mouse and keyboard interfaces, EIDE disk controllers, and SVGA graphics, as well as PCI-expansion slots. To meet the needs of embedded applications, however, the MTX family goes beyond the PC paradigm. An MTX board also includes two PMC-expansion sites; a 100-Mbit Ethernet port; flash memory; and a choice of AIX (Unix), VxWorks, pSOSystem, LynxOS, or OS-9 real-time operating systems. Use of the PowerPC as the core processor allows MTX motherboards to meet the production-lifetime needs of embedded applications. Motorola controls production of its CPUs, allowing it to target MTX boards for three- to seven-year production life. Prices start at $1200 for boards with the PowerPC 603e CPU.

The MBX family provides a 5.7538-in. CPU board with two expansion options. An MBX board can accept a PCMCIA-Type 3 card and a stack of as many as three PC/104+ cards. The first family member, the MBX 860, uses a PowerPC 860 CPU, Ethernet, EIDE, keyboard, and mouse interfaces, and substantial memory options. The card has 4 Mbytes of DRAM, 4 Mbytes of flash memory, and 32 kbytes of nonvolatile RAM. The card also has one 168-pin DIMM slot that can accept as much as 64 Mbytes of additional memory. The board offers additional communications protocols with the I2C serial bus, four 16-bit timers, and a time-slot assigner for time-division-multiplexed communications. Prices for the board start at $745. An entry-level version without PC/104+ expansion starts at $545.

—by Richard A Quinnell  

Motorola Computer Group, Tempe, AZ. (602) 438-3000, fax (602) 438-3518.

Hitachi, EDN announce contest winners

Hitachi and EDN recently honored the winners of the SH-1 Design Contest, which concluded last August. The $10,000 Grand Prize Winner, the OmniMeter field-programmable instrument from DVP Inc, is a multipurpose signal-processing instrument that you can configure for multiple instrument applications via removable PCMCIA cartridges. Its designers are Andrew D Girson, Boris Donskoy, and Mark Price of DVP.  Winners in four other categories won $2500 per design. The prize for “Best/Most Complete Use of Peripherals” category went to a high-speed wireless modem; its designer is Kublir S Sandhu of Casio Personal Communications Laboratory. In the “Performance” category, Curtis Birnbach of Hudson Research Inc won for his design of an intelligent, autonomous instrument controller for a Space Shuttle experiment. Paul Whitcher of Data General won in the “Low Power” category for his design of a handheld computer, and Andrew S Huang of Qualcomm Inc won in the “Application Note” category for his design of a pulse-width modulator for a switching DAC.

—by Fran Granville

Hitachi Ltd, Semiconductor and IC Division, Brisbane, CA. (415) 589-8300, www.hitachi.com.

CALENDAR

March 31 to April 2
International Verilog HDL Conference (IVC-97), Santa Clara, CA, focuses on “HDLs: delivering tomorrow’s designs today.” Conference targets designers at all levels of Verilog-HDL use. MP Associates, Boulder, CO. (303) 530-4562.

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