April 10, 1997

Logic analyzers stamping out bugs at the
cutting edge

DAN STRASSBERG, SENIOR TECHNICAL EDITOR

Once just a hardware engineer's tool, logic analyzers now aid a more diverse group of users. The instruments also cope with formidable technical challenges to their own design--the result of growing speed and hardware complexity in the circuits under test.

As clock rates increase and complex µP cores embedded deep within million-plus-gate ASICs become commonplace, figuring out what really goes on inside state-of-the-art digital circuits becomes more difficult. For designers of instruments such as logic analyzers, creating test equipment that can indicate how today's leading-edge digital circuits behave is an enormous challenge. But that's only one side of the story on logic analysis in 1997. Other test-equipment designers, also working on logic analyzers, must grapple with much different but, arguably, equally challenging requirements.

The goal of this second group of instrument designers is to provide tools for the many EEs who use--or could use--logic analyzers to develop standard-technology products. Many such EEs consider logic analyzers hard to use and simply avoid them in favor of oscilloscopes, which are best suited only to an ancillary role in logic analysis. Most standard-technology products run at clock rates lower than 50 MHz and don't use core-based ASICs. Engineers who design these products need rugged, low-cost, easy-to-use instruments. Instruments targeted at these engineers must show the skeptics that logic analyzers improve productivity.

Test-equipment designers are enjoying success with both user groups. Certainly, the high-performance tools are more glamorous, but the lower cost, workhorse instruments may actually affect the work habits of a larger number of instrument users.

More distinctions

Many other important distinctions exist between high- and low-end logic-analysis tools. The development teams that use high-end tools are usually fairly large. On complex embedded-system projects, teams typically range from five to 15 members. According to Hewlett-Packard and Tektronix, such teams on average include five software engineers for each hardware engineer. In nearly all cases, the developers write high-level-language code--usually in C or C++.

High-performance-system teams are fairly large, and many of the developers are software engineers who are somewhat uncomfortable dealing directly with hardware. Therefore, debugging tools for this group emphasize networking and connectivity. Many high-performance logic analyzers attach directly to networks via connections that conform to the Transmission Control Protocol/Internet-Protocol (TCP/IP) standard. The logic analyzer is in a lab with the target hardware; the users usually sit at workstations in cubicles hundreds of feet or even thousands of miles away from the logic analyzers. Although remote users can't move probes, networking allows these users to do most things that someone next to the logic analyzer could do.

According to a study that HP commissioned, users of low-end tools tend to be smaller teams or even individuals. Some of the systems under development are not microprocessor-based but consist of special-purpose logic. Such products don't qualify as embedded systems; to be called by that name, a product must include at least one µP. Many other systems use 8- or even 4-bit µPs. The engineers frequently have hardware backgrounds, although many are adept at software design. Usually, such engineers are comfortable writing assembly-language code and are more likely to write in assembly language than are developers on larger projects.

Another characteristic of this market segment is a frequent concentration on electromechanical systems. Such applications involve signals that are relatively low in frequency, especially when compared with signals you encounter in communications and multimedia applications. Understanding the behavior of electromechanical systems often involves capturing long data records (several seconds or even several tens of seconds).

Long records are not restricted to electromechanical systems, though. An increasing number of logic-analysis problems in high-performance systems also require deep memory. Fortunately (and not altogether coincidentally), declining memory cost is bringing the cost of the needed record length within reach. (See box, "Logic-analyzer specs: some things to look out for.")

The first logic analyzers were timing analyzers--essentially DSOs with large numbers of channels and displays capable of showing only high and low logic levels. In contrast, most DSOs digitize analog waveforms into 256 levels. To be useful, a timing analyzer must trigger on combinations of signals and sequences of events that you hope relate to the problem you are troubleshooting.

Triggering is usually the mission of a state machine, which receives inputs from a group of pattern-recognition circuits (in essence, AND gates). Each gate looks at the logic levels on multiple signal lines. To define a qualifying event, you specify which lines must be high, which must be low, and which don't matter. A qualifying event moves the state machine to its next state but only if the event occurs when you've told the state machine to look for events of that type. After a predetermined event sequence, the state machine enters its last state and triggers data acquisition. Many logic analyzers' state machines let you define trigger sequences that comprise 16 or more events, or levels.

Although oscilloscope trigger circuits have become more sophisticated in recent years, logic-analyzer trigger circuits remain more complex in some ways. Generally, logic-analyzer trigger circuits accept a larger number of inputs and allow you to define longer sequences of events that must occur before triggering takes place. (See box, "Scopes and logic analyzers.")

Different ways to view data

As digital electronics grew in complexity, designers demanded an alternative to timing diagrams for viewing circuit behavior. Timing diagrams depict two-state data as simulated waveforms on multiple signal lines as a function of time, with time progressing linearly from left to right. An alternative is a state display, which presents binary data as 1s and 0s or as hexadecimal quantities. Each state appears on a separate line, with time usually running from the top to the bottom of the display. Because systems generally do not spend equal time in different states, the time scale of state displays is inexplicit and usually nonlinear.

Originally, state and timing analyzers were separate instruments. But the value of one instrument that presented both types of displays quickly became apparent, and combination state/timing analyzers soon became available. The original state/timing analyzers did not particularly well integrate their two functions, though. For example, these instruments required separate probes for the two types of displays. Sometimes, using separate probes is advantageous (for example, when you probe different pins for state and timing data). Usually, though, acquiring both types of data through one set of probes is desirable. (See box, "Probing--difficult and getting worse.")

Even when an analyzer can acquire state and timing information through one set of probes, the analyzer often can't simultaneously acquire both types of data. Customarily, you must select either the state or the timing mode. However, some recently introduced analyzers let you choose the display mode after they have acquired the data. (See box "Combining PCs and logic analyzers: two approaches.") With such an analyzer, you can display the same captured information in either format and switch back and forth between display formats to better grasp the data's meaning.

More meaningful than numbers

As µPs grew in importance, coding in binary, octal, and hexadecimal values quickly gave way to coding in assembly language. In assembly language, meaningful names (mnemonics) represent instructions or operation codes (opcodes). A state display that traces program execution using opcode mnemonics is much more intelligible than is one that uses numbers. To provide assembly-language displays, logic-analyzer vendors added accessory software tools called "disassemblers" (or, as HP calls them, "inverse assemblers"). A disassembler converts data flowing to and from the µP's memory into opcode mnemonics. Processor-specific pods usually accompany disassemblers.

The pods facilitate connection to µPs and perform functions such as grouping of related signals onto adjacent logic-analyzer inputs. Such pods either clamp over the µP on the target board or plug in in place of the µP and provide a duplicate µP socket. Even if a µP's address bus does not appear on sequential pins on the IC, the pod rearranges the signals so that the bus appears on sequentially numbered analyzer channels. The analyzer then displays the signals in a way that is easier to interpret than it would be if the signals were arranged as they are on the IC.

Gradually, most µP-based-system developers outgrew assembly language. Programmers needed languages that were more abstract than is assembly, which is tightly linked to the µP hardware. The combination of higher levels of abstraction, more complex languages, and much more powerful processors created and is still creating challenges for logic-analyzer designers.

For example, modern µPs fetch more instructions from memory than the µPs execute. Tracing program flow is easier if you don't have to look at long lists of instructions that the µP didn't execute. The problem is that when the µP decides whether to execute an instruction, the instruction already resides in cache memory within the µP chip. The logic-analyzer software tools or hardware you use with the analyzer must determine which instructions did not execute and exclude them from the program-execution record (trace).

Logic analyzers vs ICEs

While logic analyzers were evolving, a related tool, the in-circuit emulator (ICE), came on the scene. Since ICEs emerged, they have vied with logic analyzers for supremacy among hardware-based debugging tools for µP-based systems. ICEs' claim to fame is that they allow you not merely to observe the target system's behavior, but also to control target-system behavior in real time. To use a classic logic analyzer to control a µP, you must augment the logic analyzer with additional tools. Generally, even with those additional tools, the logic analyzer cannot control the target in real time the way an ICE can.

When you must debug critical timing-sensitive hardware-software interactions (usually one of the last steps in debugging), tools that consist mainly or entirely of software are inappropriate. At this point, you need a hardware-based debugging tool. Digital-hardware engineers have historically turned first to logic analyzers, whereas software engineers have used ICEs. However, ICEs' strength--the intimacy with which they interact with the target hardware--can also become an Achilles' heel.

Over the years, ICE designers have solved the problems of keeping up with faster µPs. A half-dozen years ago, working with a processor clocked at 16 MHz was considered next to impossible. Now, ICE designers consider 16 MHz and even 33 MHz a piece of cake. For more than a decade, ICE designers have shrugged off assertions that the next increase in clock speed would spell certain doom for their products.

This time, though, those assertions may well prove true, according to EDN columnist Jack Ganssle, president of ICE manufacturer Softaid Inc (Columbia, MD). Conventionally designed ICEs--in which an emulation processor takes over for the target µP--will continue for at least a decade to serve the needs of the tens of thousands of developers who design with 8- and 16-bit µPs. But newer, faster processors will force different approaches. The tools may still use the name "ICE," but the architecture will be different. Controlling the target processor and looking at its internal registers increasingly will depend on debugging facilities designed into the µP chip.

Chip features offer visibility

Most recently designed Motorola (Phoenix) processors include background-debug-mode (BDM) ports. Newer µPs from Intel (Santa Clara, CA) and others incorporate IEEE-1149.1 ports. These ports are also known as JTAG ports, for Joint Test Action Group. JTAG was the predecessor of the committee that drafted the IEEE-1149.1 standard. Ports of both types allow you to serially transfer data to and from points within the µP. But the serial transfer is relatively slow, requiring more than n clock pulses to transfer n bits. In general, too, the clock speed at which you can transfer data is lower than the clock speed at which the µP normally runs.

So, when debugging tools use serial ports, the tools sacrifice some real-time capability for control and for part of their ability to let you observe system behavior. Currently, the sacrifice appears unavoidable. Moreover, some industry observers aver that those who insist that ingenious ways to retain real-time control will emerge are unwittingly betting on the repeal of the laws of physics.

A related, albeit far less important, issue is what you call a debugging tool that combines logic analysis with support for a BDM or an IEEE-1149.1 port. Is it a logic analyzer, an ICE, or something else? According to one school of thought, a unit that displays timing diagrams deserves the name "logic analyzer."

No time to develop tools

Despite ICEs' popularity among embedded-system developers, logic analyzers, rather than ICEs, are the mainstay for debugging several classes of leading-edge products, including PC motherboards and graphics cards. Developers of these products do not use ICEs, because the products under development have short life cycles and use the latest processors. Classic ICEs for new µPs take too long to develop and so are not available soon enough. Logic analyzers are more general-purpose than ICEs are and so are available sooner. Processor-specific logic-analyzer accessories are easier to develop than new ICEs are. These accessories are also available fairly early in the µP life cycle.

The early availability of logic-analyzer support for new processors is a logic-analyzer strong point. However, ICEs' delayed availability has not significantly precluded their use. Most ICEs are used in embedded-system development, and embedded systems have historically not been among the first users of new µPs. Thus, ICEs that support new µPs have usually become available when embedded-system developers have needed them.

Combining PCs and logic analyzers: two approaches

When you think of logic analyzers, don't think only of benchtop instruments and rack-mounted systems. You can also obtain logic analyzers in the form of PC plug-in boards. However, plugging such a board into a PC is not the only way to combine a logic analyzer and a computer. Tektronix's new TLA 700 series builds the PC into the logic analyzer. Although the idea of putting a PC inside a logic analyzer dates back to the 8080 µP and the CP/M OS, Tek's implementation offers many new features.

Although the number of companies that offer logic-analyzer boards has been shrinking, two US companies, Link Instruments and NCI, continue to offer PC-based logic analyzers. Both companies have many years' experience with logic-analyzer products.

Don't think that when you opt for a logic-analyzer plug-in, you must necessarily lower your performance expectations. For example, Link's LA4000 series permits expansion to 160 channels, acquires data at speeds as high as 500 MHz, provides capture memory to 512 kbits/channel, and offers a 16-level trigger state machine. In addition, the company offers PC-based companion products, including PC-based digital-pattern generators, which can produce patterns as wide as 160 bits, and digital-oscilloscope boards that take as many as 200M samples/sec.

A little more than $1000

Link's lowest priced logic-analyzer board is the LA4240-32K, which costs $1350. This board offers 40 32-kbit memory-depth channels, all of which operate from 1 Hz to 100 MHz with an external clock or to 80 MHz with a dc-coupled clock. You can combine 32 of these channels into 16 channels that have twice the sampling rate and memory depth, leaving eight channels with the basic 100-MHz sampling rate and 32-kbit memory depth. A unit that offers 160 100-MHz channels with 32-kbit/channel memory costs $7000. You can configure this unit to provide 32 500-MHz channels with memory of 512 kbits/channel and 32 125-MHz channels with 128 kbits/channel.

NCI's offerings begin with the $1125 PA 485 board, which provides 48 50-MHz channels with memory of 4 kbits/channel. The company's systems comprise a logic-analyzer card, a general-purpose pod with interface cable, and a lead set for the pod. The top-of-the-line configuration costs $3995 and provides 48 100-MHz channels with memory of 256 kbits/channel. This configuration can also apply a 32-bit time stamp to the captured data. You can configure this system to provide 12 400-MHz channels with memory of 1024 kbits/channel, and you can add a second board to double the number of channels.

Several of NCI's boards support transitional timing, a technique that greatly increases a logic analyzer's effective memory depth. Instead of capturing data at each clock tick, an analyzer in the transitional-timing mode captures data only when a signal changes state. The analyzer records the time at which each state-change occurs and thus can reconstruct the original data. NCI also provides disassemblers for µPs from Motorola (Phoenix), Intel (Santa Clara, CA), Hitachi (Brisbane, CA), Texas Instruments (Dallas) , and Rockwell (Newport Beach, CA). NCI says that its pods also work with HP preprocessors.

This past February, Tektronix announced the TLA 700 logic-analyzer series. These products decisively refute the idea that PC-based instruments either must offer less than state-of-the-art performance or must deny users access to the embedded PC's functions. Among the analyzers' noteworthy features is the combination of sampling speed (2 GHz) and memory depth (512 kbits/channel). However, even nontechnical people notice the full-color Windows 95-based user interface. Because nearly all potential users are familiar with this interface, learning to use these analyzers is unusually easy--despite the large feature set.

The modular units offer 2-GHz timing and 100- and 200-MHz state analysis, 512 kbits of memory per channel, and as many as 680 channels (272 channels in the portable configuration). A single set of probes provides simultaneous access to the state and timing analyzers; you need not connect separate probes for each mode. The passive probing system is pin-compatible with but provides four times the connection density where the probes attach to the unit under test than do probes of earlier Tek logic analyzers. Besides logic-analyzer modules, the mainframes accept DSO modules, including one whose performance resembles that of Tek's stand-alone TDS 684--5G-sample/sec real-time acquisition, 1-GHz bandwidth, four channels, and 15k-sample/channel memory depth.

Sampling not unlike some DSOs'

The heart of the logic analyzers' acquisition system is a technology that Tek calls MagniVu. In each tick of a 250-MHz clock, the analyzer takes eight samples at 500-psec intervals. The analyzer stores these samples in two places: off chip, in conventional RAM, at full memory depth, with a timing resolution of 4 nsec (asynchronous capture) or 5 nsec (synchronous capture); and on chip, with 500-psec resolution and a memory depth of 2-kbits/channel. With this architecture, you can view a state analysis and without resampling zoom to a timing view of a critical segment with an eight-times resolution improvement.

One of the triggering-system features is true S/H violation triggering. You can trigger an acquisition if an S/H interval is either too short or too long, and you need not choose between too short and too long when you set the trigger specifications. Moreover, the trigger state machine is 16 levels deep. The systems use a menu-driven graphical interface to answer a frequent complaint of logic-analyzer users--that trigger setups are confusing.

The TLA 704 portable mainframe with a 10.5-in., 6403480-pixel color LCD costs $9000. The TLA 711 benchtop mainframe costs $14,000. Logic-analyzer-module prices start at $5000. DSO-module prices start at $10,000. The high-density probes in 34-channel groups cost $995.

Logic-analyzer specs: some things to look out for

Although a logic analyzer's basic functions are not hard to understand, the instrument's specifications can be confusing. Vendors don't make the prospective purchaser's job easy, either. Data sheets present more than their share of pitfalls. In fact, after reading a few data sheets, you can easily conclude that the manufacturers think that instrument buyers have nothing to do but study logic-analyzer data sheets.

Among the easiest traps to fall into is failing to recognize that, on many logic analyzers, you can't sample the advertised number of channels at the advertised sampling rate. Also, if you try to sample at the advertised rate, the memory depth is often just a fraction of the advertised amount.

These compromises result from the instruments' architecture--and from the irrepressible nature of marketing people. Many logic analyzers achieve the maximum sampling rate by multiplexing. For example, a unit that can sample 64 channels at 25 MHz might be able to sample 32 channels at 50 MHz and 16 channels at 100 MHz. The analyzer assigns unused input circuits to channels that are in use and combines the input circuits' outputs to produce the display. In most cases, an analyzer operating this way also adds the reassigned channels' memory to that of the channels to which you've connected the input signals. Thus, a memory depth of 4 kbits/channel with 64 channels active might increase to 8 kbits/channel with 32 channels active and to 16 kbits/channel with 16 channels active.

The data sheet might well tout 100-MHz sampling, 64 channels, and 16-kbit/channel memory depth, but you can't have all three at the same time. Similarly, an analyzer that offers both state and timing modes might use the same probes for access to both modes. However, the analyzer might force you to use different probes for each mode. And if the analyzer does let you use the same probes for state and timing, you still might have to reacquire the data to display it in the other mode. Only a few analyzers can change the display mode for data they've already captured. When you finally capture a record of a malfunction that rarely occurs, changing the display mode without recapturing the data can save lots of time.

Scopes and logic analyzers

Digital scopes and logic analyzers are natural allies in the war against hardware and software bugs. As circuit speeds increase, analog effects become even more important. One example is reflection in pc traces. (Traces can act as transmission lines for high-speed signals.) You need a scope to see such a phenomenon. Having the scope inside your logic analyzer can save a few dollars and much-needed bench space. If you use a separate scope, make sure that the logic analyzer's trigger circuits can drive a cable to the scope's trigger input.

Modular logic analyzers, such as HP's 16500 series, have long offered the option of adding DSO plug-ins. More recently, HP brought DSO capabilities to its benchtop logic analyzers. The S versions of HP's 1660 series of 100-MHz state/500-MHz timing analyzers include two-channel, 250-MHz, 1G-sample/sec DSOs with memory of 8k samples/channel. The scope feature adds $6500 to the price of the analyzers. Without the scope, the analyzer costs $5900 for a 34-channel unit to $11,900 for a 136-channel unit. All units offer logic-analyzer memory of 4 kbits/channel when you use all channels, and 8 kbits/channel when you use half the channels. When you perform 500-MHz timing analysis, you can use only half the channels.

Of course, HP is not alone in offering DSOs in combination with logic analyzers; Tektronix also offers them. The new TLA 700 series includes a $17,000, 1-GHz-bandwidth, two-channel DSO plug-in that takes 5G samples/sec/channel and provides a 15k-sample/channel memory. Tek also offers lower cost units as well as a four-channel version. Among manufacturers of PC-based logic analyzers, Link Instruments combines DSOs with logic analyzers.

Half logic analyzer, half scope

HP targets its logic-analysis products (the 16500 series, the 1660 series, and the deep-memory benchtop units that comprise the 1670 series) to people familiar with logic analyzers. Within the last few years, though, HP has recognized the untapped potential of logic analyzers among engineers whose primary debugging tool is a scope. For these people, HP has brought out several logic-analysis products in its 54600 series. That series began life as a DSO family and, in the main, continues to be one.

The most recent addition, the 54645D, is a natural for scope users employing logic analysis for the first time. The product, which HP calls a "mixed-signal oscilloscope," combines a two-channel DSO with a 16-channel logic timing analyzer, all for $4995. (The otherwise-identical 54645A omits the logic analyzer and costs $3495.) When you use all 16 logic-analyzer channels, the unit samples each logic-analyzer input at 200M samples/sec. If you use only eight logic-analyzer channels, the sampling rate doubles. Considering their low prices, perhaps the most remarkable aspect of both 54645 products is their deep memory. Memory depth is 1M sample/channel (for both the DSO and the logic-analyzer functions). The products also incorporate HP's MegaZoom architectural feature, which lets you highlight portions of scope or logic-analyzer traces for examination with greater time resolution. You can then reacquire only the portion you've highlighted without figuring out how to reset the sweep speed or the trigger delay.

For more information…
When you contact any of the following manufacturers directly, please let them know you read about them on EDN's website. Note: All Web addresses start with http:// unless otherwise noted.
Embedded Performance Inc Milpitas, CA (408) 434-2210 fax (408) 435-7970 sales@episupport.com	Hewlett-Packard Co Santa Clara, CA (800) 452-4844 www.tmo.hp.com	Lauterbach Inc Framingham, MA (508) 620-4521 fax (508) 620-4522 info@lauterbach.com www.lauterbach.com
Link Instruments Fairfield, NJ (201) 808-8990 fax (201) 808-8786 sales@linkinstruments.com www.linkinstruments.com	NCI Huntsville, AL (205) 837-0667 fax (205) 837-5221 nci_usa@ro.com www.nci-usa.com	Tektronix Inc Beaverton, OR (800) 426-2200 www.tek.com/measurement
Thurlby Thandar Instruments Ltd Huntingdon, Cambs, England +44-1480-412451 fax +44-1480-450409

Probing--difficult and getting worse

As circuit features become smaller, attaching probes becomes more difficult. As circuit speeds increase, the effects of probe capacitance and ground-lead inductance become more significant. Logic-analyzer manufacturers constantly search for ways to improve logic-analyzer probes, mostly to stay even with advances in the packaging and performance of the circuits under test.

At the point where they connect to the circuit under test, the probes Tektronix introduced with its TLA 700 series are one-fourth as large as those of earlier Tek logic analyzers. Still, the interface between the probe cables and the instrument is compatible with earlier Tek products. Therefore, you can use existing processor-specific pods with the new analyzers.

Don't move that probe!

Perhaps the most innovative probing system developed for use with a logic analyzer is HP's MultiProbe. MultiProbe is not for everyone, however, and it is not cheap. MultiProbe addresses several problems, including getting undistorted signals to a logic analyzer's oscilloscope channels and switching easily among signals without repositioning probes.

MultiProbe's key to making quick, reliable contact with high-pin-density ICs in QFPs is a retainer that you glue to the top of the IC. HP provides a fixture to accurately locate this retainer. A probe containing a personality adapter that you configure for a specific IC fits over the retainer. When you configure the personality adapter, you designate which IC pins are signals, which are grounds, and which are power lines.

A module that plugs into the 16500C logic-analyzer mainframe lets you easily designate which signals to route to scope channels. You can specify the signals you want to view by typing in their names or by using the 16500's large rotary control. The MultiProbe control module for the 16500C costs $5000. Pod prices start at $2900.

Looking ahead

Logic analyzers are at a crossroads. They have long been the primary debugging tool of digital-hardware-design engineers. Unfortunately, the number of such engineers and hence the demand for the tools they use are no more than holding constant and are probably declining. The real growth in potential debugging-tool users is among software engineers. According to both HP and Tektronix, software engineers now outnumber hardware designers by about five to one in embedded-systems development teams.

Traditionally, software engineers' main hardware-based debugging tool has been the in-circuit emulator (ICE). But after enduring for years, despite forecasts of its imminent demise at the hands of higher µP speeds, classic ICE technology may finally be nearing the end of the road. Most likely, ICEs will survive by converging with logic analyzers until the two become indistinguishable. Indeed, tomorrow's debugging tool may begin life as a logic analyzer and, through field upgrades over a few months or years, turn into a unit that performs most ICE functions.

Such hardware-based debugging tools are also likely to have chameleonlike personalities. In the hands of hardware designers, these debugging tools will present classic logic-analyzer displays, particularly timing diagrams. In the hands of software engineers, these tools will present high-level-language source-debugging displays. Like many logic analyzers and unlike most ICEs, these instruments will include scope displays or offer them as options. At a minimum, future logic analyzer/ICEs will include features for triggering external scopes.

Other features to look for in next-generation logic analyzers and ICEs include enhanced post-acquisition data analysis and display. Currently, these functions require extra hardware. Tektronix provides such capabilities via a software package called LA-Browser, a source-code browser that runs on Sun workstations. Prices for the software plus a single-seat license start at $2950. HP implements similar features via software packages called software analyzers, of which HP offers two. The $2000 B4620A runs on the $4995 16505A prototype analyzer, an accessory to the 16500 series. The B3740A is available for Sun and HP workstations and MS-DOS PCs. A single-user license and documentation cost $2000. Because logic analyzers' processing power continually increases, enhanced analysis and display will almost certainly be basic parts of future instruments.

Dan Strassberg, Senior Technical Editor

You can reach Senior Technical Editor Dan Strassberg at (617) 558-4205, fax (617) 928-4205, ednstrassberg@cahners.com.

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Logic analyzers stamping out bugs at the cutting edge

Logic analyzers stamping out bugs at the
cutting edge