April 10, 1997

FRAM:ready to ditch niche?

BRIAN DIPERT, TECHNICAL EDITOR

FRAM is the latest memory technology to emerge from the R&D labs, and both its specifications and future predictions look great--on paper. After years as an "almost-here" technology, is FRAM finally ready for cost-effective, high-volume production?

New memory technologies, such as the first EEPROM, SRAM, or DRAM, are rare, occurring perhaps every decade or so. These new approaches are the fundamental innovations upon which engineers make—and sometimes lose—fortunes and which create companies and, ultimately, industries. The latest such technology, ferroelectric RAM (FRAM), has finally emerged after years of R&D and limited production. The technology has been "almost here" for a long time, partially because of excessive industry speculation and overenthusiastic manufacturer predictions.

But will FRAM remain a low-volume niche or live up to its hype and become the next high-volume mainstream memory? Some information on FRAM should help you decide. And decide you must, because selecting the right technologies and products for your next project is a crucial part of your job: Pick right, and you’re a hero; pick wrong, and you’re in trouble.

The basic theory behind FRAM has been around since the 1950s. (See box, "FRAM technology: decades of development".) However, silicon quality and processing characteristics at the time and for the next quarter-century or so slowed development to a virtual standstill. Ramtron Corp resurrected the technology in 1984 and, in 1988, unveiled a 256-bit memory based on 4-µm design rules. This first FRAM device used a six-transistor, two-capacitor (6T-2C) structure that functionally operated as an SRAM cell with nonvolatile backup. This architecture took up a lot of silicon area, limiting the effective density per component or, in other words, increasing the memory cost at a given density.

In 1992, Ramtron introduced another FRAM, which the company based on a simpler and smaller two-transistor, two-capacitor (2T-2C) cell structure (Figure 1a). Ramtron manufactured the 4-kbit device on a 1.5-µm process. The highest volume design win for this memory was Sega’s (Redwood City, CA) Sonic the Hedgehog cartridge, in which the FRAM stored game parameters for instant resume on power-up. Unfortunately, Sega has switched to CD-ROM for its newest game platforms.

Today, Ramtron provides a broader product line than any other FRAM vendor, in densities of 4 to 256 kbits; with I²C, serial-peripheral (SPI), and parallel interfaces; and on process lithographies as small as 1 µm. Voltage options include 4.5 to 5.5V and 2.7 to 3.6V, and devices operate at 0 to 70°C commercial and –40 to 85°C extended temperature ranges. Work in progress includes conversion to stacked- or trench-capacitor structures and smaller one-transistor, one-capacitor (1T-1C) cells (Figure 1b). Ramtron targets year-end for sampling of these devices and future migration to multilayer-metal and finer lithography processes.

Until a few years ago, Ramtron alone essentially drove process and product development, using a relatively low-technology fabrication facility. Today, however, the company has assembled a robust list of licensees that together represent some of the biggest names in nonvolatile and volatile memories. This year, Ramtron signed licensing agreements with both Samsung and SGS-Thomson. Licensing relationships have existed with Fujitsu since 1996, Toshiba since 1995, Rohm since 1993, and Hitachi since 1992.

Ramtron’s Mike Alwais, director of marketing, admits that the company needs these partners’ leading-edge process development and manufacturing capability to move the technological reality closer to its theoretical promise. The agreements Ramtron has secured with most of its licensees include an option for guaranteed capacity at their manufacturing plants. According to Alwais, the company plans to leverage this subcontractor capacity for commodity memories and reserve internal capacity for more proprietary differentiated products, such as memories for smart cards.

Rohm, one of the few partners currently shipping products, has a 16-kbit serial device in production and 4- and 64-kbit serial memories in development. Rohm will focus primarily on lower density, stand-alone FRAMs and on integrating FRAM with other memory technologies and logic on one device.

Hitachi is also sampling its first FRAM, a 256-kbit parallel-interface memory on a 0.8-µm process technology. Hitachi’s 3V HM71V832 offers a 150-nsec read access and symmetrical 235-nsec read and write cycles. Active and standby current draws are 20 mA and 15 µA, respectively. The HM-71V832, which Ramtron second-sources, offers 10-year data retention, 10¹² cycles, and 28-pin SOP and TSOP options.

Tony Carbone, Hitachi’s nonvolatile-memory product marketing manager, states that the company hopes to introduce its next product, a 1- or 4-Mbit device, within two years. The company will base the device on a next-generation, 0.5-µm, multilayer metal process and a 1T-1C cell that uses a stacked capacitor. Before introducing that product, Hitachi plans to reduce the cost of a 256-kbit device with a 0.5-µm, 1T-1C, nonstacked cell.

The other licensees, Fujitsu, Samsung, SGS-Thomson and Toshiba, are at various stages of technology and architecture evaluation. Fujitsu’s 1-Mbit device is in design, according to both Ramtron and Fujitsu’s Masao Taguchi, director of the DRAM Division’s memory-design department. In October, Samsung announced the development of a 64-kbit device using a 1T-1C, stacked-capacitor cell and double-layer metal processing.

Several additional large semiconductor manufacturers are going it alone, at least for the moment, in developing their FRAM technology. At the 1996 International Solid State Circuits Conference (ISSCC), for example, NEC delivered a paper on a 3.3V, 1-Mbit device with 60-nsec access time and 100-nsec read/write time. The company based this memory on a 1-µm, 1T-1C cell with strontium-bismuth-tantalum-oxide dielectric material and with 50-mA active and 10-µA standby current specifications. The device approaches the read and write speeds of today’s DRAMs.

Meanwhile, Sharp’s last public disclosure of technological developments was a paper delivered at the 1994 International Electronic Devices Meetings. The paper discussed a 256-kbit memory with a 0.6-µm, 1T-1C, stacked-capacitor cell.

Both Micron Technology and Matsushita presented at the 1994 ISSCC. Micron’s paper provided an overview of FRAM technology and applications but disclosed no development plans or status. Matsushita and Symetrix discussed a 3.3V, 256-kbit FRAM with a 100-nsec access time. The companies based the device on a 1T-1C-cell, single-layer-metal, 1.2-µm process using a Y-1 non-PZT (lead-zirconate-titanate) dielectric.

Ramtron and Hitachi’s documentation reveals their goals to sell FRAM into designs using memories such as nonvolatile RAM, battery-backed SRAM, or EEPROM and later to extend this "cannibalization" to low-power SRAM and low-density flash memory and DRAM. Other FRAM vendors also express these ambitions. Meanwhile, these companies all view FRAM as the ideal memory technology for emerging applications, such as smart cards and RF identification (RFID). This application, which often both reads from and writes to the memory media, draws all power solely from the wireless link between an RFID system and a transceiver via the transceiver’s radiated electromagnetic field. RFID requires fast and low-power reads and writes both to minimize transaction time and to maximize allowable distance between the RFID system and the transceiver.

How realistic are these FRAM goals? Some engineers are reluctant to seriously consider FRAM based on its less-than-stellar past performance at translating predictions to reality. However, assuming FRAM eventually overcomes this bad reputation with sufficient industry focus, you still have to compare fundamental attributes of the various technologies (Table 1).

Manufacturers aiming to decrease costs and increase density are working toward one goal: integrating more and more memory bits in a cost-effective silicon implementation. However, cost-effectiveness depends on a variety of factors. First, how much silicon area do designers devote to each bit of stored information? The earliest 6T-6C FRAM cell structure was large and complex, whereas today’s 2T-2C approach is roughly twice the size of the DRAM and EEPROM alternatives and three times that of a one-transistor flash-memory cell on equivalent-process lithographies.

On the other hand, a 2T-2C FRAM cell is smaller than both four- and six-transistor SRAM and clearly smaller than nonvolatile RAM’s redundant SRAM and EEPROM. Future migration to the 1T-1C architecture and stacking of the capacitor above or trenching it below the transistor should further cut FRAM-cell size to more closely resemble that of DRAM. In fact, Hitachi is evaluating an FRAMlike cell as one means of developing future cost-effective gigabit-sized DRAMs. FRAM capacitor dielectric constants, which measure the charge-carrying ability of the capacitor, are higher than those of today’s silicon-oxide compounds, enabling much smaller capacitors and, therefore, more cost-effective silicon.

Another issue when determining FRAM’s cost-effectiveness is other circuitry on the memory die or module. These circuits include interconnects, decoders, sense amplifiers, output buffers, and any on-chip voltage pumps. FRAM advocates point out FRAM’s advantage here over EEPROM and EEPROM-based memories. FRAM write operations directly use the 3.3 or 5V supply voltage vs pumping up to a higher internal voltage. Because FRAM currently focuses more on low-power operation than on high-speed access, vendors need not devote precious silicon area to large, fast output buffers. Again, future conversion to the 1T-1C cell will also simplify and minimize the size of sense amplifiers and bit-line interconnections.

FRAM also eliminates the need for separate power-management circuitry and the batteries that battery-backed SRAM requires. However, Dallas Semiconductor’s Drew Jenkins, memory-products manager, states his company’s intentions this year to integrate SRAM and power management on one die.

Process-lithography size and its compatibility with other semiconductor devices also influence cost-effectiveness. Today’s leading-edge µPs, DRAMs, and SRAMs use 0.3- to 0.4-µm lithography processes, whereas FRAM employs older 0.8- and 1-µm technology. This approach allows FRAM vendors to leverage equipment and processes with already-amortized costs and well-understood characteristics. However, using the older technology limits the effective bit density for a given die size, outweighing equipment costs in high-volume manufacturing.

Hitachi hopes to be only one process lithography behind DRAM within two years and to close the gap even further when the FRAM market size begins to more closely resemble that of today’s DRAM market, which is approximately $25 billion in worldwide sales, according to market-research company In-Stat (Scottsdale, AZ). Hitachi’s Carbone also points out that FRAM processing is approximately 75% compatible with DRAM; differences exist only in the last few manufacturing steps, including deposition of the ferroelectric dielectric material.

Other FRAM vendors, however, are more conservative in their process- and equipment-compatibility estimates and point to the continuing challenge of high-volume, low-cost manufacturing with complex ferroelectric materials. The degree of process compatibility defines a company’s ability to leverage technology and equipment development across multiple technologies.

Atmel’s Ken Kwong, vice president of marketing for memory products, and Microchip Technology’s David Wilkie, senior product-development engineer, challenge FRAM predictions. They point to the significant volume-cost lesson they learned from participating in almost 15 years of EEPROM development and innovation. FRAM’s limited production life does not yet allow the technology to match EEPROM. SRAM’s established presence as a mature memory technology should also allow it to compete with FRAM from a cost standpoint, at least for a while.

Multiple FRAM manufacturers and standardization among their products both have strong potential for lowering costs. DRAM’s impressive density, cost, and architectural innovations exemplify what happens when many companies, both collaborating and competing with each other, bring their collective weight to bear on problems. Unlike flash memory, for example, in which engineers face a bewildering array of contradictory packages, pinouts, command sets, voltages, internal architectures, interfaces, and specifications, FRAM provides some encouraging news.

Many FRAM manufacturers are also large DRAM suppliers and understand the benefits of standardization for a radically new technology. Hitachi’s Carbone, for one, states his intentions to aggressively pursue standardization and points out his company’s FRAM command-set compatibility with EEPROM.

Ramtron’s devices are also command-set-, package-, and pinout-compatible with EEPROM, SRAM, and nonvolatile RAM. However, isolationist business decisions sometimes supersede good standardization intentions stated up-front. Of concern is the fact that each of Ramtron’s partners is developing its own variation on the core FRAM technology and not necessarily sharing that accumulated knowledge with other manufacturers. Whether this situation will splinter the FRAM market in the future remains to be seen.

Serial-interface memories inherently find use in data-storage and -retrieval applications that value minimal pin count more highly than access time. Today’s serial-interface FRAMs, with their I²C and SPI options and as great as 2.1-MHz performance, appear to meet many system needs, although Xicor recently announced SPI EEPROMs with as great as 5-MHz frequencies, and several EEPROM vendors also offer I²C devices that operate at frequencies higher than FRAMs specify. Meanwhile, EEPROM but not FRAM supports the MicroWire serial interface, which constitutes approximately 25% of Microchip Technology’s yearly EE-PROM shipments, according to Wilkie.

Parallel-interface FRAMs present a more ambiguous decision, because you can potentially use these devices in both code and data applications. Both RAM-based alternatives, such as battery-backed SRAM and nonvolatile RAM, and EEPROM provide faster read accesses, especially when you add FRAM’s post-read internal precharge and rewrite delay. Atmel’s Kwong claims that approximately half of the company’s product shipments offer read accesses faster than 120 nsec.

On the other hand, FRAM’s sustained write times are orders-of-magnitude faster than are those of both serial- and parallel-interface EEPROMs, although still slower than are RAM-based technologies.

Mike Watson from Strata Design (Tadley, Hampshire, UK), who has evaluated both serial-interface EEPROM and FRAM, states, "FRAM’s main benefit for me is losing the 10-msec write-cycle time. I recently designed the Ramtron FM24C16 into a Microchip PIC-based touchscreen decoder for saving some application-specific data. The data needed to be updated on the fly, and the FRAM write speed enabled me to do this task with ease."

What does the future hold for FRAM? From a fundamentally technological standpoint, two of the main suppliers somewhat disagree. Ramtron’s Alwais believes that with a 1T-1C cell, smaller lithography, and minor design and process tweaks, a PZT-based FRAM can achieve 70-nsec read access and 100-nsec read/write cycle times at 5V. Hitachi’s Carbone feels that this level of performance will probably require a more advanced ferroelectric dielectric material. Regardless of how FRAM suppliers accomplish this goal, achieving it will place FRAM in the ballpark of both low-power SRAM and EEPROM.

Beyond raw performance, FRAM’s cell and internal architecture similarity to DRAM beg the question of the improvement potential of a fast-page-mode interface. Carbone views the fast-page-mode-interface as interesting and says that Hitachi is considering the idea for future code-focused products, although he points to a 10% bigger die for this feature. Alwais is more enthusiastic, saying that a PZT-based product provides an example of Ramtron’s differentiated product strategy. The company’s high-speed-DRAM subsidiary, Enhanced Memory Systems, is defining this strategy.

Cycling performance, along with cost, is one of the most fundamental determinants of application viability for FRAM both now and in the future. Each time you write or read—because of automatic postread rewrite—an FRAM location, you cycle it. In comparison, other nonvolatile memories, such as EEPROM and flash, have infinite-read cycles, and battery-backed SRAM provides infinite cycles for both reads and writes. Nonvolatile RAM, according to Paul Ruths, product manager at Simtek, operates uniquely, delivering unlimited reads and writes during normal operation and writing to the nonvolatile EEPROM shadow array only during system power-down. Invariably, other memory vendors all claim high read or write cycling as an important advantage over FRAM.

To decide whether this feature is crucial to your application, FRAM’s unique cycling characteristics require that you closely analyze your system’s memory-access profile. Most of today’s FRAMs have a 10¹⁰ cycle specification. Assuming a 10-year system lifetime, this figure corresponds to an access to the same memory location approximately every 30 msec. At 10¹² cycles, this average-required-delay interval decreases to approximately 300 µsec. When evaluating FRAM, look beyond the time interval for any memory access and focus in on the worst-case number of accesses to the same location in a given time, as increased location cycling degrades only those cells’ dielectric capacitors. Also, factor in variables that could reduce the number of FRAM accesses, such as memory shadowing, caching, or other techniques.

FRAM vendors view their future 10¹⁵ cycle goal as significant, for this figure corresponds to consecutive accesses to the same memory location every 300 nsec or so for 10 years. In their minds, this benchmark exceeds the requirement of even the most stringent code or data-storage and -retrieval applications. However, only your own analysis, given realistic system-usage parameters for your application, can determine when and if FRAM can work for you. Obtain not only your vendor’s product-cycling specifications, but also its failures-in-time, mean-time-between-failures, or defect-per-million predictions at various cycle counts to accurately evaluate FRAM applicability for your system lifetime and reliability goals. It makes no sense to know at which cycle count a device or devices might fail unless you also know the number of devices in a given population that will fail at that time.

Data retention is another area in which other memory vendors currently enjoy an edge over FRAM vendors. Data-retention times for memories such as FRAM, EEPROM, DRAM, and flash memory degrade with increased temperature. All but FRAM, though, provide memories that guarantee 10 years at 70 or 85°C or even higher temperatures. Nonvolatile-RAM data retention is a factor only for information stored in the redundant EEPROM array, and SRAM data retention typically does not vary with temperature. (Remember to consider battery life vs temperature, however.)

Almost all FRAMs specify 10-year data retention but only at 25°C, or room temperature. Above this temperature, data retention depends on the product and the vendor but is at least several years at the upper temperature range. Hitachi claims 10 years at 70°C as an eventual goal for the HM71V832. Data-retention requirements automatically decrease if you periodically rewrite the data. FRAM manufacturers see trading off data retention for cycling as a key means of achieving their future 10¹⁵ cycle target.

FRAMs that operate as low as 2.7V are available. This voltage is higher than that of some alternative memories but sufficient for many system requirements. FRAM vendors see low-power applications, such as cellular phones and pagers, as key to future success and are aggressively pursuing even lower voltage operation. Again, the vendors disagree about whether accomplishing this objective requires fundamental technology changes, internal voltage pumping, both, or neither.

For example, Ramtron believes that cycling capability will inherently improve as the supply voltage decreases. The reason for this improvement is the capacitor dielectric’s lower electric-field stresses. The company believes that the lower voltages complicate memory sense-amplifier design but do not slow write performance.

With a combination of low power and fast writes, FRAM enjoys a write-energy consumption edge over both EEPROM and flash memory, both of which generate higher internal voltages and take longer to program and erase. Power consumption is at least as good as that for SRAM and nonvolatile RAM, and lack of refresh requirements gives FRAM a significant advantage over DRAM in power-conscious applications.

Operating temperature

Ramtron’s FRAMs operate over both the 0 to 70 and –40 to +85°C temperature ranges. Thus, alternative technologies, such as EEPROM and nonvolatile RAM, would better serve extreme-temperature applications, such as automotive and military. The FRAM focus on low-power portable systems will invariably require that vendors continue to offer extended-temperature operation in their future products. Extended-temperature operation is one of the key factors currently gating production qualification of Hitachi’s HM71V832.

With most parallel-interface memories that employ a standard RAM interface (chip select, read and write strobes, address, and data), the sequence of chip select and addresses does not matter; the access begins when the last signal goes valid and stable. For this reason, these memories are relatively tolerant of glitches in chip select and addresses during reads, although such unintended transitions will increase the effective access time. Also, subsequent accesses usually require only address transitions, whereas chip select can remain active and not toggle. Parallel-interface FRAMs do not share these characteristics, however, because the devices have fundamentally "destructive" read characteristics and postread precharge and rewrite.

A read-timing waveform from a parallel-interface FRAM data-sheet example, Hitachi’s HM71V832, shows that addresses must be stable before chip enable’s (CE#’s) active transition (0-nsec setup time) and must remain stable for a 15-nsec hold time after CE# (Figure 3). The FRAM internally latches these addresses and begins the read cycle. Some µPs and microcontrollers may not directly satisfy these hold-time requirements and, therefore, require an external address latch. CE# must toggle inactive and then active before the next access; this requirement complicates external address decoders and some dedicated CPU chip-select outputs. Eliminating spurious CE# activations is key to minimizing FRAM cycling. This consideration is important in external-address decoders and minimal-chip designs that might normally tie the CPU’s address strobe signal to the FRAM CE#, such as the 8051’s ALE#.

Figure 3 also shows the postread precharge and rewrite delay before the next access to either the same or another location. Unless your CPU provides a long delay between external bus cycles or you can guarantee that the CPU will always interleave between accesses to FRAM and either internal registers or other peripheral devices, this characteristic will impact wait-state performance. Fortunately, serial-interface FRAMs seem compatible with their EEPROM counterparts in all areas except, in some cases, maximum operating frequency.

Many FRAMs include EEPROM-compatible multicommand software-write sequences and software-controlled block-lock and -unlock protection. These features, along with glitch-protection circuitry on WE#, effectively protect the FRAM from accidental writes during power transitions but not from runaway code or viruses. FRAM manufacturers still recommend CE# control during system power transitions, as with other nonvolatile and rewritable memories. Some power supplies directly provide a POWERGOOD signal for this purpose, or you can use power-monitoring circuits from companies such as Linear Technology (Milpitas, CA) and Maxim Integrated Products (Sunnyvale, CA).

A final area to consider involves the potential for power loss during FRAM writes or postread rewrite operations. Although the likelihood of data corruption is probably remote, thanks to FRAM’s fast writes and comparatively slow system-voltage ramp-downs, concerned design engineers can incorporate one or several workarounds. These strategies include voltage-monitoring circuits to give system hardware and software early warning of power loss and auxiliary power supplies for memory or system. You can also detect, though probably not correct, data corruption via a checksum stored in the FRAM or elsewhere in the system compared to a calculated checksum of the FRAM contents during system power-up initialization.

Acknowledgments

I’d like to especially thank Drew Jenkins from Dallas Semiconductor; Tony Carbone from Hitachi; David Wilkie from Microchip Technology; Lee Brown, Mike Alwais, and Don Carrigon from Ramtron; Paul Ruths from Simtek; and Mike Watson from Strata Design for their patience and robust assistance as I researched this article.

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