April 10, 1997

VHDL and Verilog fundamentals--expressions, operands, and operators

Douglas J Smith, VeriBest Inc

The data objects in VHDL and Verilog form expression operands. Knowing the operand differences between the two HDLs helps you write more efficient chip-design code.

Expressions consist of operators and operands (Figure 1). Data objects form the operands of an expression, and operators use the operands' values in an expression. VHDL has more operands than does Verilog. Synthesis tools support most VHDL and Verilog operands (Figure 2).

You use expressions with design entities to describe digital logic (Reference 1). You must also understand how to write expressions in the two HDLs to describe chip-circuit behavior.

Operands

Literal operands. A literal is a constant-value operand. You can use only string, enumeration, and numeric literals in synthesizable models. In both VHDL and Verilog, a string literal is a 1-D array of characters enclosed in quotation marks ( " " ). There are two kinds of string literals: character and bit.

Character-string literals are se-quences of characters that are useful for describing test operations in readable text when you design simulatable test harnesses around a synthesizable model. "ABC" is an example of a character-string literal.

Bit-string literals are a special form of string literals in VHDL that you can use to represent binary (B)-, octal (O)-, or hexadecimal (X)-numeric values. You prefix the string with an uppercase or lowercase B, O, or X, depending on the base you are specifying. B"1010'' is an example of a bit-string literal.

Enumeration literals, found only in VHDL, are the individual values of an enumerated data type. An enumerated literal may be an identifier, a character, or a combination of both. The VHDL language predefines enumeration types: bit, Boolean, character, and severity_level.

Numeric literals in VHDL may be integer, real, or physical. You should use integer numeric literals only with synthesis. Integer numeric literals are the values of integer constants that you define in the default base, 10, or any other base from 2 to 16. Underscores may separate digits in the numeric literal without changing its meaning. For example, "16#9F_DE" is a four-digit hexadecimal number.

Numeric literals in Verilog are simple constant numbers that you can specify in binary, octal, decimal, or hexadecimal. Specifying a numeric literal's size is optional, because Verilog calculates size based on the longest operand value in an expression and the corresponding assigned value in an assignment. For example, "4'h#9FDE" is a four-digit hexadecimal number.

Identifier operands. Identifier operands name a data object so that you may easily reference the data object in an HDL model. Identifiers are the most common type of operand. The HDL returns the value of the named object as the operand value.

VHDL identifiers consist of letters, digits, and underscores (_). Verilog identifiers have these representations plus the dollar sign ($). Because VHDL is case-insensitive, it treats uppercase and lowercase identifier names as the same identifier. Verilog is case-sensitive, so it treats uppercase and lowercase identifier names as different identifiers.

Aggregate operands. An aggregate operand (VHDL only) is a set of one or more elements of an array or a record separated by commas and enclosed within parentheses, for example, ('0', '1', A, B). The syntax of an aggregate operand is:

type_name'([choice =>] expression
{, [choice =>, expression}),

where "type_name" is any constrained array or record type, "choice" is optional and used for explicit named notation, and "expression" is the value of the element.

You can consider aggregate operands as array or record operands. Synthesis tools typically support both array and record aggregates. An aggregate also may be the target of a signal or variable in an assignment statement, for example:

(A,B,C)<=unsigned'("101'');

Function-call operands. Function calls, which must reside in an expression, are also operands. The single value returned from a function is the operand value that is used in the expression.

Index- and slice-name operands. An index-name operand specifies a single element of an array. For synthesis, the array may be of type constant, variable, or signal. A slice-name operand is a sequence of elements within an array and is identified in VHDL using to or downto, and in Verilog with a colon (:).

Qualified-expression operands. In VHDL, you use a qualified-expression operand to explicitly state the type or subtype of the operand itself. The operand may be a complete expression in its own right or an aggregate. By using qualified operands, you resolve any possible ambiguities in an operand's type. These ambiguities include the use of an enumerated literal and aggregate whose types you do not know from the context in which they are used in VHDL code. Examples of qualified-expression operands are:

type_name ' (expression)

or

type_name ' aggregate.

Type-conversion operands. Because VHDL is a strongly typed language, you sometimes cannot avoid changing an operand's type within an expression. Type-conversion operands change the type of the returned operand.

The type of the originating expression is implicit. The closely related types that you can convert are abstract numeric types of type integer, which include floating-point numbers but which synthesis does not support. You can also convert particular kinds of array types that have the same dimension index and having each element of the same type. Similarly, you can convert array types that have the same dimension index and having each element that is a closely related property of the array type.

Type-conversion operands usually contain a function call to a type-conversion function; this function call is always the case for models that you synthesize. Type conversions that you use in synthesizable models typically do not infer logic.

Record and record-element operands. In VHDL, you use a record to group objects of the same or different types. A record-type declaration defines the different types that you wish to use in a record. Each element of a record is referred to as a "field." You can use the whole record or an element within the record as an operand in an expression, the syntax of which is shown in the following example. You use the period (.) to separate record names and record-element names when referencing record elements.

record_name (record)

record_name.field_name (record field).

Operators

An operator performs an operation on one or more operands within an expression. An expression combines operands with appropriate operators to produce the desired functional expression.

There are seven functional groups of VHDL operators (Table 1). Operators within a group have the same level of precedence when you use them within an expression. Starting from the top of the table, each group of operators has precedence over the group below it.

Table 2 lists the 10 functional groups of Verilog operators. Although you can't use all operators in the same expression part of code, Table 2 shows the operators in descending order of precedence for cases in which you can use operators in the same expression. Table 2 also shows grouped operators with equal precedence. The third column of Table 2 shows the group to which each operator belongs; these groups do not govern precedence.

Table 3 compares VHDL to Verilog operators. Operators are categorized into functional groups and are not in precedence order. When there is no equivalent operator in the other language, the entry in the table is left blank.

Overloaded operators. VHDL operators for single-bit values operate only on type bit. The language also defines a data type (signal or variable) of type bit to have one of two values: 0 or 1. The only multivalued data types VHDL defines are of type integer. For this reason, VHDL-synthesizable models use overloaded operators from the soon-to-be-standardized IEEE-1076.3 synthesis package, Numeric_STD.

You use type std_logic for single-bit data types, which can have one of nine possible values: U, X, 0, 1, Z, W, L, H, or -. The IEEE library package STD_ Logic_1164 defines data type std_logic, along with the appropriate overloaded language operators.

For multiple-bit data types, you use types unsigned and signed. Both IEEE- 1076.3 synthesis packages, Numeric_bit and Numeric_STD, define these two data types. Numeric_bit defines types unsigned and signed to be 1-D arrays of values of type bit. Numeric_STD defines types unsigned and signed to be 1-D arrays of values of type std_logic.

Arithmetic operators. Of the eight VHDL arithmetic operators, only five are in Verilog (Table 3). The five common operators are addition, subtraction, multiplication, division, and modulus of A divided by B. The VHDL operators not in Verilog are A to the power of B (exponentiation), remainder of A divided by B, and absolute value of A.

Sign operators. Sign operators simply assign a positive (+) or negative (­) sign to a singular operand. You usually do not define a sign operator, in which case the sign is assumed to be "+."

Relational operators. A relational operator compares two operands and returns an indication of whether the compared relationship is true or false. In VHDL, the result depends on the types of operands and is not necessarily type Boolean; the result also depends on the overloading. The relational operator compares enumeration types according to each element's positioned ordering in the enumeration type declaration. Record or array types compare corresponding elements of each operand. In Verilog, the result of a comparison is either 0 (comparison is false) or 1 (comparison is true).

Equality and inequality operators. You use equality and inequality operators in the same way as you use relational operators. They return a true or false indication in the same way as relational operators, depending on whether any two operands are equivalent.

Logical-comparison operators. You use logical-comparison operators with relational and equality operators to perform multiple comparisons within one expression.

Logical bit-wise operators. Logical bit-wise operators take two single- or multiple-bit operands on either side of the operator and return a single-bit result. The only exception is the NOT operator, which negates the single operand that follows it. Verilog does not have the equivalent of a NAND or NOR operator, but you can implement their functions in Verilog by negating the AND and OR operators.

Shift operators. Shift operators require two operands. The operand before the operator contains data to be shifted by the operator, and the operand after the operator contains the number of single-bit shift operations to be performed.

Concatenation and Verilog replication operators. In VHDL, the concatenation operator "&" combines (concatenates) the bits of single- or multiple-bit operands on either side of the operator. The operands must be 1-D. In Verilog, the concatenation operator "{ , }" combines the bits of two or more data objects. These objects may be scalar (single bit) or vectored (multiple bit). You can perform multiple concatenations, called replication, with a constant prefix. VHDL does not support this method of replication.

Reduction operators. Verilog has six reduction operators, but VHDL intrinsically has none. A reduction operator accepts a single-vectored (multiple-bit) operand, performs the appropriate bit-wise reduction on all bits of the operand, and returns a single-bit result. You can do the equivalent of Verilog reduction operators in VHDL by using a loop statement or a function.

Conditional operator. Only Verilog has a conditional operator; it consists of the symbols "?" and ":". An expression using the conditional operator evaluates the logical expression before the "?". If the expression is true, Verilog evaluates the expression before ":" and assigns the result to the output. If the logical expression is false, Verilog evaluates the expression after the colon and assigns the result to the output. The functionally equivalent VHDL model uses the if statement for comparison. For example,

(Time != TimeOut) ? Time + 1 : Zero;

in Verilog.

References

1. Smith, Douglas J, "VHDL and Verilog fundamentals--design entities, data types, and data objects," EDN, Feb 3, 1997, pg 163.

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