April 10, 1997

Digital filter makes simple spike eliminator

Francois Corthay Dr Sc, Engineering School Wallis, Switzerland

As an alternative to counter- and shift-register-based techniques, you can use a digital filter to eliminate spikes from a signal (Figure 1a). This scheme, which feeds the signal into a digital lowpass filter whose output drives a trigger with hysteresis, can filter short pulses and preserve long pulses unchanged except for a time shift. At first, the realization of a digital filter seems to be cumbersome and hardware-greedy. However, using "oversampled digital leapfrog filters" (ODLFs) drastically reduces the hardware (Reference 1).

You can consider the up/down counter in Figure 1a as a differential-input integrator. The rate multiplier codes the bit-parallel output of the up/down counter back into a bit stream. You can find further details about a rate multiplier from the CD4089 data sheet. The working of the filter is similar to that of a first-order RC network, for which the input charges a capacitor and a resistor discharges it with a rate proportional to the capacitor’s charge.

The circuit filters the pulses as follows: When a positive pulse appears, the up/down counter output rises toward its maximal value with an exponential function similar to that of a first-order RC network. When the counter reaches a certain value, the output sets to one. If the pulse is too short, the up/down counter output falls again, and the pulse is ignored.

The length of the rise time is proportional to the power of the number of bits of the counter and to the sampling rate. Usually, the system determines the sampling rate, so the main design parameter is the number of bits in the counter.

One application of this filtering scheme is in a radio-synchronized digital clock. The time information is in the form of pulses, the width of which equates to a zero or a one. The pulses occur every second, except for the last second in the minute. Clearly, the reception and demodulation of an RF pulse stream is subject to noise, which the binary signal contains as spikes. A Xilinx FPGA implemented the digital part of the clock. The quartz oscillator operates at about 2¹⁵ or 33 kHz, and the pulses are about 100 msec for a logic zero and 200 msec for a logic one.

For simplicity, the design uses a first-order ODLF. The trigger with hysteresis provides a logic zero when the two most significant bits of the up/down counter are 00 and a logic one when the two most significant bits reach 11. To eliminate spikes of around 20 msec, the necessary counter length is 20 msecx2¹⁵ Hz=655, which is about what a 9-bit counter can do.

You can design the rate multiplier using a counter and adder. The counter runs indefinitely, and by reversing the order of the bits (most significant bits become least significant bits and vice versa), you obtain a dither pattern (Figure 2). As the counter least significant bit toggles from zero to one at each sample, the dither-pattern most significant bit toggles at each sample, which ensures sustained variation in the pattern. Finally, the carry output of the sum of the bit-parallel input and the dither pattern produces the rate-multiplier output. You don’t use the actual sum but only the carry output.

This realization of the filter requires two 9-bit counters, a 9-bit half-adder, plus some additional logic. In a Xilinx series 4000 FPGA, this circuitry requires 12 configurable logic blocks.

An oscilloscope photo of the spike eliminator shows the effectiveness of the circuit in an especially noisy example (Figure 1b). The delay between an incoming pulse and the filtered output gives the maximal width of the pulses, which the system can eliminate. Adding 1 bit to the counter results in doubling the maximal width of the eliminated pulses.

Reference

1. Corthay, F, "Oversampled digital leapfrog filters," Doctoral thesis, Neuchatel University, 1992.

(DI #2015)

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