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April 24, 1997
Design
tools for analog/mixed-signal ICs
come of age
Jim Lipman, Technical Editor
Fueled by higher operating frequencies and
communication-system requirements, more analog and
analoglike circuitry is appearing on silicon chips. You
need to know what design tools are available to help you
design analog and mixed-signal chips.
So you want
to design a system on a chip? The days of chip designers
dealing only with ones and zeros are rapidly
disappearing. The evolving nature of complex chip design
requires you to learn how to perform mixed
analog/digital-IC design. First, many chips now include
analog circuits along with the chips' digital circuitry.
Second, at clock rates greater than approximately 50 MHz,
digital signals start taking on analog characteristics.
(Looking at the situation another way, all signals are
analog; some just saturate sooner than others.)
There is more
to mixed-signal-chip design than just having an analog or
mixed-signal simulator along with your digital-simulation
tools. Analog-cell performance depends more on physical
layout than does digital-cell performance. Analog
circuits are more sensitive to interconnect coupling and
crosstalk, requiring you to do more circuit matching and
balancing for analog-cell design. If these demands were
not enough, high-speed-chip design may force you to use
some RF-design tools to meet electromagnetic-compliance
(EMC) requirements. Although design tools for analog- and
mixed-signal (A/MS) ICs lag far behind
digital-chip-design tools in capability and ease of use,
a number of EDA vendors have products to help you over
the "analog- design hump."
Top-down
vs bottom-up design
 Analog designers perform chip
designs differently from digital designers. The major
difference is how a designer employs a design
methodology, which must conform to the capabilities of
the EDA tools he uses for the design. If you're a
digital-IC designer, you use a top-down design
approach (Figure 1):
Define
the system architecture and partition it into
subsystem modules;
Specify
each module as an RTL description;
Synthesize
the design to the gate level;
Place
and route the chip;
Verify
the design after layout.
What makes
this methodology work is the availability of Verilog and
VHDL, HDLs that accurately represent a digital system's
behavior, and simulators that predict the behavior of
systems with more than 1 million logic gates.
If you're an
analog designer, you do not have the luxury of a
standardized HDL to represent analog circuitry.
Furthermore, the simulators you use for analog circuits,
for the most part, are limited by the capacity of
components the simulators can handle and by how fast they
can perform simulations. These limiting factors force
most analog designers to design with a bottom-up
design implementation. With this implementation, you
design relatively small analog circuits or cells with as
many as a few hundred or thousand components, separately
verify each designed cell's performance, and combine the
smaller cells into larger analog blocks.
You can
design dense chips only using an HDL-based, top-down
design approach. You need A/MS tools that look more like
the tools you use for digital-chip designs. (See box,
"Analog HDLs.") Using an analog HDL lets
you design at a higher level of abstraction (behavioral
vs device). High-level design makes more efficient use of
your simulation resources and lets you make engineering
trade-off decisions earlier in the design. Fortunately,
some A/MS tool vendors are developing tools that support
an HDL-based design methodology.
Spice and
more--much more
Most analog
designers depend on Spice or a Spice-derived tool for
their circuit simulation. With Spice, you get a high
degree of accuracy but at a price: a relatively low
component limit (a few hundred components per simulation
run) and long runtimes. Some EDA vendors have enhanced
their device-level analog-simulation tools to run
significantly faster than "plain-vanilla" Spice
(Table
1). This
"super-Spice" vendor list includes companies
such as Avanti (through its mergers with Anagram
(Sunnyvale, CA) and Meta-Software (Campbell, CA), Deutsch
Research, Intusoft, and Tanner Research. The speed
increase of some newer device simulators compared with
Spice is impressive. For example, Avanti says that its
Star-ADM simulator can run three orders of magnitude
faster than Spice and has a circuit capacity greater than
1 million transistors.
Some new
device simulators use memory more efficiently than does
Spice, which lets you simulate larger circuits with a
fixed amount of design-platform memory. The Spicelike
simulators in Table 1 have requirements from 100 to 4000
bytes/transistor. You should be careful when comparing
the per-component memory claims of device-simulator
vendors because the memory per transistor necessary
during simulation depends on the type of transistor model
you use. (For more information about analog/digital MOS
models, see Reference 1.) In addition, transient analyses and other
compute-intensive simulations may have platform-memory
requirements that outstrip the memory dedicated for
actual device models. Further complicating this issue is
the fact that some simulators supplement hard memory with
system virtual memory.
For
mixed-signal simulation, some EDA vendors include digital
models along with the Spicelike simulator core. This
capability allows a mixed-signal simulation to run much
faster than if the design's digital and analog portions
were running in an analog-only simulation mode. Examples
of simulators with enhanced mixed-mode are Cad-Migos'
Spice-It! (event-driven, 12-state digital simulation),
Deutsch Research's Dr Spice 2000 A/D (compiled C models
for basic state machines, digital cells, multiplexers,
adders, and RAM), Intusoft's IsSpice4 (compiled C and
behavioral models for digital-logic functions and
memory), and Tanner's T-Spice Pro (external table look-up
for digital models).
Mixing it
up
You get the
most efficient mixed-mode simulation by combining two
simulator operations, one for the digital portion of your
design and one for the analog section. Tool vendors
achieve this near-ideal simulation environment in two
ways: with a single-kernel product that contains both
digital- and analog-simulation capability and by
combining analog and digital simulators on a common
backplane and synchronizing their operation.
ATTSIM, from
Bell Labs Design Automation, has a single-kernel,
mixed-mode simulator. The tool supports a variety of
digital (Verilog and VHDL) and analog (Spice and C-code
behavioral) models at a high level of abstraction. This
capability lets you simulate large circuits in a
reasonable time. A unique feature of ATTSIM is its
partitioning of the analog and digital blocks in a
mixed-signal chip. ATTSIM then independently analyzes and
simulates the analog blocks only when inputs change,
which speeds total chip runtime.
An example of
combining two simulators, one digital and one analog, is
Mixed-Signal Pro from Mentor Graphics. Mixed-Signal Pro
combines QuickHDL with Model Technology's (Beaverton, OR)
VSystem kernel for digital simulation with Anacad's
(Milpitas, CA) Eldo for analog simulation. QuickHDL
accepts both Verilog and VHDL models, and Eldo uses Spice
models and behavioral models with HDL-A, Mentor's analog
HDL.
 You may also get a third-party
simulation backplane and choose from a number of digital
and analog simulators. To cosimulate in this mode, you
use a product such as the SimMatrix simulation backplane
from Precedence. SimMatrix works in a number of EDA-tool
environments and gives you a broad choice of simulators (Figure 2). When you cosimulate on a backplane, there
is some overhead associated with the backplane. However,
precedents indicate that the overhead is small for
analog/digital cosimulation.
Laying out
your design
The
overriding concern for designers placing and routing
digital-chip blocks is delay: how long a signal takes to
go from Point A to Point B. Deep-submicron technology,
with feature sizes at 0.5 µm and below, results in
interconnect delay's dominating these on-chip delay
paths, requiring place-and-route tools to minimize
routing paths. To help designers, many place-and-route
tools are timing-driven, which means that you specify
timing constraints for critical on-chip paths, and the
tool places cells and routes between them to meet these
constraints. With clock rates now measured as high as
hundreds of megahertz, signal-integrity concerns get more
attention from tool vendors and chip designers, but delay
remains the number-one problem.
Layout
requirements for on-chip analog circuitry are more
complicated than they are for high-speed digital cells.
For mixed-signal-chip design, good cell placement and
routing require you to consider additional factors, such
as interconnect resistance, analog-to-analog and
analog-to-digital coupling, heating effects caused by
power dissipation of the analog cell and surrounding
digital blocks, and balanced routing for differential
signals. Automatic routers must be able to use analog
constraints to do their job, along with using digitally
imposed timing constraints.
 Noise coupling is particularly
important because it is more critical for analog than for
digital circuits. For digital blocks, noise is excessive
when it results in a false state-change on the receiving
wire. For analog cells, the level of coupled noise
necessary to upset an analog signal on a line is much
less than it would be to change the state of a 5 or 3.3V
digital signal. Noise-coupling constraints for analog
design force you to change interconnect spacing as wire
length increases. To complicate this design problem, the
level of coupled noise depends on whether the section of
closest wire coupling is nearer the signal-sending cell
or the receiving cell on the transmitting wire (Figure 3).
 A/MS placement and routing combine
designer knowledge and good EDA physical-design tools.
Good cell placement on a mixed-signal chip depends on
your expertise. For example, you should keep sensitive
analog cells away from digital blocks that dissipate
large amounts of power, such as I/O drivers and large
clock drivers. For connecting the analog and digital
blocks, some physical-design tools are available to help
you perform the routing. The Master configuration of IC
Craftsman from Cooper & Chyan performs both
timing-driven and noise-controlled routing. This tool
supports many analog-design features, including
differential-pair routing (Figure 4), net shielding to minimize
crosstalk to a sensitive wire, minimum/maximum
wire-length control, and wire spacing for crosstalk
control. You can also use IC Craftsman to prioritize nets
or even sections of nets that are more sensitive to
noise-coupling problems. The SC layout system from
Silicon Valley Research has Analog Tool Box (ATB), an
analog-simulation capability. ATB uses physical-design
data to calculate capacitance, delay, voltage, and
current with Spicelike accuracy but with reduced
computational times. You use these calculations to guide
your chip's placement and routing to meet
signal-integrity constraints.
System-on-a-chip
design means putting a lot of functionality on that
single piece of silicon. You will probably need to
implement some of your chip's functions with analog
circuitry. The capabilities of design tools for A/MS ICs
currently fall behind those of digital tools,
particularly for front-end design tasks, such as system
specification and partitioning. But have faith: You do
have some good tools available to help you with
extraction, simulation, and physical design of
mixed-signal chips, and suppliers are constantly
developing more and better tools. As for front-end,
mixed-signal, chip-design-tool development, that will
remain at a low level awaiting the release of
standardized A/MS HDLs.
References
Chang,
Yuhua et al, "An investigation on the
robustness, accuracy and simulation performance
of a physics-based deep-submicrometer BSIM model
for analog/digital circuit simulation," 1996
Custom Integrated Circuits Conference
Proceedings, May 5 to 8, 1996, pg 321.
Ogawa,
K, Y Gendai, and E Filseth, "AHDL-based
design for mixed-signal 'system-in-silicon'
ICs," Electronic Engineering Times,
May 13, 1996, pg 66.
Teegarden,
Darrell and H Alan Mantooth, "Modeling and
simulation using an AHDL," Analogy white
paper, Beaverton, OR.
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Analog
HDLs
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Using Verilog and VHDL for
digital-chip design is widespread and
well-established, with standardized versions of
both HDLs available. Designing with a top-down
design methodology is necessary for
high-complexity, mixed-signal chips, such as
those in communication and multimedia systems.
The problem is that no standardized
analog/mixed-signal (A/MS) HDL exists to support
language-based, top-down design.
Both
Verilog and VHDL have committees defining analog
extensions to these HDLs, which do a good job of
supporting digital design. Open Verilog
International (OVI) (Los Gatos, CA), which
comprises Verilog users, EDA and ASIC vendors,
and universities, is an independent organization
that supports and promotes using Verilog for
top-down design. OVI helped form an IEEE study
group for Verilog-AMS (Verilog with analog and
mixed-signal extensions) in September 1996.
Current plans are to start an IEEE working group
for Verilog-AMS in July and to make the language
an IEEE standard in 1998. An IEEE Working Group
is reviewing VHDL-AMS (VHDL with analog- and
mixed-signal extensions) as Specification 1076.1.
You can find information about the VHDL-AMS
effort on the Web at www.vhdl.org/vi/analog/wwwpages.
Some
EDA-tool vendors have proprietary analog HDLs for
their products. This list includes Analogy's MAST
(Saber), Cadence's Spectre-HDL (Spectre),
Mentor's HDL-A, similar to the evolving VHDL-AMS
(Mixed-Signal Pro), and VeriBest's Diablo
(VeriBest Analog). The use of proprietary analog
HDLs is only a stopgap until the
electronics-design community creates standardized
A/MS HDLs. A proprietary HDL usually works only
with the simulation tools from the company that
created the HDL. Models created in a proprietary
HDL are not universal; you can't create a model
and export it to other simulation environments.
There are a few exceptions, however; some EDA
companies permit proprietary-HDL models to run in
their simulators.
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RF-chip-design tools
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Although most people do not consider
RF-design tools within the realm of traditional
analog design, some EDA tools that can
significantly speed the RF portion of your
mixed-signal designs are available. Two
noteworthy tools for analyzing modulated-RF
waveforms are HP-EEsof's Circuit Envelope and
Cadence's SpectreRF. Both of these products
address a major problem you encounter using Spice
for modulated-carrier simulation: slow runtimes.
Spice,
a time-domain simulator, uses a time step for the
highest frequency component in the signal, the
carrier frequency, and probably some of the
carrier's harmonics. The time needed to
adequately simulate the modulated carrier is thus
excessive. Another drawback of Spice is that it
cannot handle the frequency-domain models that
you often use in high-frequency circuit analysis.
You can use harmonic balance, a frequency-domain
analysis, for analyzing modulated RF carriers.
The problem with harmonic balance is that it is
best suited for steady-state systems. Many
digital-communication systems use digital
modulation. Harmonic balance models digitally
modulated waveforms as a sum of Fourier harmonics
to represent the modulated signal. This method
requires long runtimes (although not as long as
Spice) and large amounts of memory.
Circuit
Envelope handles a signal's amplitude and
phase-modulation information in the time domain
and handles the RF carrier and its harmonics in
the frequency domain. Unlike with Spice, with
Circuit Envelope you can output a signal's
instantaneous amplitude and phase information,
which is useful for analyses such as ringing
severity when you vary an oscillator's frequency.
In addition, whereas Spice relies on
lumped-element approximations, Circuit Envelope
can also include frequency-domain models, such as
s-parameter data, for more accurate simulations.
 SpectreRF is a tool module
for RF design that you use along with other
Spectre simulation tools for device-level and
analog-HDL design. SpectreRF uses
"shooting-Newton methods" to analyze
linear and nonlinear circuits without having to
run simulations for thousands of signal cycles.
The tool handles strongly nonlinear circuits
containing as many as 1000 transistors and
produces modulated RF simulation orders of
magnitude faster than does Spice (Figure A).
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Looking ahead
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Stop! Don't touch that silicon just
yet. Before you start your detailed
mixed-signal-chip design, you should define the
characteristics you need for each block on the
chip. How many taps does my filter require? What
should the gain of this output stage be? How much
noise can this converter tolerate? You can
address these kinds of questions only in the
early stages of your system design, during system
specification and partitioning.
Companies
offer EDA tools to help you during the critical,
system-definition phase of your design. These
companies include Alta Group (Sunnyvale, CA),
with tools for multimedia, networking, and
communication-system design; i-Logix (Andover,
MA), which has Statemate Magnum for graphically
specifying and analyzing a complex system and
generating hardware and software code from the
verified specification; and Hyperception
(Dallas), focusing on DSP-block design. Use these
kinds of high-level specification, analysis, and
verification tools to decide what your A/MS
blocks should look like before you waste time
designing a block that meets the wrong
specifications.
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