April 24, 1997

V/F converter draws fleapower

W Stephen Woodward, University of North Carolina, Chapel Hill, NC

The V/F converter in Figure 1 is unique because it draws less than 30 µA from one unregulated supply while converting bipolar input voltages. It produces three CMOS-compatible, 0- to 10-kHz outputs: one (F+) that becomes active when the input voltage is positive, another (F­) that takes over for negative inputs, and a third (F_ABS) that produces a frequency proportional to the absolute value of the input. Linearity is better than 0.1%, and the full-scale span and offset drift are typically less than 100 ppm/ºC and 2 µV/ºC, respectively.

The circuit's core comprises CMOS switch IC₂ and the NP0-dielectric (less than 50 ppm/ºC) reference capacitor, C₁, which combine to form a classic charge pump. When IC₂'s Address pins 8 and 9 are both at logic zero, the top end of C₁ connects to V_REF; the bottom end, to ground. C₁ thus charges to the 1.2V reference voltage that IC₂ produces. When C₁ subsequently discharges into the current-summation node at the junction of C₂, R₁, and R₂, C₁ deposits 1.2·C₁=264 pC of charge on the node. The magnitude of the average current into C₂ is thus (264 pC)F, where F is the frequency of the charge-discharge cycles. Integrator IC₁ accumulates any difference between the average current and the converter's input current (V_IN/R₁). Therefore, for V_IN>0V, IC₁ tends to ramp down and, for V_IN<0V, to ramp up.

When IC₁ ramps to a point greater than approximately 1.25V, the multivibrator that IC_4A and IC_3A form triggers and produces F­ pulses. If IC₁ ramps to a voltage less than than approximately 1.15V, IC_4B and IC_3B wake up and produce pulses on F+. Both F­ and F+ pulses trigger C₁'s charge-discharge cycles. The trick that makes bipolar conversions possible hinges on which Address pin in IC₂ is pulsed to trigger C₁'s discharge. If F­ pulses on Pin 9 trigger the discharge, the multiplexer selects State 1. This state connects the positive end of C₁ to C₂ via R₄ and connects the negative end to ground. The result is to deposit 265 pC of charge onto C₂ and drive IC₁'s output negative. F+ pulses, by contrast, drive IC₁ to State 2, which grounds the positive end of C₁ via R₅ and connects the negative end to C₂. This action deposits ­265 pC on C₂ and drives IC₁'s output positive. State 1 balances the circuit with V_IN<0V; state 2 with V_IN>0V. Thus, the circuit handles both input polarities.

R₁ sets the conversion gain according to the relationship F=(V_IN/R₁)(265×10^­12) Hz/V. The supply voltage can range from 3 to 16V with virtually no effect on accuracy. Current consumption, however, does increase directly with the supply voltage. The consumption ranges from approximately 20 µA for a 3V supply to 100 µA for a 16V supply. A 5V supply typically results in 30-µA draw. For negative inputs, stray capacitance at the positive end of C₁ tends to reduce conversion gain by a few percent. You therefore make R₄ large enough that the 30-µsec F­ pulses leave a little residual charge on C₁, thereby equalizing the ± scale factors. (DI #2013)

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