April 24, 1997

WHAT'S HOT IN THE DESIGN COMMUNITY

Edited By Fran Granville

Charger IC guards against raging ions

It's a challenge to fully charge two-cell lithium-ion battery packs while guarding against likely fault conditions: overcharge, excessive discharge, reverse charge, open center-tap, and short circuits. By monitoring each cell's voltage to within 50 mV, the Si9730 from Temic oversees charging and discharging to keep the cells at maximum capacity without exposure to potentially hazardous charge levels and rates. The SO-8 device contains drivers for external N-channel MOSFETs used as current switches.

If the Si9730 detects an overcharge in either cell, it bleeds current from that cell at 15 µA until the cell voltages are equal and then returns to charging mode. Similarly, the IC invokes appropriate tactics for other undesirable conditions; for example, if it detects an excessive overcharge, the IC isolates the battery fromthe load while drawing less than 1 µA from the battery pack itself. During normal operation, when the batteries approach full charge, the Si9730 continues to charge but with rest breaks during which each cell voltage can stabilize and let you accurately measure it. You can use two of the $6 (1000) devices to handle four-cell packs.

--by Bill Schweber

Temic Semiconductors, Santa Clara, CA. 1-408-567-8220, ext 37, www.temic.com.

Quantum µP takes a leap

Quantum Effect Design (QED) has leveraged the MIPS R5000 architecture to develop two MIPS µPs targeting the high-end embedded market. The RM5230 and RM5260 are derivatives of the 64-bit R5000 and, therefore, implement the MIPS IV instruction-set architecture (ISA). QED also expanded the MIPS IV ISA by adding multiply/add and three-operand multiply instructions.

Like the R5000, the RM5230 and RM5260 feature a superscalar architecture. The µPs have five-stage integer and eight-stage floating-point pipelines that allow the µPs to perform one integer and one floating-point instruction per clock cycle. A two-way, set-associative, 16-kbyte instruction cache and 16-kbyte data cache feed the pipelines. The data cache supports both write-back and write-through operations. The µPs manage memory using a R4600/R5000-compatible memory-management unit with a 48-entry translation look-aside buffer.

The RM5230 has a 32-bit memory interface, comes in a 128-pin PQ-4 package, and runs at 100 and 133 MHz. The device consumes only 2.5W typical at 3.3V and 133 MHz. The 100-MHz version costs $35 (10,000). For higher performance, the RM5260 has a 64-bit memory interface, comes in a 208-pin PQ-4 package, and is available in 133- and 150-MHz versions. Typical power consumption for the RM5260 is 2.8W at 3.3V and 150 MHz. The 133-MHz version costs $75 (10,000).

Algorithmics Ltd (London) provides a tool package, including a compiler, an assembler, a linker, and a debugger. Galileo Technology (San Jose, CA) offers an RM5260 evaluation board.

--by Markus Levy

Quantum Effect Design, Santa Clara, CA. 1-408-565-0300, www.qedinc.com.

Full-duplex ATM chip operates at 622 Mbps

At 622 Mbps, asynchronous transfer mode (ATM) offers the fastest available full-service standard interface. However, chips are scarce that are flexible enough to keep up with evolving specifications and provide high performance. Hitachi says it has the chip set with performance and flexibility with its hybrid approach in the NewPort 622-Mbps ATM chip set. The SH-3 RISC processor and the NewPort Accelerator chip work together for full-duplex cell or data-packet transmission and reception.

The chip set employs the NewPort accelerator for segmentation and reasembly, flow control, and traffic shaping. The SH-3 RISC processor controls resource-management cells and buffer management. Together, they support multiprotocol over ATM (MPOA) and LAN emulation. Relying on the high-volume SuperH processor gives the chip set a road map for future performance increases. The NewPort Accelerator has a 64-bit PCI interface, Utopia 1 and 2 interfaces for multiple physical-layer connections, and a standard interface for low-cost memory.

The NewPort chip set will be available for sampling in July. The chip set, including a hardware accelerator and the SH-3, costs $175 (10,000).

--by Stephen Kempainen

Hitachi, Brisbane, CA. 1-800-285-1601, ext 11, fax 1-303-297-0447, www.hitachi.com.

Tool makes VHDL-based programmable-logic design "easy"

At $495, Minc's VHDL Easy logic-synthesis tool provides a low-cost way to get into language-based FPGA and complex-PLD design. The tool provides automatic finite-state-machine extraction from VHDL source code, resource sharing to minimize required logic, device-specific optimization, and netlist generation. It supports many logic families from Actel (Sunnyvale, CA), Altera (San Jose, CA), AMD/Vantis (Sunnyvale, CA), Lattice (Hillsboro, OR), and Xilinx (San Jose, CA).

The price includes a choice of one target-device family, a complete VHDL tutorial, and Web/e-mail support. Each additional target family costs $495, as does telephone technical support for one year.

--by Jim Lipman

Minc, Colorado Springs, CO. 1-719-590-1155, fax 1-719-590-7330, www.minc.com.

Synchronous+dual port=simpler, faster designs

Synchronous memories deliver measurable benefits in performance (thanks to internal interleaving and pipelining) and design simplicity (by integrating registers and address counters) over their asynchronous counterparts. Dual-port memories find use when two hosts, such as two DSPs or a local processor and a global interface bus, need to simultaneously read and write to different locations, often at different speeds. Combine the two, as Integrated Device Technology (IDT) does with its 709xxx series, and you have specialized SRAMs that are well-suited to today's high-performance networking, telecomm, graphics, and multimedia applications.

Available in a range of densities and configurations (Table 1), these memories all operate at 5V V_CC, and IDT plans 3.3V versions for the end of the second quarter. IDT provides both 5-mW typical and 1-mW typical standby-power versions. Users can configure one or two pipelined mode ports for 709xx9 devices, which can deliver performance as fast as 40 MHz with 12-nsec clock-to-data output, and flow-through mode for both 709xx and 709xx9 memories supports performance as fast as 33 MHz with a 25-nsec clock-to-data output.

The 5-nsec setup and 1-nsec hold times on all input signals and the internal full-range address counter and separate upper/lower byte control on ×16 versions make the devices suitable for interfacing to processors, DSPs, ASICs and other synchronous buses. IDT supplies all devices in 100-pin TQFPs and in both commercial- and extended-temperature versions. The 70927 and 709279 also provide a 108-pin PGA option, and the 70908 and 709089 also come in 84-pin PGAs. Samples of the 70927 and 709279 are now available, and IDT plans production versions, along with samples of lower density and ×8 versions, to be available this summer.

In selecting between pipelined and flow-through versions, decide whether sustained bandwidth or initial access latency is more important in your application. Flow-through interfaces also enable the fastest transition from read to write on a given port. Synchronous memories are generally more useful for long sequences of reads and writes to consecutive addresses, not short, random data bursts. One additional caveat: Unlike traditional asynchronous dual-port RAMs, IDT's synchronous memories provide no mechanism for preventing simultaneous reads and writes or dual-port writes of the same memory location. As many as three versions of the same data--one in each port register and the third in the SRAM array--could exist simultaneously in the device. IDT's designers took this approach because they believe that providing comparison and hold-off capability to resolve access conflicts would negatively impact performance. The company also indicates that the potential for invalid data was not a concern to beta-site customers and that external components, such as hardware-controlled address-range lockout, clock skewing between ports, and protected-mode software configuration, could address the problem. For other applicable techniques, see "Ping-Pong scheme uses semaphores to pass dual-port-memory privileges" (EDN, June 6, 1996, pg 179).

--by Brian Dipert

Integrated Device Technology Inc, Santa Clara, CA. 1-408-727-6116, fax 1-408-492-8674, www.idt.com.

IC collapses speakerphone to one device

You can build a speakerphone using the Motorola MC33215 IC, dual-tone multiple-frequency (DTMF) dialer and ringer ICs, plus some passive components. To minimize feedback and howling, this telephone-line interface and speaker IC includes a half-duplex controller that monitors both transmit and receiver channels and reduces the gain by 40 to 52 dB (set by the phone designer) in the channel with the lower gain. The phone-line-powered IC, in a 42-pin DIP or 52-pin QFP, requires 4-mA line current and lets you use approximately 90% of the loop current for the internal speaker amplifier.

The IC lets you select ac- and dc-parameter operating points, such as set impedance, as well as switching depth from one mode to the other. It includes separate supplies for the handset and base microphones, and you can power and use the loudspeaker amplifier separately from the rest of the phone. Internal circuitry manages a smooth switchover from handset to speakerphone operation, as well as including ac- and dc-line termination, two- to four-wire conversion, and line-length automatic gain control. The IC costs $2.55 (10,000).

--by Bill Schweber

Motorola Semiconductor Products Sector, Phoenix, AZ. 1-602-413-3615, www.mot.com/sps.

Flash device targets mixed code and data storage

Intel's new Smart 3 boot-block architecture follows the trend for memory manufacturers to integrate code- and data-storage within one flash device. Examples of that trend include Atmel's (San Jose, CA) ConcurrentFlash and Sharp's (Camas, WA) Dual Works. Thanks to flash's single-transistor cell structure, flash memory is significantly cheaper than either EEPROM or SRAM. This fact is especially true when you compare, for example, a 64-kbyte EEPROM with a 64-kbyte block of a 1-Mbyte flash memory.

Intel made some inexpensive silicon tweaks to its previous boot-block flash memories to combat the fact that flash is not fully byte-alterable, that block erases take longer than EEPROM or SRAM writes, and that it's difficult to simultaneously alter data in the same device from which you're reading. To correct these problems, Intel uses slightly faster program and erase times; a greater number of small data blocks for end-system flexibility; more suspend modes; and quicker, more predictable suspend times.

Intel also leverages its flash-file-system experience to develop Flash Data Integrator (FDI) software. FDI consumes less than 16 kbytes of flash code and only 2 kbytes of RAM. Written in portable C and available in source code, the software provides an EEPROMlike, foreground application-programming interface that executes primarily in RAM and isolates the system from the flash-memory command set. The foreground manager also detects system code-fetch requests and suspends flash writes and erases to service the interrupts. The background manager translates foreground read, write, close, and delete requests to flash-memory algorithms and handles media reclaim. Finally, the boot manager initializes data structures on system start-up and provides any necessary data recovery due to previous power loss during write. FDI also uses part of the 2-kbyte system SRAM to remap the interrupt-vector table and queue data before writing it to flash memory.

Smart 3 also features reads and writes as low as 2.7V V_CC with a fast 12V write option and ×16 output-buffer operation as low as 1.8V for easier system interfacing and lower power consumption. Packaging alternatives include both 48-lead TSOP and 48-bump BGA, and densities range from 4 to 16 Mbits in both bottom and top-boot options. The 120-nsec access time is valid across all operating voltages and the extended temperature range. Price of a 16-Mbit version (sampling now) is $20.50 (10,000), and production begins in August. Price of an 8-Mbit version (sampling in July) is $10.30 (10,000), and production begins in September. The 4-Mbit version will be available at year-end. A free developer's kit is also sampling. Micron Technology (Boise, ID) plans to second-source the Smart 3 boot-block family.

--by Brian Dipert

Intel Corp, Folsom, CA. 1-916-356-8080, fax 1-916-356-2803, www.intel.com.

New kid arrives on logic-synthesis block

Say "hello" to Ambit and its new wonderfully named logic-synthesis tool, BuildGates. You use the tool to synthesize gate-level representations from digital-circuit RTL descriptions. Aimed at synthesis of modules with more than 100,000 gates, BuildGates contains a new static-timing-analysis engine, automatic time budgeting, and a technology mapper.

BuildGates addresses the limitation of other synthesis tools, which limit logic-block synthesis to a few thousand or fewer gates. When signals cross module boundaries, you must generate a cross-boundary timing "budget" to guide the synthesis tool. For large designs with many separately synthesized modules, the timing budget becomes complex, particularly for deep-submicron designs in which even tens of nanoseconds are critical. BuildGates bases its pin-based timing analysis on the tool's storage of timing information at every pin in the module under synthesis. The tool stores both driving- and receiving-pin timing information for each net, accounting for connecting-wire delay. When you resize gates during synthesis, BuildGates updates the timing information only for those pins directly affected by the resized gates. This technique is more efficient than the path-based timing algorithm that traditional timing-analysis tools use, which recalculates an entire signal path for a gate-structure change at any point in the path.

Time budgeting, distributing available timing slack among combinatorial logic in a signal path, is traditionally a manual operation when synthesizing logic. BuildGates automates time budgeting, saving much of a designer's design time. The tool also uses algorithm-based technology mapping. This feature eliminates rule sets and lets BuildGates map bigger cells, without special synthesis switches, producing better timing results.

Ambit claims that BuildGates will halve synthesis time, improve by 10% the timing of the synthesized circuits, and let you synthesize blocks five to seven times larger than possible with current synthesis tools. BuildGates is available now on Unix platforms at a starting price of $85,000.

--by Jim Lipman

Ambit Design Systems, Santa Clara, CA. 1-408-566-8000, fax 1-408-566-8001.

622-Mbps ATM chip boasts programmable SAR and ABR

Breaking with the tradition of segmentation-and-reassembly (SAR) functions in hard-wired circuits, Maker Communications introduces a programmable architecture for cell processing. The CellMaker-622 processor and firmware perform asynchronous-transfer-mode (ATM) Adaptation Layer 5 (AAL5) SAR functions at the full line rate for 622-Mbps (OC-12) links. It supports multiple classes of service, including available bit rate (ABR) and constant, unspecified, and variable bit rates. The programmable architecture accommodates changes in evolving ATM standards by upgrades through firmware. ATM access, routing, and integrated services for LANs or wide-area networks use CellMaker for connecting to OC-12 or OC-3 links.

CellMaker-622 combines the MXT3010 processing engine chip and Softwire-622 ATM AAL5 SAR and scheduling firmware, which adapts to all AAL layers. Two MXT3010s each operate in unidirectional mode for OC-12 and quad OC-3 applications. A single MXT-3010 operates in bidirectional mode for a single OC-3 connection. The MXT3010 comes in a 240-pin PQFP.

Based on Maker's custom RISC processing core, the CellMaker-622 performs SAR at full line rates independent of packet size. The specialized cell-processing instruction set enables the high-speed software SAR. The CellMaker-622 also performs cell scheduling based on a proprietary Maker technology. This scheduling dynamically allocates per-connection bandwidth and supports more than 15,000 virtual connections. CellMaker-622 costs $225 (10,000).

--by Stephen Kempainen

Maker Communications, Wal-tham, MA. 1-617-672-0622, fax 1-617-672-0256, www.maker.com.

FC-AL adapter boosts data rates

Symbios Logic combines the FC-AL interface and the emerging industry-standard I₂O architecture in a new PCI-bus host adapter. The SYM40940 allows system designers to harness the 100-Mbyte/sec peak data rates that FC-AL disk drives afford. At the same time, I₂O offloads the host CPU of I/O overhead via the use of an Intel i960 µP dedicated to the storage subsystem. Moreover, I₂O simplifies driver development. The SYM40940 will be available in the third quarter for $850 (large quantities).

--by Maury Wright

Symbios Logic, Fort Collins, CO. 1-970-223-5100.

Big DRAMs come on little chips

Toshiba America is upping the on-chip-memory ante for its ASIC technology. The company is announcing a 128-Mbit embedded DRAM for its 0.25-m m chip process. Large-DRAM capability on ASICs doesn't appear to be much in demand now but should see more applications as chip density continues to increase. Available DRAMs, organized as ×64-, ×128-, ×256-, ×512-, and ×1024-word-wide blocks, range from 1 to 128 Mbits. The DRAM is fully diffused and manufactured in Toshiba's ASIC process using a trench technology. The trench process produces a higher capacitance than does the stacked capacitor technology of other processes. The higher capacitance reduces potential soft errors, because the capacitance takes more charge to switch the logic state of a memory bit.

Toshiba will begin design starts of its 0.25-µm ASICs by midyear. The company projects fabricated chips to have more than 3.2 million usable gates, gate delays of 120 psec, and power dissipation of 0.65 µW/gate/MHz.

--by Jim Lipman

Toshiba America, Irvine, CA. 1-800-879-4963, fax 1-408-456-8910, www.toshiba.com/taec.

CD-ROM summarizes storage-interface activity

System designers trying to stay abreast of constant activity in storage-interface standards can now turn to the CD-Access subscription service from ENDL. Subscribers get a new CD-ROM every two months with all of the activity and interim standard work of the ANSI X3 SCSI, Fibre Channel, SSA (Serial Storage Architecture), and other working groups, as well as the activities of the ad hoc SFF (Small Form Factor) Committee. You access the CD-ROM using your favorite Web browser. All subscribers must pay a one-time $1500 corporate fee. The corporate fee allows an organization to buy a $360/year individual subscription or a site license for intranet usage of the material. For example, a corporation would pay $2160 plus the one-time $1500 fee to put the material on an intranet for 60 users.--by Maury Wright

ENDL, Saratoga, CA. 1-408-867-6630.

CALENDAR

May 5 to 8

Custom IC Conference, Santa Clara, CA, includes educational sessions on IC design, wireless-IC design, and interconnect and Spice modeling. On-site registration for the conference and educational sessions costs $590 for members and $640 for nonmembers. Custom IC Conference, Gaithersburg, MD. 1-301-527-0902.

May 5 to 9

NetWorld and Interop '97, Las Vegas, offers introductory sessions on WANs, LANs, and wireless technologies. Admission to the general conference, an intranet conference, two tutorials, and one workshop costs $2495; the three-day general conference costs $1195. NetWorld and Interop, 1-415-372-7090.

May 6 to 8

The Electronics Industries Forum of New England, Boston--formerly, Electro--offers five audience-targeted summits on technology. The event features more than 400 electronics manufacturers and more than 35 educational programs. Summit Exhibition Management, Norwalk, CT. 1-203-855-3000.

May 13 to 15

EDS '97, Las Vegas, hosts more than 425 exhibitors and offers keynote addresses on the globalization of distribution and the future of cyberspace. EDS Corp, Chicago, IL. 1-312-648-1140.

SRAM substitutes: not quite cloning--but close

New memory architectures from MoSys and Motorola emulate portions of their full-featured alternatives while delivering additional benefits. MoSys has expanded its MCache line to include the lower power MC80232K64, a 32k×64-bit device for use in level-two caches and other high-speed, pipelined-burst SRAM (PBSRAM) applications. MoSys implemented this Mobile MCache memory using multibank DRAM technology, which offers smaller dice and packages and lower cost and active power consumption than does PBSRAM.

Operating at 3.3V V_CC and available in 66 and 75 MHz, the MC-80232K64 delivers 3-1-1-1 burst read and write performance with 60-mA active current draw. The memory internally controls refresh operations, and its sleep mode lowers current draw to a maximum of 1 mA. Pinouts in the 128-lead QFP match those of a PBSRAM with three exceptions: MCache includes a host-bus read/write signal and two function-control pins. Jumper configuration on the system board enables widespread chip-set support and interchangeable use of either Mobile MCache or PBSRAM. Price is $6.50 (1000).

With the MCM69C232 and MCM69C432, Motorola enters the content-addressable-memory (CAM) market. CAM, a variation of synchronous RAM, reverses the traditional concept of memory.

Instead of providing an address and getting data in response, you provide a CAM with data, including specifying don't-care bits, and the CAM tells you the address or addresses of matching locations. You can cascade multiple memories for depth expansion, and the CAM can also supply additional associated data after a match.

CAMs commonly find use as address-look-up and address-translation tables in data-communication systems, such as routers and asynchronous-transfer-mode switches. Motorola refers to its memories as "pseudo-CAMs" and implements them using low-cost, four-transistor, two-resistor (4T-2R) cell structures. Many full-featured CAMs, on the other hand, use a nine-transistor approach. The devices also feature 3.3V operation; a 50-MHz maximum clock frequency; and 160- and 180-nsec match times for the MCM-69C232 and MCM69C432, respectively. Motorola also removed portions of the traditional CAM feature set, such as multiple mask registers, dynamic mask reconfiguration, and separate associated data and address outputs. Motorola's devices target applications requiring low cost but lacking the need for complex matching algorithms, frequent updates of CAM or mask-register contents, and very high-speed matches.

The MCM69C232, a 4k×64-bit device in a 100-pin TQFP, is available for sampling now, and production will begin in May. It will cost $20 (1000). The 32k×64-bit MCM-69C432, also in a 100-pin TQFP, will be available for sampling in July, and production will begin in August. Price will be less than $50 (1000).

--by Brian Dipert

MoSys Inc, Sunnyvale, CA. 1-408-731-1800, fax 1-408-731-1893, www.m2i.com/mosys.html.

Motorola Corp, Austin, TX. 1-512-933-7726, fax 1-512-933-6809 www.mot.com/FastSRAMs.

Quad-port RS-485/442 card eliminates driver concerns

The Ultra-comm+422 ISA card from Sealevel Systems allows designers to add four RS-485/422 ports to any DOS, Windows 3/x/95/NT, or OS/2 system with no special driver software. User-selectable interrupt-request and I/O-address selections allow the ports to mimic standard COM ports, thereby leveraging serial-port support built into stand operating systems and applications. Meanwhile, the RS-485 capability allows each port to connect with as many as 32 external devices using a multidrop cable. Compliance with the RS-422 standard ensures noise-free communications over cables as long as 4000 ft. The card supports host data rates as high as 460.8 kbps and includes 16550 UARTs or optional 16650 UARTs with 32-byte FIFO buffers. Available now, the Ultra-comm+422 costs $399.

--by Maury Wright

Sealevel Systems Inc, Liberty, SC. 1-864-843-4343.

Windows CE proliferates at ESC

If any consistent message emerged at the Embedded Systems Conference (ESC) show in Boston this March, it was that Windows CE is spreading rapidly. Portings, extensions, tools, and distribution agreements all appeared at the show, adding to the substantial support the operating system garnered at its introduction last September. The latest processor to join the fold is AMD's Elan SC400 microcontroller.

Three companies announced Windows CE-distribution agreements. Annasoft Systems can now license Windows CE in any quantity, allowing developers to prototype designs without committing to a large license purchase. Annasoft offers an OEM adaptation kit to customers that purchase at least 1000 licenses, however, so that developers can adapt Windows CE to their custom platforms. Eclipse International and VentureCom also offer Windows CE licenses. VentureCom plans to go further, however, and develop modifications that will bring deterministic behavior to Windows CE.

Phoenix Technologies has also created enhancements to Windows CE. The enhancements include a software-abstraction layer to provide a consistent interface for the operating system, an IrDA communications stack, and a flash-memory interface. Phoenix has also developed a tool set for software development under Windows CE. The PicoScope tool set runs under Windows NT and communicates to the target through a debugging engine.

--by Richard A Quinnell

AMD, Sunnyvale, CA. 1-408-732-2400, www.amd.com.

Annasoft Systems, San Diego, CA. 1-619-674-6155, fax 1-619- 673-1432, www.annasoft.com.

Eclipse International, Mountain View, CA. 1-415-969-4175, fax 1-415-428-0292, www.EclipseInt.com.

Phoenix Technologies, San Jose, CA. 1-408-570-1000, fax 1-408- 570-1001, www.phoenix.com.

VentureCom, Cambridge, MA. 1-617-661-1230, fax 1-617-577-1607, www.vci.com.

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