May 22, 1997

Micropower ADC has eight differential channels

Kevin Hoskins, Linear Technology, Milpitas, CA

If you need a 12-bit ADC with eight differential channels for a portable, battery-powered data-acquisition system, you'll find that many 12-bit ADCs with configurable multiplexers are available. However, they all suffer from as much as 50% channel reduction when you require differential inputs. The circuit in Figure 1 overcomes the channel-reduction problem. It provides eight differential-channel, 12-bit A/D conversion. The circuit uses a low-power, 12-bit, eight-channel ADC and a low-power, eight-channel multiplexer. The system communicates with a host processor over a serial connection.

The circuit offers considerable flexibility. You can use two methods to select inputs that form differential pairs. Moreover, the system performs continuous conversions on a selected input pair without requiring configuration data before each conversion, and the system offers an external analog-signal-processing loop. Figure 1 shows two ways to send channel-selection data to the internal and external multiplexers.

The host processor sends the same data to the external multiplexer and to the ADC's internal multiplexer when Connection 1 is closed and Connection 2 is open. This configuration always pairs the same channels with their signals. Closing Connection 2 and opening Connection 1 increase flexibility by allowing you to select different channels on each multiplexer. This operation permits combining any channel on the external multiplexer with any channel on the ADC's internal multiplexer. For example, you could combine a single external multiplexer channel with each ADC multiplexer channel or the ADC's multiplexer channels 4, 6, or 1 with external multiplexer channels 2, 5, or 7, respectively.

Some serially interfaced, multiplexed ADCs must receive channel-selection data each time you need a conversion, even if the channel selection remains constant with successive conversions. This requirement creates unnecessary software overhead and limits the maximum throughput. The circuit in Figure 1 uses an ADC that overcomes the limitation by generating conversions on the same differential channel pair without receiving channel-selection data for each conversion request. This benefit simply requires generating separate CS_ADC and CS_MUX signals for IC₂, pins 10 and 6, respectively. Once you select the desired channel pair, consecutive conversions and associated clocking occur while CS_ADC is low. In this operating mode, the maximum throughput is 21.3k samples/sec. The maximum throughput is 16.8k samples/sec when you change channels for each conversion.

The ADC in this application performs unipolar conversions and provides no sign bit. The signal applied to the COM pin must have a magnitude lower than that of the signal you apply to a selected ADC multiplexer channel. The ADC's output code is zero if the voltage applied to COM exceeds the voltage on a selected ADC multiplexer channel. (DI #2023)

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