May 22, 1997

Counter provides divide-by-4.5 function

Alex Sumarsono, Baynetworks Inc, San Jose, CA

It's common practice to use a divide-by-N circuit to create a free-running clock based on another clock source. Designing such a circuit where N is a noninteger is not as difficult as you might think. Listing 1 gives the synthesizable VHDL code to configure a divide-by-4.5 circuit. Figure 1 shows the simulation result for a 50-MHz input clock and a 11.11-MHz output. You can apply the concept given here for any N, where N is 1.5, 2.5, 3.5.... First, consider what divide-by-4.5 is. It simply means that, for every nine clocks, you need to generate two symmetrical pulses. You can easily design such a circuit by using a 9-bit shift register initialized to 000000001 upon reset and then taking the first shift-register output bit and the fifth output bit shifted by half a clock period.

If you're not concerned with the duty cycle of the output waveform, then your job is done. If you need to correct the duty cycle, you need to do a little more work. To generate the first pulse, you must shift the first bit by half a clock period and then OR it with the first and second bit. To generate the second pulse, you need to shift the fifth and sixth bits by half a clock period and then OR these bits with the original sixth bit. All this shifting is necessary to ensure a glitch-free output waveform. Click here to download the file from DI-SIG, #2022. (DI #2022)

Listing 1--VHDL code for divide-by-4.5 circuit

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