June 5, 1997

Not just your basic ASIC libraries

IC designers do not live by reusable cores alone. Libraries of basic logic functions, memories, datapaths, and I/O cells are the glue that holds a chip together.

Core-based chip design, using predesigned and preverified logic blocks, is here. Using cores helps you shorten product-development time and manage the complexity of chips having a million or more logic gates. However, you can't just connect all the cores and get a working chip. You also have to use lower complexity logic blocks, often called "glue logic," to connect the larger and more complex chip blocks. You will most likely have some memory on-chip and possibly other blocks performing datapath or arithmetic functions. Finally, you need some way of bringing control and data signals on- and off-chip, usually with one or more standard I/O interfaces.

An ASIC library provides the IC cells and blocks to help you with intercore and I/O functions. When choosing a library for your chip design, you have to consider the library attributes, such as available functions and performance, along with how well library implementation fits into your chip-design flow. Knowing what cells to look for in an ASIC library and where you can get those cells will help you successfully complete your core-based chip designs.

Why you need ASIC libraries

The ASIC chips you design now probably include one or more cores. These cores, developed and proven by either an ASIC vendor or a third-party core provider, represent large blocks of logic (often referred to as "intellectual-property blocks") that you can implement on different chips. The advantages of core-based design are faster time to market and reuse of often complex logic functions.

Unfortunately, core-based chip design, particularly for complex chips, is a more difficult task than either core providers or EDA tool vendors might lead you to believe. A lack of standardization in both core- and intercore-bus specifications requires you to place custom-designed logic blocks--glue logic--between cores (Reference 1). Chip-to-chip communication is relatively well-defined, but you also need I/O logic to transfer control and data on- and off-chip. ASIC-library cells give you the basic functions you need to implement chip glue logic and I/O cells.

Assuming that you do not want to develop your own ASIC libraries, you usually get them from an ASIC vendor or a third-party library provider. Some ASIC vendors develop their own libraries, and others get theirs from a third-party source, sometimes supplementing the library with their own cells. Regardless of where you get your ASIC libraries, there are many factors to consider when making the correct library choice for your design.

What to look for in a library

An ASIC library comprises basic logic functions (and combinations of these functions), I/O cells, memories, and structured blocks. Basic logic functions and combinations of these basic functions, often called "library primitives," or "foundation cells," include functions such as AND, OR, NAND, NOR, XOR, AND-OR-Invert, one-bit adders, buffers, latches, flip-flops, and multiplexers. I/O cells implement standardized interfaces--some interfaces based on electrical and some on bus standards. Examples include TTL, PECL, and PCI. The memory group usually includes SRAM and ROM. Some ASIC vendors also have DRAM. Structured blocks include regularized-cell logic functions. The structured group are cells such as datapaths and multipliers.

(The number of interface standards available for your chips is increasing rapidly. Understanding the definition of each standard and where you use it is not a trivial matter. Table 2 lists some of the most commonly used chip-I/O interfaces, including both electrical and bus standards, and a brief description of each. You can find additional information in References 2 through 5.)

Every ASIC library should include library primitives and I/O cells. In addition, each library should include some memory capability, either as fixed blocks or compilable cells. Other blocks, such as multipliers, FIFO memories, and barrel shifters, may also be part of an ASIC library.

Some companies sell a complete, tightly integrated library. Cascade Design Automation has its Silicon-Intelligent Library cell-based product, consisting of standard cells for foundation-logic functions, I/O libraries, and compilers for memories and datapaths. Other vendors, such as Artisan Components with its Process-Perfect products, have libraries consisting of foundation and I/O cells along with memories. Lack of datapath and other structured blocks should not be a problem, because you can get these types of logic functions from some EDA and other non-ASIC-library vendors.

When choosing an ASIC library, your primary concern is finding a library for your chip's target fabrication process that has the functions and performance you need. If you buy a library designed for your process, you'll have a high level of confidence that the vendor has optimized the library's performance for that process. If you already have an ASIC library designed for another process, you can buy layout-conversion software to convert the library primitive cells to the new technology. (See box, "Layout-conversion tools.") However, these tools do not give you process-optimized cells. Furthermore, you use these tools to translate basic logic functions from one technology to another. You would use no layout-conversion tools for memories, structured blocks, or I/O cells. A library vendor "tunes" these cells to a specific process to maximize density, optimize speed, or meet interface standards.

You will probably not find an ASIC library that has all the logic, I/O, and memory functions you need. For example, graphics-workstation manufacturer Silicon Graphics (Mountain View, CA) gets libraries from many ASIC and library companies, with each division using its own vendors. Greg Buchner, Silicon Graphics' director of engineering for Onyx 2, a graphics supercomputer, indicates that his group will add or change approximately 20 cells in a library the company buys, as well as add a few more I/O cells. Silicon Graphics makes these changes either because of increased density to reduce chip cost for low-end products or because of increased performance for high-end chips. Both Buchner and Alex Silvey, a design-automation manager in Silicon Graphics' Scalable Systems Group, agree that compilable memories are more desirable than a lot of fixed memory blocks (Figure 1). Buchner and Silvey have requirements for many RAM configurations on one chip, making compiled memories simpler to implement.

As important as library performance and flexibility are, just as important is how easily the library's implementation fits into your design flow. Peter Santos, marketing director of Ca-dence's (San Jose, CA) design services, notes that chip time to market is a Cadence customer's most important design consideration. Time to market depends on both library attributes and a library's integration with EDA tools and design methodology. Closely coupled to library integration are the library cell representations, or models, also called "views," that come with the library. Table 1 shows cell representations for some ASIC companies and library vendors for physical design, HDLs, timing analysis, and power analysis.

All but one vendor in Table 1 provide both Verilog and VHDL cell representations. Industry-standard GDSII (Graphic Design System II) and LEF (Library Exchange Format) dominate the available physical-cell representations, and cell views for Quad Design's (Camarillo, CA) Motive are the most popular for timing analysis. When choosing a library, make sure that the vendor includes cell representations that are compatible with your chip-design tools. A typical design flow shows library-specific and third-party EDA tools to combine ASIC libraries and compiled blocks in one chip (Figure 2).

Another important feature of an ASIC library is how well you can place and route the cells. Many vendors have different library versions optimized for different place-and-route tools. This optimization gives you cells that are easier to place and route, are denser, and usually perform better than nonoptimized place-and-route cells. Cadence's Cell3 and Avanti's (Sunnyvale, CA) Aquarius are the tools of choice for library optimization, although Table 1 shows library optimization for other place-and-route tools and, for ASIC vendors, internally developed place-and-route tools.

Caution: ASIC libraries ahead

Before deciding which ASIC library to use, make sure that it has the features you need and that it fits into your design methodology. An important consideration is that the library cells follow the same design practices that you use in your chip design. For example, if your designs don't use pass-transistor logic, your ASIC-library cells shouldn't either. Other ASIC-library-cell features to watch for are unbuffered outputs, unbuffered clock inputs to latches and flip-flops, and the use of large transistor stacks in wide-input logic gates.

Decide if you want to buy an ASIC library from an ASIC vendor or a library provider. An ASIC-vendor-supplied library is a lower risk choice, because the ASIC company presumably verifies the library cells and compilers with its process, which is your target process. Make sure the library has the functions you need, including I/O capability. If any functions are missing, either you or the ASIC vendor must design additional cells. Also, make certain that the library has the models you need to fit within your chip-design flow. If you want optimized performance, verify that the library vendor optimizes the cells for your place-and-route tools. Finally, don't assume that every cell will work as advertised in your design. Designers often find cells that don't meet specifications. Once embedded in a complex chip design, problem cells are difficult to debug. If you have time before starting an important design, check out all cells and blocks that you intend to use, preferably on a test chip fabricated in the target process.

References

1. Lipman, Jim, "Choosing the right models for your core-based chip designs," EDN, Jan 2, 1997, pg 75.
2. Wright, Maury, "USB and IEEE 1394: pretenders, contenders, or locks for ubiquitous desktop deployment?" EDN, April 25, 1996, pg 79.
3. Prioste, Jerry E, "Exploit the potential of high-performance CMOS by selecting best interface," EDN, Oct 26, 1995, pg 121.
4. Maniwa, RT, "Logic Signals Need New Standards," Integrated System Design, February 1997, pg 44.
5. Prioste, Jerry E, "Solutions for Designing and Analyzing High Performance CMOS System Interfaces," Design SuperCon '96: High Perform-ance System Design Conference, February 1997, pg 3-1.

Acknowledgments

Thanks to Aspec Technology, Artisan Components, Motorola, and Toshiba America for providing additional I/O-interface information.

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