June 5, 1997

Use a CPLD to implement an SDRAM controller

Mark Novak, Mark F Novak and Associates

Engineers are more familiar with conventional DRAMs than they are with SDRAMs, and using SDRAMs requires expertise that only a few EEs possess. Still, SDRAM-controller designs need not be especially difficult; in this design, a CPLD handles the complex aspects.

Synchronous DRAMs (SDRAMs) will probably replace extended-data-out (EDO) DRAM as the most popular memory type. For burst cycles, SDRAMs are about twice as fast as EDO DRAMs. SDRAMs are also relatively cheap. The goal of major memory suppliers is to make SDRAMs as inexpensive as EDO DRAMs within the next few years. In addition, almost all of the leading DRAM suppliers provide SDRAMs. Finally, SDRAMs can be easier to use than EDO DRAMs.

Despite SDRAMs' likely popularity, most engineers know little about how SDRAMs work and how to use them. You can build an SDRAM controller for an Intel 80960Cx/Hx or other processor using an Altera (San Jose, CA) complex PLD (CPLD). SDRAMs have advanced through the early 2- and 4-Mbit generations and are now moving to higher densities.

Processor requirements

This control design generally applies to all µP designs, but processors with the following capabilities are the primary focus:

• Support of burst-mode memory cycles with sequential (incrementing or decrementing) addressing during the burst;

• Have an external ready pin to generate processor wait states;

• Memory-interface-bus speed from 20 to 125 MHz.

Most popular µPs include these features except, maybe, burst-mode. But you can emulate burst mode by prefetching the next word in memory following a first-word read. If the processor then requests this address, the data is immediately available; otherwise, the µP ignores the prefetched data, and a new SDRAM cycle begins.

The big difference be-tween conventional DRAMs and SDRAMs, as their name implies, is that SDRAMs are synchronous. Table 1 shows the signals in a 16-Mbit, 512k×16×2-bit SDRAM.

The signals RAS, CAS, WE, A[0:11], and DQ[0:15] have similar functions to those of a conventional DRAM. Like conventional DRAMs, SDRAMs have row and column addresses. You present the row address with RAS active low (SDRAM ACT cycle) and the column address with CAS low (a READ or WRIT cycle). Like conventional DRAMs, SDRAMs offer burst-mode cycles, analogous to page-mode memory cycles, which access different column addresses, although such cycles are somewhat more complex.

The signals CLK, CKE, and DQM[0:1] are new. CLK is the free-running, normally continuous clock to which all other signals are synchronized. CKE is an enable signal that gates the other control inputs. If CKE is false, the processor ignores the inputs. DQM[0:1] are byte-input enables during write cycles and output enables during read cycles.

For years, DRAM designers have internally partitioned conventional DRAMs into multiple banks, but the interface views the memory as one bank. The SDRAM interface now supports this multibank structure, usually providing two banks in 2-, 4-, and 16-Mbit devices and four banks in 64-Mbit devices.

To access multiple banks, SDRAMs use a command-driven interface. Conventional DRAMs use level-control signals. For example, on conventional DRAMs, a row is active as long as RAS is low. On SDRAMs, the ACT command activates a row, and the PRE or PALL command deactivates the row. Between the commands that activate and deactivate a row, you can issue other commands, including additional ACT commands, to activate other SDRAM banks.

SDRAMs support multiple banks because the architecture potentially allows for higher throughput. In practice, taking advantage of the multibank architecture can be fairly complicated. For simplicity, consider the SDRAMs as having one bank.

With conventional DRAMs, you can guess the architecture of next-generation devices. Density always increases by a factor of four. You access the added capacity via a new-address pin, which, through multiplexing, provides 2 address bits: one representing the row address; the other, the column address. SDRAMs are slightly different. Table 2 shows how the addressing differs between 16- and 64-Mbit devices.

The jump in density from 16- to 64-Mbits requires two extra address bits. The controller presents these bits to the SDRAM during the row-address (RA) cycle. Because the 64-Mbit devices have four banks, they require two B bits. The 16-Mbit devices have only two banks and one B bit. The B bits that the controller applies to the SDRAM during the column-address (CA) cycle provide no extra addressing. They merely indicate which bank the controller selects (from a previous ACT cycle). (See Table 2 for acronym definitions.) Some commands, such as PALL, ignore the B bits during the CA cycle. Note that the number of valid address bits during the CA cycle is the same in 16- and 64-Mbit devices. For each doubling of data-bus width, the device requires one fewer address bit.

Table 3 shows an address mapping for the i960 that applies to all these SDRAMs. During the column-address cycle for A[8:9], you must select a[22:23] for 16-Mbit SDRAMs and a[24:25] for 64-Mbit SDRAMs. You can use this scheme for designs that work with either 16- or 64-Mbit devices.

SDRAM state model

Figure 1 shows a simplified SDRAM state diagram for a bank of an SDRAM. Because the SDRAM includes multiple banks, the state diagram for the overall device is significantly more complex. In addition to what the figure shows, SDRAMs support a clock-suspend mode to reduce power consumption via the clock-enable signal, CKE. Lowering CKE to logic zero suspends the clock and the operation in progress. If the SDRAM is in the IDLE state at the start of clock suspend, the device automatically refreshes itself. The demonstration circuit ties CKE high and doesn't use this feature.

Automatic state transitions don't necessarily happen in one clock period. You can measure the delays between states either in clock cycles or elapsed nanoseconds. The SDRAM samples inputs only on the clock's rising edges. For operations that use these inputs, measure the internal timing delays from the sampling-clock edge. Also, the time that the controller and the SDRAM spend in a state varies, even if the state ends in an automatic sequence. Unless you terminate read and write commands early, they remain active until the burst length equals the value that you specify.

Before they can execute, the READ, READP, WRIT, and WRITP commands all require that a bank be in the ROW ACTIVE state. Because several banks can be in the ROW ACTIVE state at once, the B bits select the bank to which these commands apply. The PALL command is special in that the controller applies it while the SDRAM is in a ROW ACTIVE state. The SDRAM ignores the B bits during this command, however.

Table 4 gives the command encoding for 16-Mbit devices (without CKE, which is always true in this design). DESL and NOP are functionally equal.

Tour of the states

Like conventional DRAMs, SDRAMs power up in an unknown state. The controller must first precharge the cells. To accomplish this task, the controller issues the PALL command. After precharge, the SDRAMs automatically go to IDLE as shown by the bold-arrow state transitions in Figure 1.

After the initial precharge, the controller programs the configuration register using a mode-register-set (MRS) command, which sets the read and write burst length, wrap type (sequential or interleaved), CAS latency, and options. The configuration register is write-only and uses the address bits A[0:11] (A[0:13] for 64-Mbit SDRAMs) as data signals during the MRS command (explaining the V bits for A[0:11] in Table 4). The sample circuit implements this arrangement by using a 64-kbyte MRS window in the i960 memory space to allow a[2:15] to map to A[0:13] of the SDRAMs. The program can either exclusively reserve the memory, or a control bit in a register can select between normal memory accesses and MRS cycles.

Once the controller programs the configuration register, the SDRAMs require a number of REF cycles to charge internal nodes. From then on, the controller must periodically execute REF commands, such as those that conventional DRAMs require.

To get to the read/write states, the controller presents the ACT command along with the row address, which corresponds to RAS falling in a conventional DRAM cycle. Note that after ACT executes, RAS need not remain low. Once the bank is active, you can access the memory by executing the read/write commands. In conventional DRAMs, you do the same thing by cycling CAS while holding RAS low.

To return to IDLE, execute either an explicit precharge command (PRE or PALL) or a read or write command with precharge at the end (READP or WRITP). This approach provides the precharge the same way the RAS high interval between memory cycles does for a conventional DRAM.

Read-write cycle example

Figure 2 shows an SDRAM read cycle followed by a write cycle in the same row at a clock frequency of 100 MHz. At the start of the cycle, ACT executes with the row address, taking the bank out of IDLE. The delay from ACT to READ satisfies the RAS-to-CAS minimum delay (t_RCD). The delay from READ to data output is three clocks (as the configuration register's CAS-latency field indicates). A request from the µP causes the controller to read 2 words from the SDRAM (in which the word length is the same as the SDRAM-data-bus width). CAS latency for reads is always between one and four cycles (three for some SDRAMs). The configuration register's burst-length field determines the burst length.

After issuing READ, the controller issues NOPs until it issues WRIT. The SDRAM internally latches the column address it receives during READ and WRIT at the start of the burst and automatically adjusts this address during the burst.

CAS latency is always effectively zero for WRIT/WRITP commands. While the write burst is in progress, the controller places NOP on the control lines. To conclude the cycle, PRE returns the bank to IDLE (as does RAS rising at the end of a conventional DRAM cycle). The delay between the last write-data input and the PRE command satisfies a timing requirement for some SDRAMs (typically, 15 to 20 nsec).

In addition to the signals shown, there is a low-active signal, DQM, for each 8 data-bus bits. During read cycles, this signal enables the three-state data-bus outputs. During write cycles, the signal acts as a write enable. DQM must be low during write cycles if you want the data in memory to change. This signal is synchronous, and its timing varies between read and write cycles. For read cycles on most SDRAMs, the signal has a delay of two clocks (similar to a CAS latency of two). For write cycles, the signal has a delay of zero clocks. If the controller executes a read command with a CAS latency of one, DQM must be true one clock before the controller issues the read command.

Burst cycles

The big advantage of SDRAMs over conventional DRAMs is the performance gain when the processor accesses memory in bursts. Every read/write cycle is automatically a burst cycle whose length is the value in the configuration register's burst-length field. If you do not want to execute a complete burst cycle, you can use another command to interrupt burst cycles early. (Be careful: Early-termination restrictions apply to almost all manufacturers' parts, and no two manufacturers seem to follow the same rules.) Most SDRAMs support burst lengths of one, two, four, eight, and full page (512 or 1024 words) burst cycles. SDRAMs use the four commands, READ, READP, WRIT, and WRITP, to handle bursts. The READP and WRITP commands automatically execute a precharge command at the end of the burst. The READ and WRIT commands do not do so in anticipation of another read/write command.

Burst length is slightly confusing in that it indicates the number of data words that transfer during each uninterrupted read or write command. After issuing the command, the controller sets the active command to NOP until the burst finishes. At that time, the SDRAM transitions back to a ROW-ACTIVE state. The controller can service processor-burst cycles by stringing together multiple short READ or WRIT commands. For the i960, using a burst length greater than one SDRAM burst cycle is awkward, because processor burst length varies from 1 to 4 words and can equal 3 words. The controller does not know the number of cycles in the processor burst until the µP asserts BLAST (Burst Last). So, the sample circuit implements processor bursts by setting the SDRAM burst length to one memory cycle and issuing back-to-back READ/WRIT commands. This approach doesn't work for all SDRAMs, however. Some devices don't support read/write commands on consecutive clock cycles.

If processor burst length is greater than one memory cycle, the controller adjusts the address that the read/write command latches for each successive transferred word. Only the least significant bits of the column address, A[0:log₂(Burst Length)­1], change; the upper address bits don't change. In the following loop, the start address of the burst (Start), wrap type, and the burst length determine the adjustments to the least significant bits:

for( i = 0; i Burst_Length; i++)

if( Wrap_Type == 0 ) /* SEQUENTIAL */

lsbs = (Start + i) % Burst_Length;

else /* Wrap_Type == 1 -- INTERLEAVED */

lsbs = (Start^i) % Burst_Length;

Controller specifications

The SDRAM controller controls 16- and 64-Mbit, 4-, 8-, or 16-bit-wide SDRAMs and supports CAS latencies of one or two clock cycles. The device works with an Intel i960Cx/Hx processor with a 33-MHz or slower bus clock. The controller also receives asynchronous refresh requests from an external timer and supports i960 nonpipelined burst-mode transfers of 1 to 4 words as well as one bank of SDRAM. It uses a 64-kbyte space (that an external select controls) for the MRS command and uses the processor-bus clock as the SDRAM clock.

To provide these capabilities, the SDRAM controller requires SDRAMs that meet the specifications in Table 5. The last time in the table is subtle in that SDRAMs usually specify different access times, depending on whether CAS latency is one or two clock cycles. If you use CAS latency of one clock cycle, make sure that you can access your SDRAMs within 20 nsec.

There is some confusion regarding the data-hold time that 80960Cx devices require. Data sheets for the 80960CA-33 indicate that the data must be stable for 3 nsec after the clock's rising edge. Most SDRAMs can achieve this hold time, but the 80960CF and slower 80960CAs require a data-hold time of 5 nsec, which is 2 nsec longer than what most SDRAMs are capable of. Fulfilling this requirement is easy for the 80960Hx, which has a data-hold-time spec of 1.5 nsec.

Schematic

Figure 3 shows the schematic of the demonstration SDRAM-controller system, including the i960 processor, the SDRAM-controller CPLD, the SDRAMs, and a bank of Q switches. These switches isolate the SDRAM data bus from the i960 data bus and convert the 5V levels to the 3.3V levels that SDRAMs require. The schematic is straightforward; the design of the Altera CPLD hides most of the complexity.

An Altera EPM7128ELC84-7, which has a 7-nsec propagation delay from input to output, implements the SDRAM controller. Some signals, such as CYCRUN\, actually have a 4.5-nsec delay from CLK to output. The schematic uses 16-Mbit SDRAMs and implements Fujitsu (San Jose, CA) MB811641642A-84 devices, which can handle a CAS latency of two clock periods at 33 MHz. Be careful to connect the EPM7128ELC84-7 V_CCIO supply pins to the 3.3V supply to avoid overdriving the SDRAMs' 3.3V inputs. The QS32X245 Q switches come from Quality Semiconductor (Santa Clara, CA). The circuit also requires bypass capacitors, which do not appear in the schematic.

Here is a brief description of the signals:

• A[2:31], D[0:31], BE\[0:3] are the i960 address, data, and byte-enable buses, respectively--directly from the processor and unbuffered.

• ADS\, WR\, and BLAST\ are the direct, unbuffered control lines from the i960.

• RESET\ is the same signal that resets the i960, but RESET\ must remain low for at least 100 µsec after power-up.

• REFRQ is an asynchronous clock that requests refresh cycles every 15.625 µsec. The clock-high time must be at least twice the period of the processor clock. Disable REFRQ until after the first MRS cycle.

• READY\ is the SDRAM-ready signal to the i960. The demonstration circuit uses a totem-pole driver. You must change this circuit if multiple sources drive the i960 READY\ line.

• CL1 is high to select CAS latency of one clock period and low to select CAS latency of two clock periods. A latched control bit from an external control register drives this line.

• DRAMSIZE is low to select 16-Mbit devices and high to select 64-Mbit devices. A latched control bit also drives this line.

• MRSSEL is high to exclusively select MRS cycles and low to select normal memory cycles. Either a latched control bit or a decoded i960 address-space select drives this line.

• RA[0:11] are the SDRAM's multiplexed address bits. RA[12:13] are unconnected unless you are using 64-Mbit devices.

• CLK is the i960 processor clock, which should have a duty cycle as close to 50% as possible for compatibility with the Q-switch circuit.

If CAS latency is two clock cycles, the cycle immediately following the end of an i960 burst read may be the address-select (ADS) cycle for a write. In this event, the SDRAMs may still send read data while the i960 presents the address for the write cycle. The SDRAMs do not actually release the data bus to assume the high-impedance state until some time after the clock edge that ends the ADS cycle. Immediately following this clock edge, the i960 can drive the write data onto the data bus. To eliminate contention, the Q switches disconnect the i960 from the SDRAM data bus during the first half of the clock cycle following ADS.

Even if there is no contention and you use an 80960CX, you must convert the data-bus signals from 5V levels to the 3.3V levels that the SDRAMs require. To clip at 3.3V, the Q switches must operate from a supply of about 4.4V. You can create this voltage using a 0.6V diode drop from the 5V supply to the Q switches' V_CC inputs.

Figure 4 shows what the SDRAM-controller CPLD should generate for several i960 SDRAM requests. Note that the SDRAM-controller CPLD generates SDRAM-address and -control signals, the READY\ signal to the i960, and the enable signal for the Q switches.

Altera HDL (AHDL) is often the language of choice for designing an Altera CPLD. In addition to AHDL, Altera supports VHDL. The source code was written, compiled, simulated, and timing-verified using the MAX+plus II Version 6.0 tools. (Click here to download the file 09MS138.LST.)

The source code includes control logic using a Mealy state machine and address-multiplexing logic. The control logic uses a Mealy-model state machine, which gives the fastest response when the processor requests a memory cycle. This type of state machine creates many hazards, which are visible as glitches on the control lines, but, because the design is synchronous, the glitches need only settle out in time to meet the clock-setup time. A Moore state machine would not create these external glitches but would be significantly slower than the Mealy model.

The control logic automatically generates the PALL command on the rising edge of RESET\. This situation means RESET\ must remain low until the SDRAMs meet the power-up conditions (at least a 100-µsec delay).

The state machine uses the MRSSEL signal to select MRS cycles. In an MRS cycle, the controller drives the address bits [2:15] as data bits to set the SDRAM mode register.

The source code's REGCA signals are early versions of the two least significant address bits during burst cycles. The REGCA signals provide addresses to the SDRAMs early, so that the controller inserts wait states only at the start of a burst. This sequence of operations explains why sequential access is important in a burst cycle: The controller calculates the address before the processor presents it to the controller. This design increments only the REGCA signals. If your processor uses different or additional sequencing, implement it in place of the REGCA updata logic.

The address-multiplexing logic implements Table 3 and includes the multiplexing logic to drive the address bits during an MRS cycle.

Even with fast processors, using state-of-the-art CPLDs to design high-performance SDRAM controllers is straightforward. More speed and more capabilities will come--in processors, memory, and CPLDs. Advances in CPLD technology will more than keep pace with those in memories.

You can extend these design fundamentals by adding SDRAM-module support, supporting more banks, allowing the use of 256-Mbit SDRAM components, implementing caching using several active banks at a time, and conserving power by using the CKE line to disable the clock. As so many textbooks say, "These modifications are left as exercises for the reader."

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