June 5, 1997

Thumbs up for Hands-on

In "Demystifying ADCs" (EDN, March 27, 1997, pg 26), Bill Travis discusses a problem with a 14-bit ADC that shows reasonable harmonics at full-scale input, bad harmonics at one-tenth full scale, and good harmonics again at 1/1000 full scale. He says no one can explain this phenomenon, but the explanation is obvious; he is having a most-significant-bit transition-error problem.

With large signals, the relative probability of bouncing around the most significant bit is small as long as the input frequency is high. (Incidentally, you have a weird result for very low input frequencies, because the output becomes extremely noisy as it passes through the most-significant-bit region and then gets quiet again.) But when you lower the amplitude to 200 mV, you suddenly begin bouncing back and forth across the most-significant-bit regions with each cycle, and now the most-significant-bit error is significant relative to the signal amplitude. When you further reduce the signal amplitude, the inherent dc offset pulls you away from the most-significant-bit transition, and things become quiet (or distortion-free) again.

The "dither" technique can greatly reduce this problem. When done properly, it does not introduce any errors in the resultant data. A small, random error signal is added to the input analog, but then its value is digitally subtracted at the output, resulting in the correct digital result for the original analog input. (You introduced this error, so you know its amplitude and can subtract it.) The result is that the conversion for a given analog input level goes through many "bins" of the ADC's digitization, thus averaging the bin errors over time. I look forward to the rest of Travis' series.

Ken Hatch, KLA Instruments, San Jose, CA

One of the toughest chores, by far, is the testing and characterization of ADCs. Bill Travis' is the first article I've seen that starts to describe how difficult this kind of thing really is and why. I'm very much looking forward to the follow-up articles on this topic. Good job!

Eric Johnson, Quantum Corp, Milpitas, CA

I enjoyed Bill Travis' article on ADCs, and I'm looking forward to the follow-up article. I have just designed a four-channel, 12-bit, 60M-sample/sec VME board for a military customer. I'm building it now, and I'm anxious to begin testing. I'm writing in regard to Figure 9 of the article (pg 43) and the glitching that shows up in the reconstructed data. I've seen this problem, too, using Analog Devices' parts AD9020 and AD9042. I found that the problem had two sources: improper clocking of the data latch and improper termination of the datapath. Correcting the clocking issue is a matter of carefully controlling setups and holds relative to the latch. However, termination of the datapath is necessary, even with the correct clocking. In fact, the termination of the datapath is necessary to make accurate measurements on the digital transitions.

I'm amazed that the glitches "disappeared" when you doubled the sample rate from 40 to 80 MHz. Figure 9 shows how the glitches fall in roughly the same place on the waveform. If you examine the data more closely, you may find that those glitches are transition points in the digital codes in which a large number of bits switch (for example, 0FFh to 100h). It may be the latch, but I think the glitches would be spread a little more randomly if it were only clocking. I think it may also involve the higher sample frequency reducing the number of bits in transition from sample to sample, thus reducing the noise. When the signal level crosses through the 0 offset of the part (1FF to 200 transition), the circuit is in a lower noise state and can more readily absorb this worst-case transition. I would be curious to see what happens when you change the sample frequency from 40 to 80 MHz while doubling the frequency of the input signal.

Jim Tatem, via the Internet

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