June 19, 1997

Inverting latches make simple VCO

Ed Nielson, VLSI Technology, Sophia Antipolis, France

The output frequency of the simple VCO in Figure 1, which is synthesized from inverting latch stages, is tunable to an integer multiple of the input frequency by selecting which output phases feed back to the input multiplexer. The circuit has worked successfully in on-chip clock multiplication in ASICs. The number of latch stages that you can cascade in a real-world design limits the multiplication factor. However, this circuit is practical for applications that require low size, cost, and power consumption but that don't require output frequencies in the hundreds of megahertz. You can also use this circuit to implement a fixed delay, such as a 90° delay of a master clock (Figure 3c).

You can implement a charge-pump VCO in several ways, but using inverting latches offers the advantage of having both a clock phase and its complement available at the output of each stage. You can then recombine the output phases of each VCO phase using simple combinatorial logic to provide intermediate multiples of the input frequency. That is, you can multiplex the feedback from the last stages of the VCO to the first VCO stage (Figures 3a and 3b). Another advantage is that this VCO provides an output clock with a 50% duty cycle, which is independent of the duty cycle of the input because the design compares the rising edge of F₁ to the rising edge of the reference input.

The general expressions for uppercase phi_OUT for odd and even numbers of stages are as follows:

You can use this VCO in a general PLL design (Figure 2). In this design, uppercase phi₁ feeds back to the phase/frequency detector for comparison with CLKIN. In the locked state, uppercase phi₁=CLKIN, and the VCO runs at the same frequency as uppercase phi₁. The output phases of the VCO drive the clock generator and combine to create a CLKOUT that is a multiple of CLKIN.

In each latch stage of the VCO (Figure 1b), the size of the transistors must be appropriate to control the discharge of the input to the transistors' respective NAND gates. By controlling the gate voltage to these two transistors with the voltage-control signal, VCO_CTL, you can control the stage delay and thus control the VCO's overall frequency of operation. Only the falling edge of the input to the NAND-gate latches has an effect on the frequency of operation because that latch trips on a transition to 0 at the input.

The implementation of this VCO in Figure 1a uses four stages and a 13-MHz input frequency. Two select lines allow you to program the output for 13, 26, 39, or 52 MHz. This design in 0.6-mm technology runs from 2.7 to 3.65V. At 2.7V, the input range is 8 to 16 MHz; at 4.5 to 5.5V, the input range is 8 to 20 MHz. The PLL's lock time is less than 5 msec, and worst-case output jitter at 13 MHz is 1.5 nsec. Supply current is less than 1 mA.

This circuit requires a few special design considerations. Switching to or from multiplication by three changes the electrical characteristics of the VCO. (With the same voltage on the control line, the three-stage VCO runs faster than the four-stage VCO.) This feature requires the VCO to relock when switching between three and four stages. One approach is to mask the output clock during this relock period. Another possible approach is to increase the number of VCO stages to 12, which allows switching among one, two, three, and four stages without losing lock.

Another design consideration is that you allow only one select line to change at any time. Otherwise, when switching from 00 to 11 or back, if the second control line changes state before the first, there can be a glitch going from first three, then four VCO stages in operation.

Finally, to ensure an equal delay between each stage, each output stage must have the same load. Because stages 3 and 4 multiplex back to Stage 1, you may need to include dummy devices between the other stages to compensate. (DI #2047)

| EDN Access | Feedback | Table of Contents |