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June 19,
1997
WHAT'S HOT IN THE DESIGN COMMUNITY
Analog
designers have long coveted FPGAs' versatility. Now,
these designers have their own versatility: the MPAA020
field-programmable analog array (FPAA) and its MPAA3DS
development-system evaluation kit from Motorola. The FPAA
contains an array of 20 identical configurable analog
blocks, arranged in a four×five-block matrix. Each block
includes a switched-capacitor op amp, a comparator,
capacitor arrays, CMOS switches, and static RAM. The SRAM
data controls the switches that set static and dynamic
capacitance values in the op-amp input and feedback
paths. Using an MPAA block, you can build programmable
gain stages, analog adders or subtracters, and
first-order filters. You use multiple blocks to configure
higher level functions, such as biquad filters, PLLs, or
level detectors. Bandwidth is approximately 200 kHz, with
integral and differential nonlinearity of less than 0.15
and 0.24 LSB, respectively.
The
development kit includes a PC interface and a CD-ROM with
an interactive design tool for Windows, along with a
library of macros for gain stages, a track-and-hold
amplifier, a rectifier, and various filters. The board
provides interface headers, so that you can monitor input
and output signals, plus a breadboard area for additional
circuitry. The MPAA020 analog array costs $50 in small
quantities, and the development kit costs $1500.
--by Bill Schweber
Motorola Semiconductor Products Sector, Phoenix, AZ. 1-602-413-4034, www.mot.com/sps/general.
IR transceivers for IrDA pack a lot
into little space
Infrared
transmission and IrDA (Infrared Data Association)
standards let you build short-distance, medium-rate link
capability into your PC, peripheral, personal digital
assistant, cellular phone, or pager. This ability can
eliminate the need for an electromechanical connector and
its requisite enclosure opening, which can diminish your
system's integrity. Temic Semiconductor has enhanced the
performance and more than halved the size of the needed
IR transceiver compared with existing transceivers. The
company's TFDU4100 supports 115.2-kbps data rates at
distances as long as 3m; the similar TFDU6100 supports
4-Mbps data rates at 1m. Both transceivers integrate the
optical components along with the mixed-signal control
IC--which includes receiver automatic gain control, a
transmitting driver, a receiving amplifier, and a
comparator--in a 4-mm-high, 9.7×4.7-mm package. You can
use the same surface-mount device for either side- or
top-view pc-board applications.
The slower
IrDA transceiver requires 3V at 1.5 mA for receiving, or
5V/2.5 mA, and operates as low as 2.4V for
less-than-standard distances. Maximum transmit current is
0.5A; a typical transmission duty cycle is about 20%. The
faster transceiver uses a 4.5 to 5.5V supply with a
typical receiving supply current of 5 mA. Both the $2.90
(1000) TFDU4100 and the $5.40 (1000) TFDU6100 also
support a standby mode with currents of 500 nA and 100
µA, respectively.
--by Bill Schweber
Temic Semiconductors, Santa Clara, CA. 1-408-567-8220, www.temic.com.
Gate-count claims continue to rise
New devices
set claimed-gate-count records for the two largest
programmable-logic companies, Altera and Xilinx. Xilinx's
3.3V XC4085XL, 40% larger than the company's next-
biggest XC4000-series device, delivers, the vendor
estimates, 85,000 logic gates. Xilinx's FPGA architecture
distributes RAM in small portions within each logic
block's look-up table (LUT). The company's gate-count
measurement assumes use of all of this available RAM as
logic (at 9.5 to 12.6 equivalent ASIC gates per
four-input LUT and flip-flop, depending on the device).
The XC4084XL, currently sampling, costs $1530 (100) and
comes in PGA and BGA packages.
Altera's
EPF10K130V, according to the company, delivers as many as
130,000 "typical" gates and also operates at
3.3V. The Flex10K architecture differs from Xilinx's
architecture in several ways. Specifically, for gate
counting, the EPF10K130 contains 32 kbits of dedicated
RAM in addition to LUT memory. Altera's
"typical" gate-counting procedure assumes that
the device uses all LUTs for logic (at approximately 12
gates per four-input LUT and flip-flop). The EPF10K130V
also achieves its "typical" claimed gate count
when a design uses all dedicated RAM as on-chip memory
(at four equivalent ASIC gates per bit). To test its
calculation, Altera implemented an FFT circuit, which
took 107,000 gates in an LSI Logic (Milpitas, CA) LCA500K
gate array. This design in the EPF10K130V consumed only
52% of the logic and 75% of the memory resources. Altera
does not, however, specify how much handcrafting the PLD
design required. The EPF10K130, sampling now, comes in
PGA and BGA packages and costs $895 (5000).
Both
companies provide documentation detailing their
gate-counting schemes. Xilinx is even proposing yet
another logic-measuring method, which counts only
four-input LUT and flip-flop equivalents and ignores
dedicated memory blocks, such as those Actel (Sunnyvale,
CA), Altera, and Lattice (Hillsboro, OR) provide.
Ultimately, your success in translating gate-count
potential to reality de-pends heavily on your design's
efficiency in using the proprietary coarse-grained logic
structures and available routing resources.
--by Brian Dipert
Altera Corp, San Jose, CA. 1-408-894-7000, fax
1-408-435-1394, www.altera.com.
Xilinx Inc, San Jose, CA. 1-408-559-7778, fax
1-408-879-4780, www.xilinx.com.
Color DSOs with gray-scale display
hit 400-MHz bandwidth
Late last
year, Gould announced the DSP-based TruTrace
intensity-modulation feature in its Classic DSO series.
But with a 200-MHz bandwidth and a maximum real-time
sampling rate of 100M samples/sec, the first member of
that family was too slow for many applications. Two new
four-channel color-display models remove the bandwidth
and sampling-rate issues for most users. The $9950
Classic 6500 ups the real-time sampling rate to 500M
samples/sec with all channels active (1G sample/sec if
you shut down one channel). The $11,500 Classic 9500
doubles the sampling rate and doubles the bandwidth to
400 MHz. Besides TruTrace, both scopes offer
50k-sample/channel standard memory depth and optional 1M
sample/channel. A floppy-disk drive, the ability to
sample in equivalent as well as real time, and FFT
capability are standard features. Depending on the memory
depth, the FFTs can use as many as 32k data points.
--by Dan Strassberg
Gould Instrument Systems, Valley View, OH. 1-216-328-7000,
fax 1-216-328-7400. www.gould.co.uk/.
$599 parallel-port unit turns PC
into 100M-sample/sec DSO
Are you tired
of looking at waveforms on a 7- or even 9-in. display? An
unusual DSO provides a bigger picture--in full color--on
a PC's screen. The two-channel, 30-MHz-bandwidth DSO,
Link Instruments' DSO-2102M, costs $599. At that price,
the scope and a Pentium PC cost no more than any of
several scopes that Link considers competitive. Moreover,
the new scope offers triggering features that competitive
scopes lack. The 9-oz, 7×3.5×1-in. (plus power supply)
unit plugs into the PC's parallel port. The vendor
supplies software to run the scope under Windows 3.1,
Windows 95, and MS-DOS. The DSO takes 100M
samples/sec/channel in real time via a separate flash ADC
and 32k-sample acquisition memory for each channel. A
similar unit, the DSO 2102S, costs $499 and lacks only
the advanced triggering and waveform-analysis features.
Link's
competitive analysis makes several points with which
other DSO manufacturers may take issue. For example, the
lowest priced unit with which Link compares the DSO-2102M
is Tektronix's (Beaverton, OR) TDS 210 ($995). The Tek
unit costs only $396 more than the DSO-2102M. That
difference won't buy the PC that the Link unit requires.
Moreover, most of the scopes with which Link compares the
DSO-2102M have greater bandwidth. Some of the comparison
units must use equivalent-time sampling to view
full-bandwidth signals, however. The Link units operate
strictly in real time.
The DSO-2102M
triggers not only on pulse width, but also on the nth
occurrence of a pulse of a specified width. Moreover, you
can set the scope to wait to trigger until after the
occurrence of n waveform edges that meet the trigger
specifications. The unit also measures 45 pulse
parameters and performs pass/fail testing using 10 sets
of pulse parameters or high/low limits. Finally, the unit
calculates 32k-point FFTs. Although FFT capability is
available on most of the competitive units, it is
typically optional.
--by Dan Strassberg
Link Instruments Inc, Fairfield, NJ. 1-201-808-8990,
fax 1-201-808-8786, www.linkinstruments.com.
Mini-Circuits receives ISO 9001 certification
Mini-Circuits,
a manufacturer of RF, IF, and microwave components for
wireless communication has re-ceived certification to
meet the ISO 9001 International Quality Management System
Standard. The certification covers all systems and
activities at the company's headquarters and
manufacturing facility, as well as its Deer Park, NY, and
Branson, MO, locations.
--by Fran Granville
Mini-Circuits, Brooklyn, NY. 1-718-934-4500, fax
1-718-332-4661.
Wide gain range lets CCD ADC
run from light to dark
CCDs for
imaging applications have unique signal-processing
requirements. Exar's CMOS signal processors, the 5V
XRD4460 and 3V XR44L60, contain a correlated double
sample-and-hold function; a 10-bit, 15M-sample/sec A/D
converter; a programmable gain amplifier (PGA); a timing
generator; and automatic offset-calibration circuitry.
The PGA's 2 to 80 gain lets you use the device to handle
a range of brightness and lighting conditions in
applications such as digital camcorders, videocameras,
scanners, and still cameras. You set both the PGA gain
and the offset calibration via a serial interface.
Differential
nonlinearity is 0.74 LSB at both minimum and maximum
gain, and integral nonlinearity is 2 LSB. The 48-pin,
$5.95 (1000) FQFP devices can use an active-high or -low
clock for the correlated double-sampling function. The 5
and 3V devices dissipate 250 and 150 mW, respectively.
Both ICs also feature a 1-mW power-down mode.
--by Bill Schweber
Exar Corp, Fremont, CA. 1-510-668-7000, www.exar.com.
Dynamic-system tools ease
embedded-system design
The MathWorks
has combined two new tools and one enhanced tool to help
you model, simulate, and virtually prototype real-time
embedded systems. You use Simulink, Stateflow, and
Real-Time Workshop for designing various dynamic systems,
including linear, nonlinear, discrete-time,
continuous-time, and hybrid systems.
Simulink, an
interactive modeling and simulation environment, lets you
build block-diagram system models from a library of
predefined components. The components include stimulation
and noise sources; discrete, linear, and nonlinear
functions; and interblock connections. It also provides
oscilloscope and numeric-display blocks for visualizing
results while simulations are running. If you can't find
a function you need in the library, Simulink lets you add
your own blocks or customize existing library blocks.
You use
MathWorks' Stateflow to graphically model and simulate
event-driven control systems expressed as finite-state
machines. Put Stateflow diagrams into Simulink models to
add event-driven behavior to your simulations. When you
finish a system model, you use Real-Time Workshop to
translate the model into C code. You use this code for
hardware-in-the-loop simulation and real-time-system
prototyping. MathWorks designed Real-Time Workshop's
generated code for speed and target independence, so you
can run it on a range of systems.
You can get
all three tools for Windows-, Macintosh OS-, and
Unix-based platforms. Prices start at $1995 for Simulink,
$9995 for Real-Time Workshop, and $1995 for Stateflow.
The Stateflow code generator costs $1995 extra.
--by Jim Lipman
The MathWorks, Natick, MA. 1-508-647-7000, fax
1-508-647-7001, www.mathworks.com.
Free Internet resources optimize
programmable-logic designs
If you use
Lattice Semiconductor's (Hillsboro, OR) or Altera's (San
Jose, CA) PLDs, two free resources are available. ISDATA
GmbH lets you e-mail your Lattice asynchronous file (LAF)
netlist that you created with your tools, and ISDATA
resynthesizes, that LAF with the company's compiler. If
the results are smaller or faster than your existing
design, ISDATA sends you a free, improved LAF along with
statistics and more information on the company's tool
set. If the results are equivalent or worse, ISDATA lets
you know. ISDATA automatically deletes design files from
its server after processing. You can find more
information and a submission form, at
www.isdata.de/english/ laf.htm.
You can get
parameterized functions for Altera PLDs, as well as other
design suggestions from the FreeCore library at
http://193.215.128.3/ freecore. Rune Baeverrud, a
distributor field-application engineer for Altera,
developed most of the cores for the library, which
contains various documented UARTs, I2C
controllers, a frequency divider, and a gray-code
counter. Baeverrud offers the cores without guarantees
and with minimal technical support, and Altera does not
officially sanction his site.
--by Brian Dipert
ISDATA GmbH, Karlsruhe, Germany. +49 721 751087, fax
+49 721 752634, www.isdata.de.
RFID tags shrink and gain flexibility
Radio-frequency
identification (RFID) takes a new form in the Interactive
Identification (I2) technology from SCS Corp.
Except for the tiny bulge of an embedded IC, an I2
RFID tag looks and feels like a short strip of flexible
plastic tape. Each 2.4×0.4×0.004-in. tag re-ceives and
transmits data at 2.4 GHz without a battery, using
on-chip circuitry to convert and store energy from
received signals' carrier waves. Read and write distances
are nominally a foot or so, but they can be considerably
greater, depending on the power transmitted by the
scanner unit that reads and writes to the tags.
The I2
tags owe their size to their 2.4-GHz operating frequency,
which allows printing an antenna on each flexible tag. In
contrast, RFID tags that operate at lower frequencies
require embedded coil antennas. For reliable operation,
the I2 technology uses frequency-hopping
spread-spectrum techniques similar to those of wireless
LANs. You need an FCC license to use some ac-operated
scanners, but you can use low-power, handheld scanners
without a license. Both types of scanners are available
from SCS. SCS envisions that the tags will find use in
baggage-handling, parcel-tracking, and uniform-rental
applications. (The tags can be sewn into the seam of a
garment and can withstand commercial laundering.)
Each tag's 1
kbit of antifuse memory allows storing and updating
information that could include ownership, itinerary, a
record of operations, control codes, and so forth. SCS
says the CMOS technology it developed for the tags allows
programming with only 4V and microamps instead of a
typical 8V and milliamps for conventional programmable
logic. In addition, read and write times are nominally 4
and 9 msec, respectively, for a 16-bit word--short enough
to allow nearly simultaneous processing of multiple tags.
An I2 tag costs $0.95 (100,000). A development
kit, including a scanner, software, and 1000 tags, costs
$4500.
--by Gary Legg
SCS Corp, San Diego, CA. 1-619-485-9196, fax
1-619-485-0561.
Chip-layout tools take different paths
Increasingly
complex chips, with logic densities of 1 million or more
gates are requiring enhanced layout tools for design
placement and routing. Two companies are addressing this
issue in different ways--one with faster place-and-route
algorithms and the other with a parallel-processor layout
approach.
Cadence
Design Systems has announced Silicon Ensemble-DSM for
deep-submicron design, a place-and-route tool suite that
uses new technologies. Cadence claims that its Ensemble's
router, WarpRoute, is three to 20 times faster than
competitive chip routers. WarpRoute also has a new
"search-and-repair" capability that lets you
more easily correct routing violations than with previous
Cadence layout tools. Silicon Ensemble-DSM's
block-and-cell placement tool, Q-Place, has been around
for a few years but now boasts enhancements that give you
smaller chips and runtimes, according to Cadence. Cadence
has also redesigned Ensemble's compaction technology,
FlexChip, for better block compaction, automated
floorplan resizing, minimized congestion, and an enhanced
graphical user interface. Silicon Ensemble-DSM is
available now for Unix workstations with a price starting
at $316,000. Users of Cadence's Cell3 and Silicon
Ensemble layout tools can upgrade for significantly less.
You use
Gambit Automated Design's Grandmaster parallel-processor
place-and-route system for standard-cell, gate-array, or
embedded-array (cell-based blocks in a gate array)
designs. The tool has automatic scheduling capability,
allowing it to automatically assign areas of a chip to
separate processors for certain types of place-and-route
tasks, such as block placement and final routing.
Additional Grandmaster capabilities include clock-tree
synthesis for spine and balanced-tree clocking, a
timing-delay calculator, and search and repair of both
shorts and opens. Grandmaster is available now on Sun and
HaL Unix platforms. Gambit prices the tool at $200,000
per design and $50,000 per process. A minimum
configuration of one design on a single-processor
workstation costs $250,000. Interfaces for Cadence and
Silicon Valley Research (San Jose, CA) place-and-route
tools each cost $30,000 extra.
--by Jim Lipman
Cadence Design Systems, San Jose, CA. 1-408-943-1234, fax
1-408-943-0513, www.cadence.com.
Gambit Automated Design, San Jose, CA. 1-408-345-3555, fax
1-408-241-6741.
Intel is now
sampling the first in a planned series of processor
modules for designing the Pentium into embedded systems.
The modules pack a processor; a system controller; a
256-kbyte, layer 2 cache; a clock generator; and a
voltage regulator onto a 3×4-in. board. The modules
connect to a system baseboard through two high-density
connectors. One connector caries the DRAM interface, and
the other carries the PCI interface and miscellaneous
clock, power, and control signals. The module measures
only 0.58 in. high, including a heat sink, allowing it to
fit on a baseboard for single-slot CompactPCI or VME use.
The modules
capture most of the high-speed portion of a Pentium-based
design, simplifying the design of the baseboard. The
pin-compatible module series provides an upgrade path for
embedded Pentium designs by allowing the baseboard design
to remain unchanged. All that needs to change is the
module. The first module in the series is now sampling,
with production scheduled for October. It uses a 133-MHz
Pentium and costs $475.
--by Richard A Quinnell
Intel Corp, Chandler, AZ, 1-602-554-5128, www.intel.com/design/.
Web site helps inventors
bring creations to market
A new Web
site from Arthur D Little Enterprises (ADLE) (the
invention-management arm of consulting company Arthur D
Little Inc) helps inventors manage their inventions
online. The site, www. adlentrprises. com, guides
would-be Thomas Edisons through commercialization. The
page offers guidance on invention development and reviews
the resources available to inventors as they try to move
their inventions from the drawing board to the production
line.
The site also
provides background on ADLE's Invention Management
Program, which helps inventors determine whether their
inventions are appropriate for the program and lets them
electronically submit patented ideas. Of inventors
submitting ideas to the program, ADLE chooses fewer than
12 for its commercialization services. The company then
invests the time and financial resources to develop each
invention, secure patent protection, and then license the
invention to manufacturers. Inventors pay no fees for
submission; compensation usually takes the form of a
percentage of licensing revenue.
--by Fran Granville
Arthur D Little Enterprises, Cambridge, MA. 1-617-498-5000,
fax 1-617-498-7025.
July 14 to 18
Conference on Lasers and
Electro-optics/Pacific Rim, Chiba, Japan, highlights ultrafast optics,
lightwave communication, and consumer electronics. Among
the 15 topics are ultrafast phenomena and
optoelectronics; nonlinear optics; quantum optics and
their applications; gas, liquid, and solid-state lasers;
and semiconductor lasers and related devices. The
conference also offers three plenary talks, nine
tutorials, and 90 invited papers. CLEO/Pacific Rim,
Piscataway, NJ. 1-908-562-3895.
July 15
Data Exchange Workshop, Philadelphia, for CAD/CAM users
and managers, focuses on data-exchange topics, including
IGES, STEP, and Direct; obstacles prohibiting effective
translation; and options for overcoming common
data-integration problems. International TechneGroup Inc,
Milford, OH. 1-513-576-3833.
July 23 to 24
SMTA Academy, Columbus, OH, offers eight seminars, whose
topics include BGA; an introduction to SMT/FPT;
troubleshooting SMT/FPT; surface-mount problem solving:
design and production; designing for manufacturability,
test, and repair; pc-board design for surface-mount,
fine-pitch, BGA, and related packaging technology; and
defect-free reflow and wave soldering in SMT. The
seminars cost $295 each for SMTA members, $395 each for
nonmembers, and $95 each for students. SMTA, Minneapolis,
MN. 1-612-920-7682.
July 28 to 29
Flat Panel and Related Display
Technologies,
Mountain View, CA, describes the processing, application,
and selection of display technologies. The Program
outlines the markets for display technologies; human
vision and photometry; colorimetry; addressing and
multiplexing; CRT displays; electroluminescent displays;
plasma-display panels; LCDs; and more. Course costs $650
for SEMI members and $750 for nonmembers. Registration
deadline is June 27. SEMI, San Francisco, CA.
1-415-940-6901.
In "Design tools for
analog/mixed-signal ICs come of age" (EDN, April 24, 1997,
pg 61), Dolphin Integration's (Meylan, France) Smash
mixed-signal, multilevel simulator was inadvertently
omitted. You can contact Dolphin for information about
Smash at +33 4 7641 1096, fax +33 4 7690 2965, www.dolphin.fr.
"EDN's
1997 DSP-architecture directory" (May 8, 1997, pg 42) lists
the incorrect Web site for Lucent Technologies. The
correct address is www.lucent.com/micro. EDN apologizes for the
inconvenience.
DSP BIOS gets development support
To simplify
the programming and debugging of DSP-based designs, Texas
Instruments introduced in March a standard
application-programming interface (API) for its TMS320
DSPs. The DSP/BIOS open API standard includes a standard
set of functions that simplify code development by
allowing a BIOS call to replace custom code in many
applications. In addition, the DSP/BIOS allows the
real-time collection of code-execution information at
runtime. This information helps simplify debugging. TI
licenses the BIOS at 1% of the DSP-chip cost.
TI makes
available the BIOStation evaluation kit for the DSP
Research Tiger 542/PC development system. The DSP/BIOS
comes preconfigured for the board. The board offers a mix
of peripherals, including stereo ADC and DAC, two 8-bit
DACs, and an RJ-11 telephone interface. Prices for the
kit start at $2595. Now, a third-party tool for more
general application of the DSP/BIOS has appeared.
Spectron Microsystems has released its BIOShop software
developer's kit, which contains both an embeddable kernel
and analysis tools. The kernel implements all the
functions the DSP/BIOS API specifies for a TMS320C45x
processor. It comes as a collection of C- and
assembly-callable modules, so that a compiler can
selectively link modules to minimize memory usage. The
BIOScope analysis tools provide performance-monitoring
and event-capturing facilities in a visual host-based
environment. These facilities supplement the performance
of other development tools, such as debuggers, by giving
them real-time access to code execution. The BIOShop SDK
costs $9995 and includes three seat licenses and a
three-day training class.
--by Richard A Quinnell
DSP Research, Sunnyvale, CA. 1-408-733-1042, fax
1-408-736-3451, www.dspr.com.
Spectron Microsystems, Santa Barbara, CA.
1-805-968-5100, fax 1-805-968-9770, www.spectron.com.
Texas Instruments, Houston, TX. 1-800-477-8924, www.ti.com.
Desktop disk drives burst 7-Gbyte barrier
Maxtor became
the first disk-drive vendor to offer a 7-Gbyte, 3.5-in.
ATA drive with the announcement of the DiamondMax 1750
family. The new drives store 1750 Mbytes per platter and
come in 1.7-, 3.5-, 5.2-, and 7-Gbyte versions. By
packing more data onto each platter, the company has
lowered the cost to 7 cents per megabyte: Estimated
retail price of a 7-Gbyte model is $499. Maxtor achieved
the high capacity using standard magnetoresistive heads.
Moreover, the drives support ATA Mode 4 and the new
33-Mbyte/sec Ultra-DMA/33 mode for fast data transfers.
Maxtor claims that the fast transfer rate and new ATA
features, such as CRC error checking, allow the drives to
invade previously SCSI-only markets, such as workstations
and even disk arrays.
Meanwhile,
capacities are also skyrocketing on smaller disk drives.
IBM for example, just introduced a 5-Gbyte member of its
2.5-in. Travelstar family. The 17-mm-high Model 5GS uses
new MRX (Magnetoresistive Extended) head technology.
Simultaneously, the company introduced the 12.5-mm-high
Model 4GT that stores 4 Gbytes and also uses MRX heads.
Both IBM drives support UltraDMA/33 transfers.
Unfortunately, you pay a significant premium for high
capacity in the notebook-oriented 2.5-in. form factor.
The cost per megabyte is two to three times higher than
that of commodity desktop drives. This price gap
continues to leave the door open for upstart,
low-profile, 3-in. drive proponents Intégral
Peripherals, JTS, and Western Digital to gain market
share (For more information on disk form factors, see
"Lean, mean storage machines," EDN, Nov
7, 1996, pg 50.)
--by Maury Wright
IBM Storage Systems Division, San Jose, CA. 1-408-256-8000.
Intégral Peripherals Inc, Boulder, CO. 1-303-449-8009.
JTS Corp, San Jose, CA. 1-408-468-1800.
Maxtor Corp, Milpitas, CA. 1-408-432-1700.
Western Digital Corp, Irvine, CA. 1-714-932-5000.
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