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July 3,
1997
Fine
print II: revenge of the marketing department
Last time, I
talked about how incomplete or unclear device
documentation could give you mind-splitting headaches
when de-signing and debugging systems. To hammer the
point home, I'll share some examples of "data-sheet
distortion" that I've experienced.
Carefully
check specifications. Manufacturers often spec
the fastest speed, "bin 1," for a
device at a more restrictive voltage/temperature
range and lower maximum output loading than lower
speed bins. I'll grant that the bin 1
voltage/temperature/impedance combination they
pick may still be realistic for some
system designs. Regardless, make sure that you
understand--and that your design can handle--all
operating assumptions before designing in a bin 1
device. Taking things a step further, why do some
devices use one output-loading value for a few
specifications and another for the rest? I've
never seen a system design that can present a
5-pF load only when a device is getting off a bus
and a 30-pF load the rest of the time. That's a
trick even Harry Houdini would appreciate!
Examine
rewrite times for nonvolatile memories, such as
EEPROM and flash. A few years ago, in an attempt
to one-up its competition, a flash-memory vendor
(not my previous employer) showed a very fast
block-erase time on pg 1 of the data sheet. One
of the last notes of the last table on the last
page of the data sheet, however, stated that this
time was only the erase portion of the automated
erase algorithm, which happened to also include
several other steps. I wonder how many engineers
found out the hard way that the part actually
erased significantly slower than the pg 1
highlight claimed? Another complaint: The
marketing folks all try to one-up each other with
block-cycling specifications yet
"forget" to document the failure-rate
assumption. What good is it to have a 1
million-cycle spec if half of your population of
parts have at least one block failure by then? To
use an analogy: Would you buy a 100W stereo
amplifier if you didn't know its distortion
rating?
Check
the claims of volatile-memory vendors. How many
times have you seen a company claim its memory is
a superset of either a JEDEC or a de facto
industry standard, only to find upon closer
inspection that the amount of hardware and
software you need to implement this compatibility
is prohibitive? It reminds me of those
car-dealership ads you hear on the radio with the
features and price advertised at 110 dB, followed
by 5 seconds of triple-speed mumbling, during
which you hear the rest of the story--if you can
understand it.
Beware
of the word "typical"; it means exactly
what it says. Vendors "typically" make
"typical" specifications at room
temperature; nominal voltages; on a quiet, solid
tester; and with a sample size of one unit from
the first wafer run on the first manufacturing
pro-cess (to get the data sheet out so they could
begin marketing the part). A typical spec or
curve can provide useful information on
approximate de-vice performance in typical usage,
but save yourself the headache and don't rely on
it.
Check
the maximum claimed programmable-logic-device
gate count: When was the last time your design
got within 25% of the maximum? I'm not saying
it's impossible--only that it's often improbable
for those without intimate silicon knowledge, a
full suite of low-level design tools, and nearly
infinite amounts of time and patience. And then
there's that "100%-pin-locking" claim.
Check to see whether 100% really means 100% and
whether pin routing means "a pin,"
"some pins," or "all pins."
Although I'm
no fan of lawyers, one of their most famous expressions
applies: Caveat emptor!
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