July 17, 1997

Give DACs due diligence for superior DDS performance

Bill Schweber, Technical Editor

Direct digital synthesis uses mostly digital circuitry to control frequency and modulation, but the DDS DAC is critical to output purity. Consider the DAC parameters that are critical in your application, as well as the challenge of placing a DAC alongside fast digital circuitry.

Just as so many other system functions are "going digital," a digital technique is also challenging the generation of basic and modulated sine waves. Direct digital synthesis (DDS) combines a numerically controlled oscillator (NCO) with an output D/A converter to yield a system that can produce periodic waveforms with full digital control of frequency and phase (Figure 1). The technique offers superior phase continuity and reduced settling time with frequency changes compared with traditional oscillator and PLL methods (Reference 1).

Although the DDS concept is not new, it is increasingly attractive for communications systems as complex, high-speed logic with clock rates greater than 100 MHz becomes less costly and power-hungry (see box, "DDS: simple in concept, complex in reality"). What makes the technology even more practical is that DACs, which are key to final achievable performance, now have the update speed, resolution, bandwidth, and clean output that designs at these frequencies need. Understanding these important DAC parameters and extracting the best performance from a DAC's pote ntial are critical to successful DDS application.

DDS communication applications include cellular base stations, whose power and size constraints are far more flexible than those for handheld and portable units. They are also starting to appear in the modulating portion of the reverse channel in high-speed cable modems and are a viable choice when complex modulation patterns balance bandwidth, throughput, and efficiency. The increased use of spread-spectrum systems is driving the technology into CDMA systems.

DDS is not for every application, though. It is still bigger, more power-hungry, and more complex than a good PLL and inferior in some parameters, such as noise-waveform purity. But DDS DACs offer some attributes in agility and dynamic performance that the PLL can't match (see box, "DDS vs PLL: not necessarily competitors").

A DAC must be fast and good

You can use DDS to generate a communications carrier wave in a relatively fixed-frequency application, such as a local oscillator, or in a dynamic frequency-hopping application, such as spread-spectrum communications. You can also use DDS to control the waveform via the DDS NCO to directly manipulate the waveform's frequency and phase. Using this approach avoids those tricky analog FM and PM circuits of FSK and PSK modulation. Finally, DDS does not restrict your design to sine-wave operation. You use DDS designs in arbitrary waveform generators to provide the same flexible and direct control over the frequency and phase of any digitized waveshapes in memory.

The DAC in a DDS system, the critical digital-to-real-world connection, has severely conflicting goals. Its digital input needs to be fast, accepting 10- or 12-bit updates, typically at 50 to 100 MHz. Meanwhile, its output must settle in nanoseconds to the final analog value. Any imperfections, including deficiencies in DAC linearity, cause output distortion and frequency spurs, which, in turn, effect spectral purity, noise, and aliasing.

Digital-noise feedthrough is inherent in any mixed-signal design with high-speed digital functions residing near sensitive analog ones. Noise enters the DAC's analog sections via power rails, grounding, stray board capacitance, and internal IC paths in the bit switches.

Second, imperfections in the DAC's bit current sources, which should look ideal with infinite output impedance, cause nonlinearity. The impedance is finite and depends somewhat on the current source's output voltage. This problem occurs at both low and high frequencies but is more difficult to compensate at the higher end.

The largest sources of imperfection are DAC glitches (Figure 2a). Glitches result from timing skews among data bits within the DAC, unequal rise and falls times of the DAC logic, finite internal-settling time, and other asymmetries. As DAC speeds increase, glitch effects account for more of the DAC's error. For settling time, shorter is normally better, but be careful: A short settling time with overshoot can result in greater glitch energy and thus larger spurs. The settling time for full-scale DAC transitions is often not a primary concern, because many DDS applications do not involve large step transitions; small-signal bandwidth and settling effects are critical.

You measure glitches, often misidentified as "glitch energy," in volt-seconds and view them as time-domain effects; however, their relevant impact is in the frequency domain. Increasingly, DAC vendors are concentrating their efforts at better specs in the frequency domain, because that's the domain that concerns users. It's difficult to correlate observed glitch energy or settling time with resultant spurs and other frequency-domain imperfections.

This fact doesn't mean that vendors are ignoring glitch. It is, after all, the largest contributor to DAC and, thus, DDS errors. One technique vendors use is to build an internal feedback loop within the DAC to control glitch--if the DAC employs differential circuitry. This feedback loop minimizes total glitch energy by transforming a positive glitch into a glitch doublet with positive and negative excursions that partially cancel each other (Figure 2a). Vendors are also reducing code-dependent glitches by using segmented architectures to counteract those codes that cause larger current transitions, using an R/2R ladder for the least significant bits and a thermometer encoder for the most significant bits. The objective is to minimize glitches and equalize current shifts across all bit-transition states' values.

Improving DAC performance is not entirely a matter of better DAC internal design. The DAC package, associated circuit board, and their associated capacitive coupling limit the isolation that a system can achieve. Isolation of 40 to 60 dB between a device's analog and digital functions is necessary for acceptable performance. Nearly all DACs for DDS applications use differential circuitry to minimize noise and to balance stray effects. You must follow all the layout high-frequency guidelines on bypassing, decoupling, ground planes, and separate grounds as good design practice.

DAC accuracy is also critical, and parameters such as integral and differential nonlinearities traditionally cause harmonic distortion. However, as with glitch, you cannot easily correlate such linearity measures and frequency-domain performance.

No longer "video" DACs

Historically, DDS DACs were the same devices that high-speed DACs used to drive large, high-resolution CRTs. This case is increasingly not true for several reasons. Plain video DACs are increasingly rare; many now include video-specific look-up tables and even incorporate three independent DACs in one package for an RGB drive. Also, as DDS applications have become better defined, their requirements are more specific and frequency-domain-oriented in contrast to prominent video parameters, such as linearity.

Although the specifications you need naturally vary with the application, you'll probably be concerned about SNR and spurious-free dynamic range (SFDR). DAC resolution is the primary determinant of SNR; each bit of resolution is theoretically worth 6 dB. In practice, the actual SNR figure is lower. You measure a 10-bit, 60-dB DAC at about 50-dB SNR, and a 12-bit, 72-dB device typically performs at 60 dB. Be aware, though, that SNR is frequency-dependent, so check which frequencies the vendor specifies for it.

You measure SFDR in decibels referred to carrier. SFDR is the difference in signal energy between the desired fundamental output and the worst-case, undesired, spurious output frequencies (Figure 3). Vendor data sheets normally specify two SFDR ratings--one for a narrowband around the fundamental and the other for wideband operation up to the Nyquist frequency. The ve ndor's narrowband window should be commensurate with your application needs. Typical values for narrowband SFDR are 70 to 80 dBc, and wideband SFDR is usually approximately 50 to 65 dBc.

When evaluating a DAC for DDS, look at adjacent sections of the spectrum as you modulate and move the fundamental. DAC performance is usually code-dependent (although newer architectures are less so than in the past), with larger glitches at some digital values. Acceptable performance at one frequency may be less so at another.

Many DACs include an internal reference, which you can override with an external reference. The external reference also allows you to use the DAC as a multiplying device, which allows both relatively static gain control and dynamic modulation access. Check the multiplying bandwidth to see if it is wide enough to give you more flexibility. For example, consider Signal Processing Technologies' SPT5310, a 12-bit, 250M-sample/sec DAC with a 40-MHz multiplying bandwidth. The 15-pV-sec-glitch, ECL-compatible device specifies 54-dBc SFDR for a 20.055-MHz fundamental and 80-MHz update rate.

Targeting similar update rates, Maxim's 12-bit, 300-MHz MAX555 voltage-output device operates from a ­5.2V supply. It offers a 58-dB narrowband SFDR at maximum speed, increasing to 78 dB at a 50-MHz update rate. Both integral and differential errors are ±1/2 LSB, and the multiplying bandwidth is 10 MHz. Also in similar performance territory, Burr-Brown's 12-bit DAC600 features a 256-MHz update rate, a ­73-dBc THD at 10 MHz, and a 5.6-pV-sec glitch.

Not all applications need 12-bit resolution, so Harris Semiconductor offers 10-, 12-, and 14-bit devices. The 14-bit, 100M-sample/sec, TTL-compatible HI5741 I/O device simultaneously multiplexes as many as 20 voice channels for applications such as cellular base stations. Harris points out the device's 70-dBc multitone power ratio (MTPR), which the company determines by feeding the DAC an input pattern that represents equally spaced sine-wave tones and examining the spectral output. For conventional applications, the SFDR is 71 dBc to the Nyquist range with a 100-MHz clock and 10.1-MHz output and measured over a 50-MHz span.

Some DACs contain extra features to simplify the generation of periodic waveforms. The 10-bit, 125M-sample/sec Harris HI5721 has a control pin that, when active, inverts the sense of the lower order data bits, with the most significant bit acting as a sign bit. When you configure the memory appropriately with the NCO, the memory needs to store only 90° of information and use the inversion signal to control the sign of the output waveform.

Watch those mixed technologies

One of the largest potential challenges in joining an NCO to a DAC is mixing ICs built with different technologies. The simplest interface requirements are those of 12-bit DACs with update rates as fast as 100 MHz. These DACs are typically CMOS, and some vendors are offering 300-MHz CMOS DACs. Higher speeds require ECL with lower digital swings and a negative supply rail. ECL is viable at speeds as high as 1 GHz. For higher speeds, GaAs be-comes the next technology of choice.

Carefully study the timing of the NCO output vs the DAC input, and pay special attention to clock speed and setup-and-hold time. Some DACs require complementary clocks, and the asymmetric duty-cycle requirements of the DAC may be a problem. To reduce ringing and transients on the digital data lines between the NCO and the DAC, many designers use a 100 ohms series damping resistor to ground in each line. They also use a 50 ohms shunt termination resistor, which you may need to match NCO output impedance and DAC input impedance.

NCOs are usually single-supply ICs, whereas high-speed DACs are usually split-rail devices. It's more than single vs dual supply, though, because the single-supply DACs can be ­5.2V ECL devices. You may need level shifters between the ICs, which add cost and complicate timing for data setup and skew, both of which are critical at these components' high clock rates. You may be able to find nearly identical DACs that let you choose between a TTL and an ECL I/O device. For example, Signal Processing Technologies offers the 600-mW, ECL-compatible SPT9712 and 640-mW, TTL-compatible SPT9713, both with 12-bit, 100M-sample/sec update rates, 15-pV-sec glitch, 13-nsec settling time, and 68-dB SFDR with a 10-MHz output and a 50-MHz clock.

Grabbing the DDS output

Once you have the NCO and DAC working together properly and with the performance you need, you still have two more functional blocks to implement. The output of the high-speed DAC is a complementary current source designed to drive a low-impedance, typically 50 ohms load. You can feed the current into a resistor to produce a unipolar voltage. For a more robust voltage output, you must use a buffer amplifier; for a bipolar voltage output, you need a circuit with adjustable offset. Fortunately, the newer wideband buffers, available from DAC and op-amp vendors, have wideband, low-distortion characteristics. Provide a good, analog-only supply for the buffer to avoid any coupling of digital signals and their supply and ground noise.

Finally, provide an output filter to smooth the DAC waveform stair steps, reduce aliases, and improve SNR. Filter settling time is usually less critical, because the DAC output does not make full-scale steps unless you instruct the NCO to make large phase/frequency transitions. Most DDS implementations use passive, lowpass or bandpass, current-driven filter designs, which are often technically sufficient and less expensive than active ones (Reference 2). Such designs also do not introduce further distortion. Your filter design is more complex if the DDS spans a wide frequency range, and you may have to resort to an active design to get the needed roll-off.

When you use the DDS DAC in phase-sensitive applications, you have to factor in the filter-phase characteristics. If you use dual DACs for I/Q modulation, then you must also closely match the filters. However, the active-vs-passive filter choice is not clear-cut, because a passive filter usually needs another buffer amplifier at the final output. Also, don't rule out using a narrowband ceramic or SAW filter.

Togetherness makes it easier

Neither designing a pc board with properly matched NCO and DDS, nor designing a single IC that does both NCO and DDS is a trivial task. However, such a design is the next logical step. For example, Analog Devices offers a series of NCO/DAC DDS ICs. The AD9850 comprises a 125-MHz NCO with a 32-bit tuning word, a 10-bit DAC, and a comparator for applications that need square-wave output. It comes in a 28-pin package that operates from a 3.3 or 5V supply (Figure 4). SFDR is greater than 50 dBc with a 42-MHz output and greater than 60 dBc with a 10-MHz output.

Suppliers are also developing integrated DDS ASICs. The STEL-1109 from Stanford Telecom is an upstream modulator covering 5 to 65 MHz, combining multimode modulator with a 10-bit DAC. The device offers 10-, 20-, and 40-Mbps speeds for BPSK, QPSK, and 16-QAM modes, respectively. This 80-pin IC also includes a Reed-Solomon encoder and scrambler and a digital FIR filter to shape the modulating signal spectrum. The on-chip DAC allows the vendor to specify subsystem performance and ensure compliance with various standards, such as IEEE-802.14 LAN/MAN, Intelset IESS-308, ITU J.83 Annex A, and European Digital Audio-Visual Council 1.1 specifications.

Virtually all vendors supply DAC- and DDS-evaluation boards. Use them as starting points for your design and even as complete designs. Even vendors that are not DAC suppliers now include DACs in the increasingly mandatory evaluation boards, and you can adapt their circuits to your final design. Qualcomm provides its 100-MHz-clock Q0340-3 DDS system as a 4×7-in. pc board with digital I/O ports; a DDS core; a PC interface; software; and an Analog Devices AD9762 12-bit DAC followed by a 40-MHz, seven-pole, passive, elliptical, lowpass filter (Figure 5).

Don't forget the clock

Just as with ADCs, you can easily overlook the role of the clock when designing and testing your system (Reference 3). Vendors are likely using a clock with far less jitter in their test setup than you have in your final system. Although the standard crystal oscillator you use may be accurate and have long-term stability, its short-term jitter can cause spurs and undesired spectral components. Compare your clock with those that DAC vendors are using and measure the performance of the DAC with your lower signal source. If necessary, upgrade your clock source or implement a better one (Reference 4).

References

1. Schweber, Bill, "PLL synthesizers make channel-hopping swift and sure," EDN, March 14, 1997, pg 51.
2. Schweber, Bill, "Analog filters: even more essential in the digitized world," EDN, April 24, 1997, pg 42.
3. Travis, Bill, "Demystifying ADCs," EDN, March 27, 1997, pg 26.
4. Cusing, Richard, and Steven Swift, "A discrete, low phase noise, 125-MHz crystal oscillator for the AD9580 complete direct digital synthesizer," Analog Devices AN-419.
5. Hagen, Jon B, Radio-Frequency Electronics, Cambridge University Press, 1996.
6. Kushner, Lawrence J, and Marcus T Ainsworth, "Spurious reduction for direct digital synthesizers," Applied Microwave & Wireless, Summer 1996.

Acknowledgments

Thanks to David Crook of Analog Devices, Patrick Hanlon of Maxim Integrated Products, Jonathan King of Qualcomm, and Lee Walter of Signal Processing Technologies for their insight into DDS DACs.

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