July 17, 1997

Presynthesis chip design: A view from the top

Jim Lipman, Technical Editor

Doing the right thing at the beginning of a chip design saves effort, time, and money. Knowing what you can and can't do with available tools keeps you heading in the right direction.

When designing complex chips, eliminating false design paths is as important as correctly executing the correct design procedures. You accomplish this "weeding-out" goal with design exploration: analyzing a number of design variations and choosing the one that best meets your specifications. The earlier you can optimize your design in the design, the less effort you waste pursuing an alternative design that won't work as expected.

Ideally, you want to perform design exploration during system behavioral analysis or architectural specification. At this design level, you have some tools and techniques you can use to rapidly investigate many design variants. You then choose the best one (or best few) to work with as you continue with more detailed design. You may also choose to explore RTL-design possibilities, based on an already-analyzed and -accepted behavioral chip description. Either way, at the behavioral level or RTL, you eliminate the time and effort needed to synthesize a design to the gate level--effort you waste if the design synthesized is the wrong one.

Top-down chip design

To design complex chips, you need to follow a structured design flow (Figure 1). Your design goes through a series of steps that converts one representation, or abstraction, of the design into another. Each subsequent abstraction level adds design detail, or "intent." Figure 1 excludes the design verifications that you do at each level to ensure that your design meets original specs.

Because each subsequent design representation--functional, behavioral, register-transfer, gate, and physical--adds design information, verifying a design representation takes longer as you move through the design process. Subsequently, problems that require a major chip redesign are harder to correct the further you go into the design. Thus, the earlier in a design cycle you select the optimum design, the more time and effort you save.

High-level chip design refers to design before logic synthesis at the functional level, the behavioral level, or RTL. A functional design description contains the algorithms describing the top-level behavior of the desired system. A functional specification does not have to include any system-timing information. A behavioral description encompasses high-level operations, system behavior, and cycle-accurate time information. At this point, you have not yet defined a system architecture and implementation. You perform design exploration and architectural analyses at the behavioral level to determine an optimum architecture for design implementation. The RTL design description de-scribes system behavior in data flow between registers and other system-storage components.

An RTL description includes other control and bit-manipulation devices, such as state machines and datapaths. You may also include estimates of chip-interconnect and gate-delay information at RTL, usually with a floorplanning tool, to improve the accuracy of performance analysis. The gate-level representation describes the system as logic gates, latches, flip-flops, and other cells that indicate Boolean operations. Finally, the system's physical description is a file showing how you physically define and lay out the system on a chip.

Before logic synthesis, your design is technology-independent, meaning that system behavior does not depend on the chip's fabrication process. However, you can add technology dependency to the RTL description with floorplanning-estimated interconnect lengths and target-process information. After logic synthesis, your design is inherently technology-dependent. The logic-synthesis tool uses a library implemented in a specific process technology to generate the gate-level design description and verify the synthesized design against user-supplied timing constraints.

You design a chip at the behavioral level either textually, typically in C or C++ but sometimes in Ada, or with a block-level graphical-design tool. You then define a target architecture to implement system behavior. This architecture comprises several components linked by communication channels. The components you use include blocks such as processors, memories, and DSP cores. The communication channels define the data and control-signal flows among the various blocks.

You want to choose the right system architecture when designing at the behavioral level. If you don't have the right architecture, continuing your design to RTL and beyond may result in either a nonoptimally designed system or, in a worst-case scenario, a system that doesn't meet specifications. You can manually try different system architectures at the behavioral level, verify your choice, and decide if the architecture you have is good enough. A better decision would be to use a tool that allows you to perform behavioral-level design exploration (Table 1). This type of tool lets you input your timing constraints and a list of resources, analyzes trade-off analyses of different architectural configurations, and then outputs one or more architectures in RTL that meet system specifications. Defining a system at the behavioral level is difficult, but a number of graphical-de-sign tools can help you do the job (see box, "A GUI is worth a thousand words").

An example of a behavioral-level "what-if" tool is Mentor Graphics' Monet. Your input to Monet includes design constraints, such as clock period, the number of clock cycles, I/O protocols, and the number and type of available hardware re-sources. Monet's automatic-allocation capability lets the tool search for the best system architecture consistent with your constraints. After you select an allocation, Monet's automatic scheduler assigns operations to clock cycles and displays results on a Gantt chart (Figure 2). The scheduler handles complex operations, such as chaining, pipelining, and multicycle tasks. You can cross-probe between the Gantt chart and a behavioral design description. After allocating and scheduling, Monet partitions your design into a finite-state machine representing control logic and a datapath. During partitioning, the tool performs some critical design operations, such as resource and register sharing. You can also cross-probe between the generated state-transition and datapath-block diagrams and the behavioral specification. Finally, Monet performs behavioral synthesis by generating synthesizable RTL VHDL code. Monet runs on Unix platforms.

Visual Architect from Alta Group is another tool that combines architectural exploration with behavioral synthesis. Visual Architect requires a behavioral HDL description and your system-design constraints as inputs. The tool graphs the dependencies between area and performance for architectural alternatives. Like Monet, Visual Architect can perform automatic resource sharing, allocation, and scheduling, and you can use it for pipelined designs. Similar to Monet's output function is Visual Architect's ability to generate RTL VHDL containing a controller block and a datapath.

You get Visual Architect's input from Alta Group's SPW hardware-design system. SPW lets you convert system-behavior algorithms into the behavioral VHDL that Visual Architect uses. In SPW, you build behavioral-level block diagrams from scalar, vector, and complex mathematical-function-li-brary elements and then simulate the diagrams to verify that they implement the desired algorithms.

The separation of a behavioral-synthesis tool's output into a control module (usually a finite-state machine) and a datapath is important. Common logic-synthesis tools, such as Synopsys' Design Compiler, work well on control logic but poorly on datapath blocks. You're better off using a datapath-compilation tool to generate your design's datapath functions.

RTL design

After you analyze system alternatives at the behavioral level and synthesize an RTL description of an architecture, you can continue to analyze your design as an RTL "virtual prototype." You have not yet included technology-specific information in the design. However, tools and techniques let you estimate chip area, speed, and power based on the design's RTL description and estimated interconnect delays for a target technology. Use an EDA tool that reads the described logic blocks as RTL code and infers which logic cells you need to implement these blocks. At this point, you can input target-technology information that allows the tool to estimate block size and delays based on the inferred block configurations. This feature lets you investigate potential target processes and then choose the one that best meets your design performance and cost goals. Some tools also read clock frequency, activity levels, and output loads to give you a power-dissipation estimation for the entire design or specific blocks in the design.

If you combine an RTL-estimation tool with a floorplanner, you get more accurate estimates of design performance. A floorplanner estimates interconnect distances and resultant parasitic-induced delays between blocks. Compass' new DesignVP combines RTL estimation and floorplanning. DesignVP's technology-independent estimation engine has a floorplanner that provides an approximate layout of the RTL logic blocks. Knowing the juxtaposition of the blocks, along with the design's connectivity, enables the tool to estimate chip area and speed based on technology information for various trial-chip processes. Compass plans to include RTL power estimation this year or early next year.

Before Cadence bought HLD Systems, HLD announced a similar tool, Top-Down DP, in early 1996. Top-Down DP also combines floorplanning techniques with RTL estimation and analysis to predict chip-level characteristics, such as size, timing, and power consumption. Cadence kept Top-Down DP off the market for further development and verification and plans to release the tool this year.

After you complete your design at RTL, you need to use a logic-synthesis tool to generate a gate-level description based on a chosen target technology. This task is not turnkey; you need to develop synthesis scripts to tell the logic-synthesis tool how to split top-level chip timing information among the various RTL blocks. (Most chip designers use Synopsys' Design Compiler for this task.) This information and other synthesis guidelines are part of a synthesis script (Reference 1). Compass offers TimeSlice, a companion tool to DesignVP that automatically budgets and partitions time for each RTL block. TimeSlice performs this operation using delay estimations from DesignVP and then generates a synthesis script, including the block-time partitioning (Figure 3).

Behavioral-level-design review

Mike O'Neill, manager of platform and design-center engineering at IBM Microelectronics (Essex Junction, VT), summarizes required high-level chip-modeling tasks. He asserts that first, you want to verify system protocols at the system level. This verification is more difficult to do down the design path. Although you have verification suites available from many vendors for common communication protocols, such as USB and PCI, most system designs need a customized protocol-verification procedure.

High-level performance modeling is also important. At this point, you investigate hardware/software trade-offs to meet system specifications for cost, time to market, and design flexibility. "How deep a queue buffer do I need?" and "How many execution units does the system require?" are examples of questions you ask yourself during performance modeling.

At the behavioral level, you need to determine your hardware options. Architectural exploration can help you make design decisions, such as using a general-purpose or a specialized processor, the size of cache memory needed, and whether you require a coprocessor. Coupled to architectural exploration is a need for hardware/software cosimulation to help you evaluate the performance of system configurations.

O'Neill also feels that a need exists for more application- or domain-specific high-level design tools. Such tools would do a better job of implementing known, good algorithms for specific types of systems, such as wireless communications. Alta Group has moved in this direction with its Envision (multimedia), EnWave (wireless), and BONeS ATM VE (ATM) products.

Where are the weak links in the current behavioral-level design tools and methodology? Weaknesses exist first in automatic hardware/software partitioning and second in tool integration for a complete set of system-on-a-chip design tasks. The tool integration is particularly troublesome because it requires designers to mix and match vendor and internal tools to cover all high-level design jobs.

References

1. Lipman, Jim, "Just what are synthesis scripts?" EDN, Sept 2, 1996, pg 42.

2. Jain, Prem, "Bridging the Gap between ASIC Behavioral and Structural Design," Proceedings of the Eighth Annual ASIC Conference and Exhibit, Sept 18 to 22, 1995, pg 93.

3. Sjoholm, Stefan, and Lennart Lindh, VHDL for Designers, Prentice Hall, London, 1997.

4. Ussery, Cary, "VHDL: Is the Phoenix Burning?" VHDL: The Next 10 Years, VIUF Spring 1997 Conference Proceedings, March 31 to April 3, 1997, pg 29.

5. Ussery, Cary, Kathy McKinley, et al, "HDL and Integrating System-Level Simulation Technologies," IVC '97 Proceedings, March 31 to April 3, 1997, pg 91.

6. Lipman, Jim, "The hard facts about soft cores," EDN, Sept 2, 1996, pg 38.

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