July 17, 1997

Low-voltage differential-signaling ICs provide speed, impedance match

Bill Travis, Senior Technical Editor

ICs targeting LVDS use minimal power and offer great speed performance and noise immunity.

Low-voltage differential signaling (LVDS) offers a way to achieve blazing data-transfer rates with minimal power consumption and high noise immunity. To achieve these speeds, some recent ICs provide low-cost drive, reception, and termination in LVDS-based systems. These devices accommodate high data rates and consume less power than single-ended approaches that yield equal data rates (Table 1).

The rationale for creating LVDS was that single-ended SCSI had reached its limits with the Ultra (Fast-20) standard. Receiver thresholds are 1 to 1.9V, working with a cable impedance of approximately 60 ohms. Because the line charges to 3V and sinks to 0.2V, the required step size to guarantee incident-wave switching is 2V. So, the minimum drive current is 35 mA in each direction. The minimum sink current for single-ended SCSI is 48 mA; because of drive requirements, you have to increase this current to 70 mA. The negation drivers have to supply 30 mA minimum. These currents are too high to allow integrating 27 lines in a controller chip.

Various standards exist for describing the driver, receiver, and termination considerations for using LVDS (Reference 1). (You can implement LVDS in systems allowing data rates as high as 2.5 Gbps (Reference 2).) The EIA-644 standard is a point-to-point LVDS norm. It relies on receivers to provide fail-safe line conditions; it provides no common-mode termination for multipoint buses, on which it's possible to have two or more drivers simultaneously driving the bus. The resulting common-mode currents that develop between the drivers produce large bus voltages that can turn off the drivers.

The new SPI-2 (Ultra-2 and -3 SCSI) standard defines high-density connectors and terminal-power distribution. This norm replaces SCSI-3, SPI, and Fast-20. SPI-2 defines the next speed increments: Ultra-2 (Fast-40) and Ultra-3 (Fast-80). Ultra-2 transfers data at speeds as high as 80 Mbytes/sec; Ultra-3, as high as 160 Mbytes/sec. Reference 3 describes the technical requirements of Ultra-2 SCSI. A new connection system allows four SCSI differential-line connectors on a single-slot PCI card (Reference 4).

A bewildering variety of nomenclature for SCSI and LVDS standards gives rise to confusion (Table 2). Fast-40, for example, is now called Ultra-2 SCSI. Maximum cable lengths and the number of devices that you can use with different standards vary (Table 3).

One thing that is clear, however, is that termination is important for LVDS devices. If you're an Arnold Schwarzenegger fan, you know that an effective terminator can change the course of events. That tenet is true, too, in LVDS interconnect systems. LVDS lines need terminators to provide the required voltage bias and the correct characteristic impedance. In the latest SCSI specs, that voltage bias is 1.25V, and the termination impedance is 100 to 110 ohms. Driver and receiver chips are designed to operate with the assertion and negation currents and voltage thresholds commensurate with those termination parameters. Figure 1 shows a differential line with a driver, a receiver, and terminators attached.

Several recent LVDS-termination chips work with a variety of driver and receiver ICs to satisfy the SCSI LVDS specs. The UCC5630 from Unitrode, for example, is a multimode device--providing nine single-ended or differential lines of termination (Figure 2). In LVDS configurations, the switches are down, providing two 52 ohms resistors in series to yield 104 ohms termination impedance on the differential line. Another switch selects 1.25V common-mode bias voltage for the line.

The UCC5630 has an automatic bus-sense function that determines if the line is single-ended or differential and then switches the device to the proper mode. If the IC senses a high-voltage differential bus, it shuts down. The UCC5630 has a 3-pF maximum output capacitance and consumes only 100 µA during disconnect. A differential-sense (Diffsense) pin supplies 1.3V to the Diffsense pin of an LVDS driver/receiver on the line, thereby enabling the device.

Two terminators from Linfinity also handle nine LVDS lines each. The LX5244 operates only with Ultra-2 systems (Figure 3). The Diffsense pin ties to the Diffsense input of the corresponding LVDS transceiver. If Diffsense is high, the LX5244 goes into a high-impedance state, indicating a high-voltage differential device on the line. If Diffsense is low, the LX5244 again assumes a high-impedance state, this time indicating a single-ended device on the line. A master/slave function, also present in the Unitrode terminator, enables the use of an external master device.

Linfinity's LX5240 multimode terminator has all the functions of the LX5244 and can also operate with Fast SCSI, Fast Wide SCSI, and Ultra SCSI lines. The LX5244 and LX5240 spec 2- and 3-pF maximum output capacitance, respectively, in disabled mode.

Two terminators from Motorola also target SCSI applications. The 18-line MCCS142236 and MCCS142238 and the nine-line MCCS142237 terminators provide switchable 110 ohms termination resistors and offer full active-negation support for SCSI LVDS lines.

Drive, receive, transceive

You have a wide choice of drivers and receivers for LVDS lines (Table 1). Some are general-purpose devices, such as Linear Technology's LTC1520 quad line receiver (Figure 4), which translates LVDS data into CMOS/TTL-output levels. The device's claim to fame lies in the inherent low skew figures: 500 psec (typical) between high- and low-switching points and 400 psec (typical) channel to channel. Propagation delay in the LTC1520 is 18 nsec, with a tightly specified ±3-nsec variance. An additional skew spec is package-to-package skew: 1.5 nsec (typical). The receiver boasts an exceptionally high ±10V permissible dc level at the inputs and has rail-to-rail common-mode input range. The hot-swap-capable IC presents 18-kilohms minimum input impedance to the LVDS lines. The LTC1520 works as a hot-pluggable backplane receiver.

Other drivers and receivers are application-specific, such as National Semiconductor's flat-panel devices. National is putting a lot of eggs in the LVDS basket. The dual-channel DS36C200 transceiver and the quad DS90-LV031/032 driver/receiver siblings, for example, offer data rates exceeding 100 Mbps and translate between EIA-644 LVDS and CMOS/TTL levels. The 031 and 032 consume less than 40-mA supply current at top speed, yielding less than 132-mW package dissipation. Differential skew and propagation delay for the 031 and 032 are typically 200 psec and 2.6 nsec, respectively.

National's DS90CF364/383/384 receivers and transmitter also target flat-panel displays, specifically LCDs. Figure 5 shows a typical connection in a notebook computer. The devices accommodate cables as long as 5m at data rates of 455 Mbps. They typically work with the family of video-processing chips from Genesis Microchip to provide video scaling and line doubling in noninterlaced applications. In addition to the representative ICs in Table 1, National offers several other families of LVDS drivers and receivers that operate from 5V supplies.

Some other National LVDS chips, dubbed "channel link," consist of driv-er/receiver pairs that convert CMOS/TTL data to LVDS levels and vice versa. The DS90CR211/212 (Figure 6) translates between 21 bits of CMOS/TTL data and three streams of LVDS data. The triple-LVDS-path 211/212 pair provides data rates to 280 Mbps/channel for a composite rate of 840 Mbps (105 Mbytes/sec). The quad-LVDS-path 281/282 also handles data rates to 280 Mbps, yielding a composite rate of 1.12 Gbps (140 Mbytes/sec). In power-down mode, the channel-link devices consume less than 10-µA supply current. The chips contain a phase-locked clock for transmission in parallel with the LVDS stream.

An application-specific LVDS chip from Maxim Integrated Products targets synchronous-digital-hierarchy/synchronous-optical-network (SDH/SONET) and asynchronous-transfer-mode (ATM)/SONET applications. The MAX3681 is a 1-to-4 deserializer that converts 655-Mbps, PECL-level serial data to 4-bit-wide, 155-Mbps parallel LVDS signals. The 3.3V device accepts a differential PECL-level clock and provides an LVDS sychronization input that enables data realignment and reframing.

Addressing the PCI bus

A host-adapter board from Symbios Logic provides a PCI-to-Wide Ultra-2 SCSI. The SYM8951U adapter incorporates the company's SYM53C895 PCI-to-Ultra2 SCSI I/O processor in an implementation that Symbios calls "LVDlink." The device accommodates as many as 16 LVDS devices on a wide LVDS SCSI bus, using the cables and connectors defined in the Ultra-2 SCSI standard. The chip switches between single-ended and LVDS modes. It contains an 816-byte DMA FIFO buffer and supports 512-byte bursts across the PCI bus. An on-chip clock quadrupler derives an internal 160-MHz clock from an external 40-MHz oscillator.

The host-adapter board uses PCI's plug-and-play features and the built-in utilities of SCAM (SCSI configured automatically). The board stores the SCSI-bus and device configurations in an onboard flash BIOS, thereby eliminating the need for jumpers, switches, or DMA or interrupt-request allocations. The adapter comes with SDMS (SCSI-device management software), which provides the SCAM, SCSI-bus, and device-configuration utilities. It operates with all major operating systems, including DOS, Windows 3.1x/NT, Novell Netware, SCO Unix Open Server, Unixware, and OS/2.

LVDS technology provides an easy and effective way (indeed, maybe the only way) to migrate to the blazingly fast data rates of emerging digital systems. Differential signaling provides high noise immunity, inexpensive twisted-pair cabling, and tightly controlled impedance parameters.

References

1. Kempainen, Stephen, and John Goldie, "Low-voltage differential signaling yields megatransfers per second with milliwatts of power," EDN, Sept 2, 1996, pg 119.

2. Travis, Bill, "Fiber vs copper: Sometimes it's not an easy choice," EDN, Nov 21, 1996, pg 46.

3. Aloisi, Paul, "LVD SCSI--What is LVD? & Design Guide for LVD," Application Note, Unitrode Integrated Circuits, May 1996.

4. Travis, Bill, "LVDS: power-miser angel, interconnect demon," EDN, June 19, 1997, pg 85.

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