August 15, 1997

SP-L modulator uses single-speed bit clock

Massimo Garavaglia, Robecchetto con Induno, Italy

Split-level (SP-L), or Manchester, encoding is a common modulation scheme in data transmission (Figure 1). SP-L is popular because bit-clock extraction at the receiving end is easy, and the modulator circuit is simple to implement--simple, but not trivial, because the output of this classic circuit suffers from severe spikes during data transitions (Figure 2). A different circuit eliminates the spiking problem (Figure 3). This circuit resamples data after stabilization, but to do so, it needs a double-speed clock. This need can be as annoying as having spikes.

Another circuit approach provides a clean output and uses only a single-speed (symmetrical) bit clock. After power-up, flip-flops FF₁, FF₂, and FF₃ are in their preset state. Provided that NRZ_DATA is valid, FF₁ samples the BIT_CLK falling edge. This action provides the first half of the SPL_DATA (FF₁'s output): high if NRZ_DATA is high, low if NRZ_DATA is low. When BIT_CLK goes high, only one of the two other flip-flops (FF₂ or FF₃) can sample a zero and drop its Q output, while the other one remains in its preset state. If SPL_DATA is low, FF₂'s Q output drops, presetting FF₁ and causing SPL_DATA to go high (second half of an SP-L-encoded zero). Conversely, if SPL_DATA is high, FF₁'s Q output drops, clearing FF₁ and forcing SPL_DATA low (second half of an SP-L-encode one). The result is that FF₁ looks like a D flip-flop on the clock's falling edge and a T flip-flop on the clock's rising edge (Figure 5). Note that the inverter between FF₁'s Q and FF₃'s PR is essential; during initialization (PWR_ON_RST low), the system could hang up if FF₃ starts in its cleared state. (DI #2064)

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