September 1, 1997

NEW IC PACKAGES really pack in the leads

JIM LIPMAN, TECHNICAL EDITOR

High-density ICs need high-lead-count packages to successfully interface with the rest of your system. But beware: Centipedelike chip packages can cause design problems. Knowing the features--and drawbacks--of these packages can help you design your high-lead-count chips and high-performance boards.

Million-plus-gate chip designs for bus-oriented electronic systems can require hundreds or even thousands of package connections to get signals and power on and off the chip. Whether you design chips or boards, high-lead-count packages give you problems you have to solve. To select the right package or to design for a selected package, you need to consider many factors, including electrical performance, power dissipation, testability, and onboard manufacturability.

The problems associated with this new breed of chip package are forcing IC designers to consider the chip and package as one design entity, rather than as separate design objects. If you're a pc-board designer, high-complexity chips coupled with evolving high-lead-count packages are creating new problems for layout, component placement, and board assembly.

The future of chip packaging is promising. New and resurrected packages, along with innovative technologies, are leading the way to IC packages with more than 2000 I/O leads and 40 to 50W dissipation. EDA vendors are also supporting package advancements with tools that allow you to analyze chip-package impact on circuit timing, signal integrity, heat dissipation, and electromagnetic radiation. Unde rstanding the benefits and limitations of high-lead-count packages, along with the materials and software tools moving these packages into mainstream system design, will help you develop your systems.

Why packages are important

On a simplistic level, chip packages have only to interface the chip's circuitry to the rest of the system and to protect the chip from its environment. In reality, IC packages must satisfy electrical, mechanical, thermal, and reliability constraints to successfully perform the chip-system interface.

The electrical chip-to-board interface, via the package, has to satisfy many constraints. Foremost is propagation delay: the time required to get signals on and off the chip. In addition to meeting these delays, the signals must also meet signal-integrity requirements, putting limitations on package-lead cross-coupling and off-chip impedances. For high-speed signals, you must have matched loading impedances to and from the chip, similar to the situation you face terminating cable connectors in a high-speed electronic system. Package-lead resistance and inductance can result in excessive power and ground degradation, especially at high clock rates. The resultant V_DD droop and ground bounce degrade signal integrity and reduce chip speed; under certain conditions, your chip may even fail.

Mechanically, a chip's package joins the I/Os, power, and ground connections to the pc board. The chip-to-substrate level, Level 1, and the substrate-to-board level, Level 2, provide the connections. For chips with hundreds of I/O pins, providing these connections is a complex task, made harder by the need to join power and ground to the chip using dozens of connections. A typical high-speed chip may require one power connection (V_DD or ground) for every three or four I/O leads. You need multiple V_DD and ground connections to lower power and ground resistance and inductance and to maintain power and ground integrity. Having so many chip-to-board connections also makes it difficult to perform board layout and onboard chip testing.

A chip's package plays a major role in power dissipation. With high-speed mPs dissipating 30 to 40W or more, the package must have low thermal resistance and be constructed to maximize the effectiveness of external heat-dissipation mechanisms, such as forced airflow and heat sinks. Maintaining package reliability with increasing lead counts is also difficult. The package must withstand heat-induced expansion of its components without failing. (In other words, it must be able to tolerate the thermal-expansion mismatches of its constituent materials.) The problem of thermal mismatches also exists at the chip-package and package-board interfaces. In addition, as the number of package leads increases, the problem of guaranteeing both Level 1 and Level 2 connectivity integrity also increases.

A few years ago, the development of the pin-grid array (PGA) partially solved the problem of getting more chip connections onto a given package footprint. PGAs, with their package-to-board interconnect array configuration, offer a higher onboard lead density than their peripheral-interconnect predecessors, quad flatpacks. However, PGAs still entail a peripheral chip-to-package-substrate interconnection scheme with wire bonding, leading to complex package construction to bring peripheral chip-pad connections to array-board connections. In addition, you mount PGAs with a through-hole method--through holes on a pc board. The introduction of the ball-grid array (BGA) package was a giant step in the right direction for less expensive, higher lead-count chip packaging that you could surface-mount on a pc board.

Regular plastic BGA (PBGA) packages typically provide as many as 500 connections from chip to board. The package substrate is single-core, with only two surfaces of metallization--ground plane and signal routing. Thermal mismatches between the chip and package substrate constrain the substrate to around 35 mm per side (see box, "Thermal mismatches put the heat on package development"). This constraint, coupled with a ball pitch of 1.27 mm, set by pc-board routing limitations, limits package lead count. You mount the chip metal-side up, with wire bonds connecting the chip's peripheral pads to metal areas on top of the package's substrate (Figure 1a). Connections continue through metal-filled vias in the core to metal balls on the bottom of the PBGA. You then surface-mount these balls onto the pc board.

Many ASIC and chip companies have developed "improved" versions of PBGA packages. The enhanced plastic ball-grid array (E-PBGA) package from LSI Logic is an example of a thermally enhanced BGA (Figure 1b). The package has two cores, resulting in four substrate-routing layers: one each for power and ground and two dedicated to signal paths. The additional core and metal-routing layers result in more controllable package-lead impedances for high-speed designs and lower lead parasitics. Additional metal-filled vias from the bottom of the chip through the substrate to balls in the central area on the package's bottom are soldered to copper regions on the board. These extra metal "pipes" provide additional chip heat dissipation, allowing the E-PBGA substrate to be as large as 45 mm. The larger substrate provides as many as 731 leads without increasing the 1.27-mm ball pitch.

PBGA packages usually have as many as four rows of balls around the periphery of the package's base, and some companies are developing packages with five rows of balls. The E-PBGA package provides as many as 61/2 rows of balls. LSI Logic indicates that the additional rows of balls are preferable to a tighter ball pitch for higher lead counts for the company's target customers--computer- and network-product developers.

A variation of LSI's E-PBGA package, which will be available by year-end, uses staggered bonding pads on the chip. The bonding pitch remains the same as for single-row bonding pads, 21/2 mils, but the pad staggering decreases effective pad pitch to 2 mils. Staggered bonding raises the upper E-PBGA lead count to approximately 800. Staggering the leads also reduces bond-lead length. ProLinx has shown that a 348-lead die with staggered bonding pads at a 6-mil pad width/3-mil pad spacing has a maximum wire length approximately half that of a die with nonstaggered pads at a tighter 4-mil pad width/3-mil pad spacing.

For large-pin-count packages with large chips, IBM uses a ceramic-BGA package variation, a ceramic column-grid array (CCGA). CCGAs substitute solder columns for solder balls to connect package substrates and boards (Figure 2). The solder columns measure 20 to 22.5 mils in diameter and 50 to 87 mils high. Solder columns provide better strain relief than solder balls, because minimum ball-spacing re-quirements limit ball height. The increased height of a column over a ball increases package reliability, particularly in situations with excessive temperature cycling or limited cooling.

Flip-chip

Changing from chip-to-substrate wire bonding to a flip-chip configuration provides a large jump in lead count (Figure 3). The flip-chip BGA (FC-BGA) uses an array of bumps on the chip in place of peripheral bonding pads and bonding wires. This package produces lead counts higher than 1500. An additional benefit of bumps over bonding wires is the decrease of chip-to-pc-board inductance, which results in lower attenuation of high-frequency and fast rise- and fall-time signals. Flip-chip structures also allow you to make ground and power connections to internal points on a chip, resulting in a "stiffer" power grid and better chip performance.

One of the first commercially available flip-chip technologies was IBM's controlled-collapse chip connection (C4), which the company still uses in ceramic BGA packages. C4-based BGA packages can handle a substrate as large as 42.5 mm, which, at a 1.27-mm pitch, results in a maximum lead count of 1088. IBM is also working on multilayer-ceramic BGA packages with a 1-mm ball pitch, which would increase lead count to around 1650. Multiple-layer substrates give you more dedicated power planes in the package's substrate, reducing signal crosstalk and power- and ground-lead inductance.

LSI Logic began its FC-BGA development with a ceramic substrate. The ceramic is a good thermal match to the silicon chip but a poor thermal match to the pc board. The substrate-to-board thermal mismatch limits the substrate size to 35 mm on a side, resulting in a maximum of 1089 leads. Replacing the ceramic substrate with a laminated organic (plastic) substrate substantially improves substrate-to-board thermal matching, allowing substrates to be as large as 45 mm on a side and lead count to increase to 1503 (with a 1.27-mm ball pitch). LSI will qualify the organic FC-BGA in the second half of the year.

Some chip companies use "peripheral redistribution" to connect a chip's peripheral bonding pads to an on-chip BGA. Peripheral redistribution uses a dedicated metal layer to route peripheral bonding slots to solder balls at array locations across the chip. For example, if you use a five-metal-layer process for circuit interconnection and you want to put the chip in an FC-BGA package, either you lose a metal interconnect layer, or the silicon vendor uses a sixth metal layer for the package. LSI is developing chip-layout schemes that will eliminate the need for a dedicated FC-BGA metal layer.

With C4 flip-chip technology, you can directly connect an array pattern of bumps on the substrate to an array pad grid on the chip. If you want to convert a chip designed for wire bonding to C4, you use peripheral redistribution to put array connections on the chip. Chips targeting C4-based packages from the outset include design-for-array connections and need no peripheral redistribution and its dedicated metal layer.

One final notable BGA variation is the tape BGA (TBGA), based on a section of flexible polyimide tape. The TBGA process mounts solder balls and the die onto the tape and encapsulates the combination in epoxy. You can use TBGA-package technology for both wire-bond and C4 (ball-bond) chips with more than 700 leads. The thin, lightweight package is well-suited to portable applications and is a good thermal match to a pc board. These features result in high chip-to-board reliability.

Currently, pc-board routing places a major limitation on what IC-package manufacturers can do (References 1 and 2). Package developers need to constrain new packages to provide inexpensive mounting on and connection to pc boards. Packages with higher lead density or tight lead pitch require either finer--yet expensive--board metal layout or--also expensive--boards with additional layers. John Shotsky, Orcad's (Beaverton, OR) product marketing manager for pc-board-layout tools, correlates board layers with the number of rows of balls on a BGA package. The more ball rows, the more pc-board layers needed to fan out the package connections to other components on the board. In addition to the increased board-layout complexity, increased pc-board layers also have problems with layer stack-up, which results in impedance-design problems for high-speed chips.

Shotsky also equates the influx of high-pin-count packages with the demise of gridded board routers for high-complexity boards. Because chip packages have different lead pitches, many designers use "smart" gridless or shape-based routers for boards with mixed-pitch packages. Companies such as Cadence (San Jose, CA) and Zuken-Redac (Santa Clara, CA), as well as by Orcad and other vendors of pc-board-design tools, offer these smart routers.

BGA packages present some unique test problems after board mounting with respect to ball integrity. Ball deformity or voids may lead to reliability problems down the road. However, chip manufacturers handle this problem with X-ray scanning, which somewhat easily pinpoints such problems. The cost of X-ray equipment is high. Many chip manufacturers, rather than purchasing this equipment, obtain screening services from third-party vendors. Screening packaged-chip parts before pc-board mounting is another problem because of the high number of BGA-package leads. This screening requires sophisticated test equipment and, usually, complex test procedures. Both the equipment and test development are expensive. In addition, test-development time can potentially be a gating item in sy stem development; make sure that you account for this time before beginning your system design.

Where do you go from here?

Emerging companies with innovative technologies are attacking the cost and performance issues associated with high-performance, high-lead-count packages. Tessera has made its presence known in the chip-scale package (CSP) arena by licensing its mBGA technology to many chip manufacturers, including Intel (Folsom, CA) and Texas Instruments (Dallas), and IC-packaging subcontractors, including Amkor (Chandler, AZ) (see box, "Where do CSPs fit in?"). Usable with flip-chip or wire-bonded chips, mBGA-based packages have an elastomer pad and flexible film separating the chip from the package substrate (Figure 4). These layers decouple the silicon and substrate, alleviating the mismatch in thermal-expansion coefficients between both materials. Chip pads connect to bumps on the substrate with conductive traces on the flexible film. Tessera's mBGA packages have their solder balls on grid pitches of 1, 0.75, and 0.5 mm. Because most pc-board assembly accommodates BGA-package ball pitches of 1.27 and 1 mm, widespread use of high-pin-count, mBGA-based CSPs won't occur for a few years (Reference 3).

Some companies have developed technology to enhance fine-pitch and fine-line capability on package substrates or pc boards. Both ProLinx Labs and Merix eliminate the need for drilled vias, a costly (for very fine holes) and space-inefficient process for package substrates or pc boards. ProLinx's microfilled-via (MfVia) process addresses BGA-substrate fabrication, substituting a photolithography-defined dielectric process for mechanical drilling to create vias interconnecting layers of a multilayer substrate (Figure 5a). The company has already proven the process on the ViperBGA package with as many as 696 leads.

MfVia technology is less expensive and produces smaller vias for use with thinner substrate traces. Furthermore, MfVia lets you stack vias and substrate pads, a space-saving feature that traditional BGA-package technology lacks (Figure 5b). MfVia-based packages currently have 8- to 9-mil vias with 12-mil-diameter metallization over the vias. ProLinx plans to reduce these sizes to 5-mil vias and 7-mil metallization next year. Also next year, ProLinx will accept not only wire-bond, but also flip-chip dice.

For pc boards, Merix uses Dycostrate plasma etching in place of drilling. Following via definition using photolithographic methods, Dycostrate provides a pc-board via diameter of 3 mils, well below drilled-hole diameters of 6 to 9 mils. You get a substantial reduction in board-manufacturing cost because one or thousands of holes use the same via definition and etch process. You can also put the small vias into a pc board's mounting pad, similar to the stacked via-and-pad arrangement made possible by MfVia processing for package substrates. Having the via under the pad eliminates almost all of the trace stub you normally use to connect the pad to the metal around the via. This elimination of almost all of the stub reduces the parasitic inductance associated with the via and its metallization by more than an order of magnitude and virtually eliminates stub capacitance to ground.

References

1. Newberry, William, "Design Techniques for Ball Grid Arrays," PCB Design Conference West Proceedings, March 1997, pg 349.
2. Trefethen, Dean, "Introduction to Design With Ball Grid Arrays," PCB Design Conference West Proceedings, March 1997, pg 131.
3. Bauer, Charles, "The Future of BGA," Advanced Packaging, January/February 1997, pg 8.
4. DeJule, Ruth, "High Pincount Packaging," Semiconductor International, July 1997, pg 139.
5. Ray, SK, H Quinones, S Iruvanti, E Atwood, and L Walls, "Ceramic Column Grid Array (CCGA) Module for a High Performance Workstation Application," Electronic Component Technology Conference (ECTC) Proceedings, May 1997, pg 319.

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