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September 25, 1997 16-BIT The register-based H8 series includes the H8/300L and H8/300 8-bit µCs with 16-bit instruction words and 16-bit ALUs and the H8/300H and new H8S 16-bit µCs with 32-bit ALUs. All future development in this family will be along the H8S line. Each series is upward-compatible. The H8 has eight general-purpose registers, a program counter, and PSW registers. The H8S further adds single-cycle execution of the common standard logic instructions, a multiply-accumulate (MAC) unit in the H8S/2655 series, and extended-control registers. These registers are not part of a register-banking or third addressing-space scheme. The 8-bit 300L and 300 chips treat registers as 8 or 16 bits, referencing registers as a set of eight 16-bit registers or 16 8-bit registers. The 300H and H8S registers are accessible as 8, 16, or 32 bits. You can dynamically resize the 8- or 16-bit-wide external datapath. H8 devices have a fixed instruction word with a supplemental word for additional data and a RISC-like load/store architecture. All CPUs have a unified address space. The address space includes a 128-byte register file to access on-chip peripherals as memory-mapped I/O. Power management: In sleep mode, CPU operation halts, register and RAM contents remain unchanged, and peripherals continue to function. In standby, CPU and peripheral operations halt, and registers and RAM contents remain unchanged. H8S devices can individually control the operation of each of their peripherals. In addition, the H8/300L series and some of the H8S series devices support 32-kHz subclock operation but require an external switching circuit. Special instructions: H8 devices are code-compatible and all share an instruction base with 55 to 69 instructions, mnemonics, and basic addressing philosophy. Bit-manipulation instructions include set, clear, test, and various logic operations. Math functions include add, subtract, increment, decrement, decimal adjust, multiply, divide, and extend sign; the H8S/2655 series includes a MAC instruction. H8 devices also perform block moves. Special peripherals: Depending on the device series, Hitachi offers an LCD drive; a VFD drive for small displays, such as a stereo-system display; a keyboard-interface controller that performs keyboard scan; a DRAM refresh; and a DMA controller. In addition, several H8 devices come with on-chip, 12V flash memory. Development tools: Hitachi and third parties offer development tools. The E3000, E6000, and E7000 emulator development platforms from Hitachi support various H8/300L, 300, 300H, and H8S/2000 series on both SPARC and PC environments. Hitachi also offers evaluation kits for product evaluation, benchmarking, and development. These packages typically include a compiler suite, a development/debugger environment, a development board, and supporting documentation and examples. IAR Systems (San Francisco), Cygnus (Mountain View, CA), and Green Hills Software (Santa Barbara, CA) offer compiler support. Hewlett-Packard (Colorado Springs, CO) and Orion Instruments (Sunnyvale, CA) offer emulators. Data I/O (Redmond, WA), Yamaichi (San Jose, CA), and others provide programmer and socket support. Second sources: There are no second sources for the H8 series.
The main core of the CPU comprises a four-stage pipeline: fetch, decode, execute, and write back; a one-cycle barrel shifter; and a fast-multiply/divide-function unit. Pipeline stages clock in 100-nsec cycles, so most of the µC's 240 instructions appear to execute in one cycle. Instruction latency is four cycles, or 400 nsec. A peripheral-event controller (PEC) performs byte or word transfers between peripherals and memory in one cycle without interrupting the CPU. The CPU uses code segmentation and data paging to address as many as 256 kbytes (the 166) or 16 Mbytes (165/167) of the unified instruction-data memory space. The external-memory bus controller has four programmable modes, chip selects, and a wait-state generator. You can partition physical memory into multiple segments and five address ranges (the 166 has only two), each having a different type of memory with or without wait states. You can program a hold/acknowledge mechanism on the external bus, so that external devices take control for critical data transfers. A system stack of as much as 512 bytes stores temporary data. Instructions are 2 or 4 bytes long. The µCs can handle a 4-byte instruction fetch from on-chip ROM in one 100-nsec stage. A single fetch gets an entire instruction. However, because the 16-bit external bus permits only a single-word access, off-chip program accesses suffer at least a one-cycle stall for a 4-byte instruction. The 166/165/167 µCs cache branch-target instructions and use them to supply the next iteration of a branch, allowing execution without pipeline stalls. First-pass loop branches pay a single-cycle penalty. Nonaligned, double-word, branch-target instructions also pay a one-cycle penalty. Power management: Idle mode shuts off the CPU clock, leaving all integrated peripherals active. Power-down mode disables the clock input. Any reset or interrupt request can terminate idle mode; only a hardware reset can terminate power-down. Special instructions: Bit-manipulation instructions include bit set, clear, move, and various logical operations. Math instructions are add, subtract, 16×16-bit multiply and divide, and 32×316-bit divide. The µCs can perform as many as 15 shifts or rotates in one instruction cycle. Every jump has 16 conditions. Second sources: The ST10 devices from SGS-Thomson are 166-compatible.
The core architecture includes the processor-execution and the bus-interface units, which asynchronously communicate to the outside world via an 8- or a 16-bit multiplexed system bus. Some AMD 186s support a nonmultiplexed address/data bus, which frees the processor to run at nearly twice the speed of standard 80C186 controllers--without an increase in external memory speed requirements. The unit uses a 6-byte instruction-prefetch queue to hold pending instructions fetched by the bus-interface unit. All memory addressing is base-relative, which is a help for embedded code because you can easily change the address base to relocate code. Address segmentation lets the CPU address as much as 1 Mbyte of memory. The 80186 adds a 16-bit offset supporting a 64-kbyte segment to the segment base address (the segment register shifts 4 bits left) to attain a 20-bit address and 1 Mbyte of addressing capability. The CPU bus supports multiprocessing. The local-bus controller deploys a HOLD/HLDA (hold/hold-acknowledge) protocol that enables another bus master, typically DMA, to take over the common system bus. Power management: Only the Intel versions of the 186 have idle and power-down power-saving modes. Idle shuts off the CPU clock, leaving all integrated peripherals active. Power-down disables the clock input. In addition, you can programmably divide the internal-processor frequency by a factor as high as 256 and slow all internal logic. Special instructions: Math instructions include signed and unsigned multiply and divide, add, subtract, BCD, and decimal adjust. The 80x86 performs a register-exchange, repeat prefix for repeating string operations (execute until zero or equal). Wait examines the test pin and suspends instruction execution if the pin is high. Special on-chip peripherals: AMD's 186ER is the only 186 to support 32 kbytes of on-chip RAM. The 186ED integrates a DRAM controller. Development tools: The x86 architecture has more development tools than any other architecture. These tools include emulators, compilers, assemblers, simulators, debuggers, and more. AMD provides demonstration and evaluation kits for AMD-specific devices. The company also sponsors a third-party FusionE86 partner program, comprising a network of tool vendors that offer industry-standard x86 hardware and software. Second sources: Second sources for the 8086 are Fujitsu (San Jose, CA), Temic (Santa Clara, CA), Siemens, and Oki. Second sources for the 80186 are AMD and Siemens. (Chips and Technologies (San Jose, CA), NEC, Sharp (Mahwah, NJ), and Vadem (San Jose, CA) make code-compatible µPs and µCs.) Harris Semiconductor (Melbourne, FL) is the second source for the 80286. The MCS-96 microcontroller product family comprises the event-processor array (EPA), the high-speed I/O (HSIO), and the motion-control (MC) lines. The EPA line comprises the KR, NT, NP, and NU devices. The HSIO line consists of the KB, KC, and KD devices. The motion-control line, which comprises the MC, MD, and MH devices, supports motor-control applications. Intel's MCS-296 microcontroller is the most recent addition to the 196 family. The 80296SA improves performance over the 8xC196NP and 8xC196NU controllers and maintains binary-code compatibility. You can drop it into an 8xC196NP/NU socket. The 80296SA exhibits improved math performance over previous architectures, making it suitable for embedded digital-signal processing and feedback-control systems. The 80296SA uses the same peripherals as the 8xC196NP/NU. Intel built the MCS-196 around 256 RAM-based registers; most of the registers can function as a result accumulator. The first 23 of these registers are special-function registers (SFR) to control the on-chip peripherals. Some family members have on-chip RAM that can hold small, critical dynamic code or data and can implement register windowing. Register windowing can substitute a block in RAM for a block of registers. The MCS-96 maps accesses to a register in the window block to the windowed block in RAM. This technique eases fast context switches by shifting the register window to another block. Block sizes can be programmed for 32, 64, or 128 bytes. The MCS-196 has approximately 220 instructions comprising one, two, or three operands. Some instructions are more than one word. Register windowing helps minimize instruction size by letting 8 bits address a register in a movable window. The address space of the MCS-96 works with both 8- and 16-bit external data buses. The external bus multiplexes data and address lines, so a buffer must hold the address stable during data transfers. However, the 8xC196NP has a demultiplexed external bus. An on-chip memory controller lets the MCS-96 use a range of memory types and speeds. External-memory wait states are programmable. Most 196/296 devices can access as much as 64 kbytes of memory; some versions can extend this memory range to 16 Mbytes. The CPU can use autoprogramming to program the internal EPROM with an 8-bit external data interface. All MCS-96 chips except the Mx have a full-duplex serial port, which the 196Kx uses to program the µC. Power management: Idle mode shuts off the CPU clock, leaving all integrated peripherals active. Power-down mode disables the clock input. Special instructions: Math instructions include add, subtract, multiply, divide, and multiply-accumulate (MAC). Special instructions include a block move of data; indirect-autoincrement addressing; and a table-indexed jump, which lets you jump via a table value. Special on-chip peripherals: The MCS-196's EPA contains two 16-bit timers and 10 capture-and-compare modules. An event interrupt generates edges, starts A/D conversions, and resets timers. The HSIO structure has as many as four input and six output timer/counter-driven lines. The 196 also supports a peripheral-transaction server that is a microcoded, hardware-interrupt handler for responding to data transfers, starting an A/D conversion, and similar tasks. The 8xC196 bus controller features programmable wait-state generation, 8- or 16-bit bus width, and support for a HOLD/HLDA (hold/hold-acknowledge) protocol for multiprocessor systems. The 8xC196NP and NU have a dynamically selectable multiplexed/ demultiplexed bus and a chip-select unit. The 8xC196NU and 80296SA include a PLL. With the PLL, an external clock drives the device at one-half or one-fourth the maximum internal clock frequency. Therefore, a 196/296 system supports a lower frequency external clock or oscillators while maintaining the maximum internal operating frequency. The 296's chip-select unit allows you to window some external-memory locations for direct addressing, an improvement over the 196. Development tools: Intel and many third-party vendors provide tools for the 196 and 296. Intel's evaluation boards provide a low-cost hardware platform for code execution, debugging, and performance analysis. You can configure a board's memory (ROMsim) to closely match the performance and structure of your planned memory configuration. All evaluation boards come with a ROM monitor that can communicate with 196 development-tool debuggers or with a serial interface. Using development tools, you can download 196 object files from the program counter to execute and debug code on the board. You can then use the evaluation board with your application software as part of your prototype-hardware design. The address- and data-bus; port; and other necessary device pins, including reset, power, and ground, are available through headers on each board. You can connect prototype hardware to these pins and operate the board in a stand-alone mode to evaluate the system design. Intel's assembler package comprises a macroassembler, a linker/locator, utilities, and a Windows-based embedded development environment. The linker/locator creates an absolute or executable load image. (Refer to http://developer.intel.com/design/mcs96/devtools/ for more information.) Second source:There are no second sources for the Intel MCS 196/296.
An integrated multiply-accumulate (MAC) unit comprises a 16-bit multiplicand register, a 16-bit multiplier register, a 36-bit accumulator, and two 8-bit address mask registers. It performs a MAC cycle in 480 nsec at 25 MHz. The MAC unit uses a simplified form of modulo addressing to implement FIR filters and circular buffers. Motorola built the 68HC16 modular architecture on the internal InterModule Bus (IMB), which simplifies the addition of on-chip peripherals. Bus protocols are based on the 68020 bus. The IMB contains circuitry to support exception processing, address-space partitioning, multiple interrupt levels, and vectored interrupts. The 68HC16 has a system-integration module that supports an external 20-bit address bus, a 16-bit data bus, and as many as 12 programmable chip selects. The module includes watchdog and periodic timers and a PLL that boosts a 32.76-kHz or 4.2-MHz crystal to system clock speeds as high as 25 MHz. You access memory-mapped, on-chip peripherals through dedicated peripheral registers. The HC16 includes Motorola's in-circuit background-debugging mode (BDM), which allows read and write access of the target system's registers and memory and offers a set of debugging commands. You use BDM to program the on-chip flash and RAM. BDM lets debuggers do source-level debugging and monitor variables without using other processor resources, such as RAM or serial ports. Program and data share a common address or use two separate spaces. The 68HC16's addressing space expands to 1 Mbyte (2 Mbytes for separate code and data spaces for larger applications). Instruction boundaries are on even boundaries and use big-endian addressing. The CPU accesses words on word or byte boundaries. Power management: Wait reduces current by stopping CPU execution while leaving the clock running. A low-power-stop (LPSTOP) instruction stops the clock. Special instructions: The 68HC16 performs bit manipulation with instructions such as bit set, clear, and test. It also supports math instructions, such as add, subtract, BCD, decimal-adjust add, and signed and unsigned multiply and divide. A background operating mode uses special debugging instructions. Development tools: The HC16 family has extensive development-tool support, including assemblers and compilers from eight third-party vendors. Eight vendors offer RTOSs, 14 offer emulators, 13 supply debuggers, three offer evaluation boards, and four supply programmers. Second sources: There are no second sources for the HC16 family.
The semipipelined 7700's CPU fetches the next instruction while executing the current one. A 3-byte prefetch queue holds the next instruction. More than 90% of the instructions execute in less than 1 µsec at 25 MHz. The 16-Mbyte address space divides into 256 64-kbyte banks. The high-order bits of a 24-bit address reference the bank; an 8-bit program- or data-bank register supplies this field. Bank 0 holds the special-function registers, internal RAM, and internal ROM. In single-chip mode, executing from on-chip ROM and RAM, the CPU has only one 64-kbyte bank. For debugging, the chip can run in µP mode, in which it executes from off-chip program memory. The 7700 has a 256-byte "direct page" for time-critical routines. This page can lie in the first 64-kbyte memory bank or between the first and second banks. The 16-bit direct-page register points to the base (lower) address of the direct page. Accessing the direct page using the direct-page register is faster and takes only 2 bytes. The external-memory bus can be multiplexed or demultiplexed. For a 16-bit address, the bus is nonmultiplexed; it uses 16-bit addresses and 8-bit data. The CPU can access 16-bit data from odd or even bytes, but performance degrades when using an odd byte. Power management: During wait, oscillation continues, and the integrated peripherals are active. In stop, oscillation stops, and most peripherals are disabled. Special instructions: The 7700's bit-manipulation instructions include bit set, clear, and test for certain flag bits. Math instructions include unsigned multiply and divide, add, subtract, and decimal adjust. The 37700 performs register A and B exchange and a forced execution breakpoint. Special on-chip peripherals: The M37750F6BFP contains 48 kbytes of 12V flash memory. Some devices, such as the M3807X and M3820X, include real-time ports that you can use to send data out to external devices for a specific number of clock cycles, thus creating precise control for applications such as printer-head control and paper positioning in a laser printer. The M3807X group of devices contains PWMs that you can use to control stepper motors of two, three, or four phases. These PWMs use a single multiplexed output line to control the other coils within the motor. The PWM's output depends on the values of dedicated registers that determine the high and low periods. Most of the MELPS7700 devices support a main clock and a 32-kHz subclock. The main clock allows the device to operate at full speed when it needs to perform calculations or port operations. Development tools: Third-party development tools for the MELPS7700 include the Ashling Ultra-7700 µP-development system, which comprises an in-circuit emulator and the PathFinder-7700 for Windows source-level debugger. Hewlett-Packard (Colorado Springs, CO) provides the 64147A emulator for real-time measurements. IAR's (San Francisco) C compiler supports both of these emulators. Additional development tools include the Lauterbach (Framingham, MA) Trace 32 and Accelerated Technology's (Mobile, AL) Nucleus (RTOS). Byte-Bos offers a multitasking RTOS for Mitsubishi's M377XX µCs. Orion Instruments (Sunnyvale, CA) offers the ADViCE emulation systems hosted by Microview G, a graphical high-level debugger and in-circuit-emulator interface. Fuzzytech offers development software for Inform's fuzzy logic solutions. Second sources: There are no second sources for the 7700.
As with the 68HC16 and 68300 families, Motorola based the HC12 on a modular design methodology. Motorola designers use the Lite Module Bus, which is similar to the InterModule Bus, to connect the core to peripheral modules. The HC12's core contains a module that includes a multiplexed or nonmultiplexed external bus, runtime monitors, and Motorola's background-debugging mode (BDM). The runtime monitors include a watchdog timer, a clock monitor that uses a resistor/capacitor time constant to monitor the speed of the crystal, and a periodic interrupt timer. The BDM, a single-wire implementation (vs four wires on the HC16 & 68300), offers code patching and two hardware breakpoints. (However, the hardware breakpoints are not available on all HC12 derivatives.) BDM also performs nonintrusive reads and writes to memory while the CPU runs at full speed, and the BDM accesses on-chip memory during CPU dead cycles. You can use it to program the on-chip flash or EEPROM or for programming the address comparators to set hardware breakpoints. BDM lets debuggers do source-level debugging and monitor variables without intruding on users' software. Power management: The HC12 uses a PLL to hit 8 MHz and help with the CPU's power management. Current implementations of the core operate from voltages of 2.7 to 5.5V with a path to 1.8V. The HC12 has wait and stop power-saving modes and many other power-saving features in the core. Each module has controls to save power when idle, low noise drivers are available on each I/O pin, and external-bus actions halt when the CPU is accessing internal events. Special instructions: The HC12 supports several indexed addressing modes, most important of which is stack-pointer referencing to handle stack-based parameters. Autoincrement and autodecrement indexed addressing is useful for loop counters in C. You can use the HC12's load-effective-address instruction in C programs to allocate and deallocate stack space. For case statements, indexed indirect-addressing modes allow you to put a computed GOTO in line. A new division instruction on the HC12 allows you to divide a 16-bit number by a 16-bit number instead of using a sign-extended, 32-bit number. Furthermore, the HC12 performs this divide in 12 cycles compared with 41 cycles for the HC11. A 16×16-bit multiply executes in 375 nsec. Minimum/maximum functions compare two values and store the result in the accumulator or the memory. For example, for a minimum function, the µC stores the smaller of the two values. Similar to the 68300 family, the HC12 performs table-look-up and interpolate functions for operations such as compressing table data. The HC12 also includes four instructions to assist with fuzzy logic. Development tools: A relatively large number of vendors support the relatively new 68HC12. Archimedes Software (Kirkland, WA), Cosmic Software (Woburn, MA), and IAR Systems (San Francisco) offer compiler support. CMX Co (Framingham, MA), Embedded Systems Products (Houston), and Motorola provide RTOSs. Eight vendors offer debuggers, eight offer emulators, and 15 supply programmers. Axiom (Clearfield, UT) and Motorola supply evaluation boards. For example, Motorola's $99 68HC912B32 evaluation board operates in BDM and acts as a target and debugger. Inform's (Oak Brook, IL) Fuzzytech HC11/HC12 version generates the fuzzy-logic system as assembly code for the target µC. It also allows you to perform in-circuit debugging using BDM, but, unlike with in-circuit emulators, you need not halt the running system to modify the fuzzy-logic control strategy. Second sources: There are no second sources for the 68HC12.
The CPU supports a multiplexed or demultiplexed external bus. You can set up the address bus to access the 1-Mbyte address space linearly or divided into four chip-select areas. In the multiplexed mode, the M16C's data bus is 8 bits wide; the demultiplexed bus can be 8 or 16 bits wide. Power management: The M16C can use a 32-kHz oscillator in addition to the main clock-oscillation circuitry. Low-frequency, subclock, wait, and stop power-saving modes support the CPU. The low-frequency mode divides the clock by 2, 4, 8, or 16. In the subclock mode, the CPU runs on the 32-kHz subclock. In wait mode, the CPU clock stops with peripheral functions and the oscillator running. Stop mode stops all operation, including oscillation. Special instructions: The M16C has 91 instructions, including bit-manipulation instructions for sequence control, graphics, and data communications. Other special instructions include high-level C-language and operating-system support instructions. Special on-chip peripherals: Some of the functions available on M16 devices include a 10-bit ADC with sample-and-hold circuitry; a subscriber-interface module; an array of multifunction timers; and full-duplex, two-channel UARTs. The M16C also supports a masked ROM program-correction function that uses an address-match interrupt scheme to allow designers to correct two faulty mask-ROM program areas with an external EEPROM. These µCs also have 16-bit CRC circuitry that uses the CRC-CCITT (X16+X12+X5+1) polynomial with either of the chip's UARTs. Development tools: IAR Systems (San Francisco) offers a C compiler, an assembler, and a C-spy simulator-based debugger. Hewlett-Packard (Colorado Springs, CO), and Orion Instruments (Sunnyvale, CA) provide in-circuit emulators. CMX Co (Framingham, MA) provides an RTOS kernel. Mitsubishi offers its own development tools. For example, the M16C starter kit includes an evaluation board, an assembler, and a Windows-based debugger. Mitsubishi also offers software- and hardware-development tools, such as in-circuit emulators, assemblers, C compilers, RTOSs, and programming adapters. Second sources: There are no second sources for the M16C.
The K0S family is a leaner version of the K0. NEC targets this device as low cost and so it has smaller ROM, RAM, and packages than the K0. The K0S has a subset of the K0 instruction set and only one register bank. The K4 provides a 16-bit upgrade path for the K2; it has a code superset and plug-in compatibility. The K4 has a 20-bit program counter and a 24-bit stack pointer and supports an external addressing range of 1 Mbyte. NEC packs as much as 256 kbytes of mask ROM and as much as 12 kbytes of RAM into its K4 devices. The K4's interrupt structure supports standard vectored interrupts, context switching, and macro service. The K4's eight sets of register banks support context switching. Each register bank contains 16 8-bit registers, which you can pair to function as 16-bit registers. Additionally, the K4 can combine any four of the 16-bit registers (actually, four pairs of 8-bit registers) with 8-bit extension registers and use the combination registers for 24-bit address specification. The macro service allows a DMA type of operation to service peripherals, such as the serial port or real-time output port. The register banks are in on-chip RAM along with directly accessible RAM. The CPU addresses the registers symbolically as the current register bank or as memory. You access on-chip, memory-mapped peripherals by main-memory addressing or by special-function-register addressing. All families separate RAM into fast RAM inside the execution unit and separate data RAM. The fast RAM includes 128-byte register and 128-byte data RAM. For context switching with the K3/K4 families, you can specify an alternative register as part of the interrupt vector itself. However, with the K0/K2 chips, you accomplish the context switch with a bank-select instruction before branching to the interrupt-service routine referencing the new bank. K3/K4 µCs contain a 3-byte instruction-prefetch queue. The bus-control unit can fetch an instruction byte from memory during cycles in which the execution unit is not using the memory bus. Power management: Halt mode discontinues CPU operation while all peripherals continue to operate. In stop mode, only the subsystem clock (if used) and interrupts operate. In addition, the K4 has an idle mode, in which the oscillation circuitry continues to operate but the entire system stops. All 78K devices have a programmable clock divider to conserve power during less demanding operations. You can also run the K series devices on a 32-kHz subsystem clock, which allows the microcontroller to stop the main clock. With the dedicated onboard watchdog timer, you can update a time-of-day clock while the microcontroller is in the low-power, subsystem-clock halt mode. Special instructions: Bit-manipulation instructions are bit set, clear, complement, test, and various logic operations. Math instructions include add, subtract, multiply, divide, and decimal adjust. K0/K2 CPUs handle 16-bit operations by pairing adjacent registers in banks. Their 16-bit arithmetic operations include add and subtract word, increment and decrement word, and shift word left or right. K3/K4 µCs can perform a 16×16-bit multiply and a 32×16-bit divide, as well as multiply-accumulate and multiply-and-subtract instructions. Hardware implements a 32-word branch-destination address table that adds a level of indirection to branches and subroutine calls. This option is useful when making frequent calls to specific subroutines because the call instruction (CALLT) is a 1-byte instruction vs a standard 3-byte call to a direct address. Development tools: K series development tools include Windows-interface-controlled emulators. The interface incorporates a project manager to allow a user to write, execute, debug, and trace code; examine registers and memory, and perform other tasks. The user can handle all development functions from within the project manager. Additional elements of the development environment include, low-cost evaluation boards, one-time-programmable- and flash-based devices. NEC also offers software system simulators. This simulator contains a window interface to enable input from components such as switches and potentiometers, along with output from components such as LCDs, LEDs, and motors. Additionally, the simulator supports application operations with C++ or Visual Basic modules. Second sources: None.
The XA's 24-bit program counter provides addressing for as much as 16 Mbytes of linear code space. The prefetch queue holds the next instruction to be executed, improving the instruction-execution performance. The XA's memory structure is the same as that of the 80C51. It has separate data-memory and special-function-register (SFR) spaces. The XA divides its 16-Mbyte data-memory space into 256 64-kbyte segments. The SFRs have the same role in the XA as in the 80C51: controlling and monitoring the on-chip peripheral functions. The XA's stack resides in the data-memory space and can be as large as 64 kbytes. The stack can reside in the on- or off-chip memory space or both on and off chip. The external-memory interface supports the 24-bit memory address, and you can configure it for 8- or 16-bit accesses. At power-on or dynamically under software control, you can configure the data-bus width for 8- and 16-bit accesses. Programmable wait states help you control external memory accesses, and a wait pin allows easy interfacing to external memory and other devices. Power management: A software-controlled idle mode shuts down processor functions but leaves most of the on-chip peripherals and external interrupts functioning; power-down mode shuts down everything, including the on-chip oscillator. Special instructions: The XA supports all of the 80C51 instructions and a variety of new instructions to benefit C programming. The XA performs extensive bit manipulation with instructions such as jump on bit set or clear, set, clear, move, AND, and OR. Math instructions include add, subtract, 16×16-bit multiplication, signed and unsigned 32×16-bit divide, and 32-bit shifts. The XA also has instructions to normalize and sign-extend operands for floating-point support, move data blocks, jump double indirect, breakpoint and trap, and reset. Development tools: Third-party development tools from 25 vendors support the XA. These tools include assemblers, simulators, C compilers, RTOSs, in-circuit emulators, EPROM programmers, development boards, and adapter sockets. Philips' $499 EB-XA emulator serially links to a PC and can emulate in ROMless or ROM mode. The emulator uses a Philips bond-out chip that emulates the µC and reveals the internal resources to the user. The EB-XA supports debugging and breakpoints and allows real-time execution of XA code. Second sources: There are no second sources for the XA.
The TLCS-900 architecture centers on a flexible register set that you can configure for 8-, 16-, or 32-bit processing using a 16-bit ALU and datapaths. Toshiba designed the general-purpose register set for fast context switching, and you partition it into four register banks, each with four 32-bit registers, or eight register banks, each with eight 16-bit registers. The chip operates in minimum mode with a 16-bit program counter and registers or 32-bit maximum mode with 32-bit datapaths, program counter, and registers. The TLCS-900, with 300 to 400 instructions, is backward-compatible with the TLCS-90 but offers a substantial performance increase by using a three-stage pipeline with a 4-byte prefetch queue. The 32-bit maximum mode accommodates large-scale arithmetic and addressing (16 Mbytes) with a basic 16-bit CPU. Configuring peripheral interrupts to bypass CPU interrupts enhances I/O processing. Instead, an I/O controller or special peripheral µDMA processor handles CPU interrupts. Using the I/O controller avoids the overhead of interrupt processing. Peripheral events trigger I/O-controller processing and "DMA" the data to or from memory and internal peripherals. The I/O controller handles as many as four µDMA channels. The CPU can execute from external memory and can dynamically shift bus sizes between 8 and 16 bits while running. Power management: Idle mode shuts down the CPU, leaving all integrated peripherals active. Power-down, or stop, disables the oscillator. Any reset or interrupt request can terminate idle mode; only a hardware reset (nonmaskable interrupt and interrupt 0) can terminate power-down. Special instructions: Bit-manipulation instructions include bit set, clear, change, test, search forward and reverse, and various logical operations. Math instructions include add, subtract, decimal adjust, signed and unsigned 8×8-bit and 16×16-bit multiply, signed and unsigned 16×8-bit divide, and shift 1 bit one to 16 times. The TLCS-900 also has a multiply-accumulate instruction and modulo increment/decrement instructions for circular-buffer pointers. It can also perform block moves and pattern searches in memory. Special on-chip peripherals: Some members of the TLCS-900/H family contain a DRAM controller that operates with either 8- or 16-bit DRAMs. The DRAM controller supplies the control signals for refresh, read/write access control, and a row-column-address multiplexer. Toshiba's clock-gear function allows you to divide the operating frequency of the device by 2, 4, 8, or 16. You can dynamically change the clock gear to meet the instantaneous processing needs of the application. Many of the TLCS-900 devices contain a pattern generator that comprises a 4-bit output port and the control logic to drive a stepper motor. The devices can also contain an LCD driver/controller that supports a 40×four-segment common. An integrated voltage-boost circuit generates the LCD voltages form the battery supply. Development tools: Toshiba offers a real-time in-circuit emulator for the 16-and 32-bit versions for the TLCS-900 series. The emulator contains a controller that interfaces to a PC system through RS-232C or LAN connection. The emulator mimics the target microcontroller. For software support, Toshiba offers a software suite that comprises an assembler, a C compiler, a simulator, and an RTOS. In addition, Avocet Systems (Rockport, ME) and others provide third-party support. Second sources: There are no second sources for the TLCS-900.
The Z180 core with more than 170 instructions contains duplicate banks of six 8-bit, general-purpose registers. Each register bank includes an 8-bit accumulator; a condition code; and six other 8-bit registers, which you can also use as three 16-bit registers. Additional nonbanked 16-bit registers include two index registers, a stack pointer, and a program counter. The Z380 family extends the Z180's capabilities by including a 16-bit data bus, 32-bit registers, an ALU, and eight banks of the basic registers. The Z380 can access as much as 4 Gbytes of memory, uses linear addressing, and eliminates the need for the MMU. Users can select varying degrees of compatibility between the Z80 and Z180. Modes include 16-bit word vs 32-bit long word for data values, and 16-bit native mode vs 32-bit extended mode for address calculations. Decoder directive prefixes allow you to override these global modes for individual instructions. Power management: Halt mode turns off the internal CPU clock while the timers and interrupts remain active. Stop turns off the internal clock and reduces standby current. Sleep mode, available on the Z180 and Z380, stops the CPU while on-chip peripherals are active. Special instructions: The Z180's bit-manipulation instructions are set, reset, or test a bit in a register or a memory location. Math functions include add, subtract, increment, decrement, and decimal adjust. You can perform most math functions as 16-bit operations using register pairs. The Z180's instruction set provides many programming options, including block-memory moves as large as 256 bytes and character searches within a block. The Z180 includes multiply, extra-test, and I/O instructions. Load and store operations transfer data between the various registers and external memory and include immediate, direct, indexed, and register-indirect addressing modes. The Z380 instruction set is upward-compatible with the 180 family. The new operations include 16- and 32-bit multiply and divide, 16-bit shifts and rotates, logical, and compare instructions. Special on-chip peripherals: The basic Z180 includes two DMA channels, two UARTs, and two 16-bit programmable reloadable timers. A clocked serial I/O circuit communicates with external serial memories, microcontrollers, and other serial-bus devices. Autovectored interrupts from these devices and from two external, maskable, interrupt-request lines provide the interrupt efficiency of--and greater ease of use than--the original Z80 family. Other family members add on-chip peripherals for specific applications. The 181, 182, and 185 add multiprotocol serial controllers based on Zilog's serial- and extended-serial-communication devices. The 182 and 189 include 16550 mimic logic for internal PC modems, and the 185 adds advanced PC-parallel-port functions in the host or peripheral role. The 80380 includes a chip-select and wait-state generator and DRAM support. The 80382 adds enhanced versions of many of the 180 peripherals as well as eight list-following DMA channels, three HDLC or unframed serial channels, GCI/IOM-2 logic, and Plug and Play ISA or PCMCIA interfacing. Development tools: The Z180 family has extensive development-tool support. Emulator support is available from Applied Microsystems (Redmond, WA), Emulation Technology (Santa Clara, CA), Hewlett-Packard (Colorado Springs, CO), Huntsville Microsystems (Huntsville, AL), Lauterbach (Framingham, MA), Orion Instruments (Sunnyvale, CA), and Pentica Systems (Bedford, MA). Software support is available from 2500AD (Buena Vista, CO), Avocet Systems (Rockport, ME), and IAR Systems (San Francisco). Zilog supplies several evaluation boards and a low-cost emulator. Unlike with the Z180, development support for the Z380 is minimal. Zilog provides an assembler and an evaluation board, a 2500AD assembler, and a Production Languages Corp (Weatherford, TX) C compiler for the Z380. Second sources: Second sources for the Z180 are Hitachi (Brisbane, CA), NEC (Mountain View, CA), Toshiba (Irvine, CA), and VLSI Technology (San Jose, CA). |
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