September 25, 1997

8-BIT

Intel 8051

The 8051 is an accumulator-based design with 255 instructions. A basic instruction cycle takes 12 clocks; however, Dallas Semiconductor redesigned the instruction-execution circuitry to reduce the instruction cycle to four clocks. The 8051 has a minimum 39-clock latency from the assertion of an interrupt to the beginning of the first instruction of an interrupt-service routine.

The CPU has four banks of eight 8-bit registers in on-chip RAM for context switching. These registers reside within the 8051's lower 128 bytes of RAM along with a bit-operation area and scratchpad RAM. You can address these lower bytes directly or indirectly using an 8-bit value. The upper 128 bytes of on-chip data RAM encompass two overlapping address spaces. One space is for directly addressed special-function registers (SFRs); the other space is for indirectly addressed RAM or stack. The SFRs define peripheral operations and configurations. The 8051 also has 16 bit-addressable bytes of on-chip RAM for flags or variables.

Without external support circuitry, the theoretical maximum address range of all 8051 processors is 64 kbytes of program memory and 64 kbytes of data memory. However, software tools with an external latch allow you to increase this address space to any number of 64-kbyte pages. The software seamlessly handles all page transitions.

Register indirection uses an 8-bit register for an on-chip RAM address; an off-chip address needs a 16-bit data-pointer register (DPTR). The 8051 has only one DPTR (Atmel, Dallas, and Philips µCs have two DPTRs; Siemens µCs have eight DPTRs.) You cannot index the DPTR; however, you can increment the 16-bit DPTR. You can index program-memory accesses using move-code instructions for look-up tables or constants. The CPU has bidirectional and individually addressable I/O lines.

Power management:

Idle mode discontinues CPU processing but leaves the clock, timer, serial-peripheral-interface, and serial-communications-interface systems enabled. Power-down stops the clock and all internal processing. Both modes maintain RAM and, for some of the 80C51 derivatives, enable interrupts to wake the CPU. You can program and selectively turn off most peripherals. Dallas and Siemens devices also provide programmable-clock divisors. Dallas' devices can automatically return to full-power operation as a result of an external interrupt or incoming serial character.

Special instructions:

The 8051 performs extensive bit manipulation via instructions, such as set, clear, complement, and jump on bit set or jump on bit clear, only for a 16-byte area of RAM and some SFRs. It can also AND or OR bits with a carry bit. Dallas versions have variable-length move-external-data instructions. Math functions include add, subtract, increment, decrement, multiply, divide, complement, rotate, and swap nibbles. Some of the Siemens devices have a hardware multiplier/divider for 16-bit multiply and 32-bit divide.

Development tools:

The 8051 has extensive tool support. Emulators are available from such companies as Nohau Corp (Campbell, CA), Hitex GmbH (San Jose, CA), and MetaLink Corp (Chandler, AZ). Tasking (Dedham, MA) and Keil Software (Dallas) offer compiler and software-development support. Needham Electronics (Sacramento, CA) and Data I/O (Redmond, WA) offer programming support. In addition, most 8051 vendors provide evaluation kits. Several RTOS vendors also support the 8051.

Second sources:

Second sources for the 8051 are Atmel, Dallas, Intel, Oki, Philips, Siemens, and Temic (San Jose, CA).

Atmel AVR

Atmel's 8-bit AVR RISC architecture, which was designed in Norway, includes a 16-bit, fixed-length instruction; a load/store architecture; and 32 general-purpose registers. The AVR also executes an instruction on every clock by prefetching an instruction during the previous instruction execution. Although Atmel sells many 8051s, the company claims that AVR is 10 times faster than the 8051, which requires four to 12 clocks per instruction.

AVR's 32 registers constitute the architecture's fast-access RISC register file and connect directly to the processor's ALU. The ALU supports arithmetic and logic functions between registers or between a constant and a register. The ALU also executes single-register operations. You can address the dual-mapped register file as part of the on-chip SRAM. Some µCs in the AVR product family feature a hardware multiplier in the arithmetic portion of the ALU. AVR uses a Harvard-style architecture and directly addresses as much as 8 Mbytes of program memory and 8 Mbytes of data memory.

Low-end versions of AVR without onboard RAM have a limited, four-level-deep, RAM-based hardware stack dedicated to subroutines and interrupts. Parts with onboard RAM have no hardware stack. The memory-mapped I/O space contains 64 addresses for CPU peripheral functions, such as control registers, timer/counters, and A/D converters.

Power management:

The architecture supports idle and power-down modes. The idle mode stops the CPU while the registers, timer/counter, watchdog timer, and interrupt system continue functioning. Power-down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.

Special instructions:

AVR supports approximately 120 instructions. Bit-manipulation instructions include bit set, clear, store, and load; some instructions can conditionally test bits in I/O space.

Special on-chip peripherals:

You can use the AVR's serial peripheral interface to program the onboard flash memory.

Development tools:

Atmel offers the AVR Studio software-debugging environment for simulation and real-time emulation. This tool, available from Atmel's Web site, contains an absolute assembler and is the front-end tool for the ICEPRO emulator. The AT90ICEPRO, which sells for $2495, supports current and future AVR devices. Atmel also sells the Flashlite evaluation board, which allows designers to program and run real-time code in an AVR device. This $49 board contains LEDs, headers, and buttons to allow users to evaluate and debug code. IAR Systems (San Francisco) supplies an ANSI-compliant C compiler, a relocatable assembler, a linker, and a loader that support all AVR devices except for the AT90S1200.

Second sources:

There are no second sources for the AVR.

Mitsubishi MELPS740/WDC W65C02S

Although the Mitsubishi MELPS740 is a redesign of Western Design Center's (WDC) 6502, the two architectures have many similarities. The accumulator-based 740 and W65C02S have 71 instructions, an 8-bit accumulator, and two 8-bit index registers. The stack pointer is 8 bits wide; the program counter is 16 bits wide. The CPU is semipipelined: It fetches the next instruction while decoding and executing the current instruction. With a relatively fast memory interface, this feature lets code use part of internal RAM as a large register set to hold dynamic variables.

The 740 and W65C02S have a 64-kbyte unified address space, which divides into 256-byte pages for X and Y indexing. The 0 page is the first page in memory, and you can easily address it using special address modes and instructions. The chip has a fast, nonmultiplexed external bus--16 bits for addresses and 8 bits for data.

WDC's 16-bit extension of the W65C02S, the W65C816S, has a 6502-emulation mode that lets the W65C816S directly execute 6502 object code. The extended versions have a 16-bit accumulator, an index, and a stack-pointer register. The W65C816S also adds 78 operation codes, nine addressing modes, and a second 8-bit accumulator. Mitsubishi also extends the architecture to 16 bits with the 7700 series.

The W65C816S addresses as much as 16 Mbytes; the W65C02S has a 64-kbyte limit. The 16-bit CPU generates a 24-bit address by concatenating the 16-bit program or calculated address with an 8-bit bank register. (The W65C02S reserves separate bank registers for program and data.)

Power management:

The devices have stop and wait low-power modes. Most of the M38XXX products support key-on-wake-up (K-O-W), a method of recovering from a low-power-consumption mode or sleep mode. When the system is idle, K-O-W can place it in sleep mode. During the sleep mode, the internal clock stops and thereby reduces power consumption while retaining its memory and status. When the system uses K-O-W, any key a user presses calls an interrupt that restarts the clock, waking the system back to its normal mode, which is transparent to the user.

Special instructions:

The W65C02S and 740 support bit-manipulation instructions that include set, clear, test, complement, and branch if bit is 0 or 1. Math functions include add, subtract, increment, decrement, and decimal adjust. STP stops the clock; WAIT waits for an interrupt. The 816S performs block moves.

Special on-chip peripherals:

The M376XX devices support an internal charge pump that allows the µC to perform voltage conversions. You can interface these µCs to external devices with different voltage requirements without extra hardware. The M37630 contains a module to support the Basic-CAN version 2.0B protocol. The M37640 supports a 12-Mbps USB hub or a single application. This device has the D+ and D­ reference voltage for direct USB communications to the host or another hub. The M37690M8 supports General Magic's (San Francisco) proprietary serial bus format, Magicbus.

Development tools:

Mitsubishi's PC4701 emulator provides real-time debugging for the 740 series products. The emulator operates with PC-compatible software to control target-system debugging. The software provides a multiwindow development environment. IAR Systems (San Francisco), 2500AD (Buena Vista, CO), and ByteCraft (Waterloo, ON, Canada) offer C compilers. WDC supplies an assembler/linker package.

Second sources:

There are no second sources for the Mitsubishi series. Sanyo (San Diego) is a second source for the WDC products.

Texas Instruments TMS370

The TMS370's register-based arch itecture has 73 instructions and as many as 256 8-bit registers in a RAM register file. The CPU can address these registers as registers or as RAM. An 8-bit stack pointer references the processor stack, which resides in the register RAM. The CPU also contains a 16-bit program counter to access as much as 64 kbytes and an 8-bit program-status register. You access on-chip peripherals and EEPROM/EPROM programming control through a set of memory-mapped registers in a peripheral file. The TMS370 assigns each peripheral a frame of 16 registers in the 16-frame peripheral file.

Although the TMS370 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, load/stores, and memory/ register and memory/memory exchanges.

Power management:

Standby mode stops the internal clock in every module except the Timer 1 module, which brings the CPU out of standby. Halt stops the internal clock, which you can restart by a reset or an external interrupt. Both modes maintain RAM. You can program and selectively turn off most special peripherals.

Special instructions:

The TMS370's bit-manipulation instructions are set, clear, complement, and jump if bit is 0 or 1. Bit instructions operate on registers in register or peripheral files. Math functions include add, subtract, increment, decrement, decimal adjust, multiply, and divide. The CPU has some 16-bit operations, such as word moves (a register pair) and incrementing a word, and it uses 16-bit offsets for jumps and register pairs as an address for subroutine calls.

Special on-chip peripherals:

The TMS370 timers provide multiple options. For example, Timer 1 supports 16 bits of granularity with a 8-bit prescale and includes a watchdog. Both timers 1 and 2 automatically generate PWM. The TMS370x3x family includes the Programmable Acquisition and Control Timer (PACT), a timer coprocessor module that generates as many as eight PWMs without CPU overhead. The 370's serial communications and serial peripheral interfaces both have selectable baud rates and data formats.

Development tools:

TI's development tools for the TMS370 offer support from evaluation through production. All tools use a similar interface that allows symbolic debugging in either assembly language or C source code. A $99 starter kit includes a software simulator, an assembler/linker, and a board for programming EPROM-based µCs. TI's C compiler accepts ANSI C source code and performs four selectable levels of generic- and target-specific optimizations. The $1000 TMS370 Compact Development Tool (CDT) supports all 135 TMS370 family members with the same development platform. This single-board, real-time, in-circuit emulator plugs into your PC. Through the use of an appropriate target cable, the CDT can connect to the application board's microcontroller socket and emulate the proper TMS370 devices. Features include program-counter trace, an integrated EPROM/EEPROM programmer, an assembler/linker, and a symbolic debugger.

Second sources:

There are no second sources for the TMS370.

Zilog Z8

The register-file-based Z8's core has 50 basic instructions and as many as 256 8-bit registers in RAM. On-chip peripherals are memory-mapped, and you access them through the register file. The RAM also holds the I/O-control registers; 16-bit, two-register stack pointer; and register pointer. The CPU contains a 16-bit program counter and an 8-bit program-status register. In addition to the register file, the Z8 architecture has 64-kbyte code and 64-kbyte data-address spaces. The Z8 allows the use of external memory for both code and data spaces. References to external memory are loads or stores only; data manipulation is confined to operations between on-chip registers. For interrupt-driven applications, the stack may reside off-chip.

Some Z8-based chips have the Z8 core plus a DSP engine with a 24-bit ALU; other chips implement infrared remote-control functions by incorporating IR signal-generation and -demodulation timers.

Power management:

Halt mode turns off the internal CPU clock while the timers and interrupts remain active. Stop mode turns off the internal clock and reduces standby current.

Special instructions:

Bit-manipulation instructions in the Z8 include AND, OR, and XOR logical instructions and some bit-test instructions. Arithmetic instructions include add, subtract, increment, and decrement. Some Z8 devices support 16×16-bit multiply and 32×16-bit divide. The versions with integrated DSPs perform multiply-accumulate operations. Z8 chips include complex instructions that help to minimize coding of multiple operations, such as fetching and operating on data and incrementing address pointers.

Special peripherals:

Z8 chips contain power-on-reset circuitry to eliminate the need for an external reset circuit. They also support brown-out voltage detection that holds the Z8 in a reset condition while V_CC is below the V_BO spec value. When the V_BO point is below V_CC minimum, Zilog guarantees that the product will operate correctly down to the V_BO point. Every Z8 contains voltage comparators that serve as low-cost ADCs. Zilog provides a reference design for rapid battery charging. (For example, it charges NiCd batteries in 20 minutes.) Every Z8 comprises an 8-bit timer with a 6-bit prescaler, usually viewed as the equivalent of a 14-bit timer. Each timer has an independent interrupt and one timer-output signal.

The Z86C83 and 84 have an eight-channel, 8-bit ADC that can offset the A_GND level by (V_CC/2), giving 10-mV resolution across this range. This feature is important in charging some battery chemistries that require at least 15-mV resolution.

Development-tool support:

A low-cost, full-featured, in-circuit emulator with Windows-based software supports the Z8.

Second sources:

There are no second sources for the Z8.

Microchip PICmicro 16Cxx/17Cxx

The register-based PICmicro family comprises the eight-pin PIC12C5xx/67xx, the base-line PIC16C5x, the midrange PIC16Cxx, and the high-end PIC17Cxx. These controllers employ a modified Harvard, RISC-like architecture that supports various-width instruction words. The datapaths are 8 bits wide, and the instruction widths are 12, 14, and 16 bits wide for the PIC16C5x/PIC12C5xx, PIC12C67xx/PIC16Cxx, and PIC17Cxx, respectively. Variable instruction-bus widths allow all the devices to fetch instructions in a word and execute most instructions in one pipelined cycle.

PICmicros are available with one-time-programmable EPROM, flash, EEPROM, and program ROM. Only the PIC17Cxx supports external memory via a multiplexed, 16-bit address, 8-bit data external bus. The PIC16Cxx and PIC17Cxx architectures support instruction words as large as 8 and 64 kbytes, respectively. Multiple register sets allow fast context switching. The PIC16C5x lacks interrupt support, so it handles external-event interrupts via polling; the PIC16Cxx and PIC17Cxx devices have as many as 12 and 18 interrupt sources, respectively.

Power management:

Low-power sleep mode reduces power consumption to only transistor leakage. In this mode, the PIC devices maintain RAM and register contents while all clocks are stopped. All devices operate at 32 kHz to save power.

Special instructions:

PICmicro bit-manipulation instructions are bit set, clear, and test. Math functions include add, subtract, increment, and decrement. PIC16Cxx and 17Cxx have a decrement-and-skip-on-0 instruction. The PIC17Cxx adds a bit toggle, a multiply, and code-saving compare-and-skip instructions. The PIC17Cxx also supports table instructions that move data into and out of program memory--typically constants--to registers for processing.

Special on-chip peripherals:

The PIC16C9xx family (winner of EDN's 1997 Innovation of the Year award) contains an LCD controller that generates its voltage from a high-current, switched-capacitor charge pump. This charge pump, operating off a 3V supply voltage, uses four external capacitors as part of an analog sampling circuit that measures system losses and overcharges accordingly. The charge pump can generate as much as three times the supply voltage, resulting in improved display contrast independent of varying battery voltages. Some PIC devices contain a high-speed USART that supports a 1.25-Mbps asynchronous interface. Other features include internal brown-out reset and an internal on-chip RC oscillator that is accurate to within 5% and frees I/O lines for other system functions.

Development tools:

Microchip provides in-circuit emulators (ICEs), a development system, a device programmer, a development environment, a C compiler, a macro assembler, and fuzzy-logic-development software. The company also offer its MP-DriveWay application-code generator. In addition, more than 125 third-party developers offer development systems supporting the PICmicro architecture.

Microchip's PICmaster Universal ICE interfaces to Windows and includes an emulator-control pod, a target-specific emulator probe, a programmer, a PC host-interface card, and PC-host-emulation control. In addition, the development tool contains Microchip's MPLab development environment. Microchip offers a lower cost ICE for the PIC16C5x and PIC16Cxx devices. This ICE provides many breakpoints; single, multiple, and procedure steps; the ability to display and modify any register; user-selectable processor speeds via an oscillator module; context-sensitive help; and an RS-232C port.

The $199 PICstart development system supports all current and future PICmicro devices and features a development programmer allowing users to program user software. Microchip's MP-DriveWay application-code generator provides a Windows-based automatic code generator that supports the PICmicro µCs. It allows users to produce tested and documented C code to control on-chip peripherals.

Second sources:

There are no second sources for the PICmicro- family.

Intel MCS 151/251

The MCS 151 and 251 cores are binary-code-compatible with the 8051. (The 251 has additional instructions.) The 151 maintains the 80C51 accumulator-based core compatibility, and the 251 is a register-based architecture. Both cores have a three-stage pipeline that allows the CPU to run at a minimum of two clocks per instruction cycle (vs 12 clocks for the 8051 or four clocks for the Dallas version). The 251 CPU comprises an 8-bit ALU, an instruction sequencer, a 24-bit program counter, a 40-byte register file, and four banks of eight registers. You can address its register file as bytes, words, or double words, and all registers are available as register pointers (vs the single data pointer of the 8051).

The MCS 151 and 251 have an internal, 16-bit-wide instruction bus that supports a 16-bit fetch per cycle from the internal code memory through the CPU's bus-interface unit. The data bus is 8 bits wide. To handle large applications, the MCS 251 architecture can perform 24-bit linear addressing for a 16-Mbyte memory space. (Implementations may vary, however.) The 251 and 151 also have programmable wait states and page mode, and you can select extended address-latch-enable capability with a user-programmable configuration.

Power management:

Idle mode discontinues CPU processing but leaves the clock, timer, serial-peripheral-interface, and serial-communications-interface systems enabled. Power-down stops the clock and all internal processing. Both modes maintain RAM and enable an interrupt to wake the CPU. You can program and selectively turn off most peripherals.

Special instructions:

The MCS 251 has new instructions as well as the instructions the 8051 supports. New instructions include 16-bit arithmetic and logic instructions, conditional jumps, and a jump to the location, depending on the result from the previous instruction.

Special on-chip peripherals:

The programmable counter array comprises a 16-bit timer and five compare and capture modules. You can use each compare and capture module in rising- and falling- edge-capture, software-timer, high-speed-output, or PWM mode. You can also use the fifth module as a watchdog timer.

Development tools:

Intel and third-party vendors provide a range of development tools and services to support the 151/251 architecture. Tools include emulators, evaluation kits, programmers, development software, logic analyzers, and RTOSs. Examples of emulators include the Emul251-PC from Nohau (Campbell, CA), AX251 from Hitex GmbH (San Jose, CA), and ICEmaster from MetaLink (Chandler, AZ). Needham Electronics (Sacarmento, CA) and Data I/O (Redmond, WA) provide programming support. Software tools include Compass/251 from Production Languages (Weatherford, TX), DK251 developers kit from Keil Software, and tools from Tasking (Dedham, MA). (For more information about tools, go to http://developer.intel.com/sites/developer/.)

Second sources:

Temic Semiconductors (San Jose, CA) offers a 251 with an ADC.

Motorola 68HC05

To date, more than 180 versions of the 68HC05 are available. The accumulator-based low-end 68HC05 µC has few registers and a stripped-down 6800 instruction set with 64 instructions. The instruction set features 10 uncomplicated addressing modes, including 8- and 16-bit indexing from the 16-bit program counter. The 68HC05 architecture can directly access a maximum of 64 kbytes; you can use paging to access additional memory. In addition to the accumulator, the CPU's core has an index register, a 5-bit stack pointer, and a 5-bit condition-code register.

Power management:

Wait mode discontinues CPU processing but leaves the clock, timer, serial peripheral interface, and serial communications interface enabled. Stop stops the clock and all internal processing. Both modes maintain RAM and enable an interrupt to wake the CPU. You can program and selectively turn off most special peripherals.

Special instructions:

The 68HC05's bit-manipulation instructions are set, clear, test, jump on bit set, or jump on bit clear. The CPU can test and branch on an interrupt bit, but branches are ±127 bytes relative to the program counter. Math functions include add, subtract, increment, decrement, and multiply.

Special on-chip peripherals:

The 68HC05's timer/counter is built around a 16-bit free-running counter, which is coupled with a 16-bit capture register and a 16-bit compare register. The capture register captures timer values on some line events; the timer/counter continually compares the compare register with the running timer. When the registers match, an output compare flag is set, and an output pin is driven to a programmed value. The 68HC705V8 and 68HC05V7 contain a voltage regulator that provides 5V directly from a 12V battery. The 68HC705JB2 and 68HC708KL8 include USB support with a 3.3V bandgap reference that helps reduce costs by eliminating an external voltage regulator. The 68HC708LN56, with built-in LCD support, includes 8-bit contrast control to control display quality with changes in voltage in battery-powered applications. The 68HC08AZ family includes Motorola's scalable controller-area network (MSCAN), which supports both 2.0A and 2.0B specs with a prioritization scheme that allows determination of maximum wait time for each CAN message.

Development tools:

Many third-party development tools are available for the 68HC05. These tools include compilers, source-level debuggers, a PC-based software simulator, production programmers, evaluation systems, and in-circuit emulators. Visit Web site http://design-net.com/csic for a listing of available products.

Second sources:

Harris Semiconductor (Melbourne, FL), Hitachi (Brisbane, CA), and SGS-Thomson (Phoenix) support some versions.

Motorola 68HC08

The accumulator-based 68HC08 provides a code-compatible per-formance extension to the 68HC05 along with 78 new instructions. Although the CPU has only an 8-bit accumulator, the index register, stack pointer, and program counter are 16 bits. (The condition-code register is 8 bits.) The 68HC08 architecture can directly access a maximum of 64 kbytes and as much as 16 Mbytes using indexed addressing.

The 68HC08 has a standard internal bus, I-Bus, that promotes derivatives by easing the addition of peripheral modules. All peripherals are memory-mapped. The HC08 also includes the System Integration Module (SIM), which is analogous to the SIM built into all 683xx chips. The SIM incorporates bus-clock generation for the CPU and modules, a watchdog timer, and interrupt and reset control.

Power management:

Wait mode discontinues CPU processing but leaves the clock, timer, serial peripheral interface, and serial communications interface enabled. Stop stops the clock and all internal processing. Both modes maintain RAM and enable an interrupt to wake the CPU. You can program and selectively turn off most peripherals.

Special instructions:

The 68HC08's bit-manipulation instructions are set, clear, test, jump on bit set, or jump on bit clear. The CPU can test and branch on an interrupt bit but branches are ±127 bytes relative to the program counter. Math functions include add, subtract, increment, decrement, multiply, divide, and decimal-adjust accumulator.

Development tools:

Many third-party development tools are available for the 68HC08. These tools include compilers, source-level debuggers, a PC-based software simulator, production programmers, evaluation systems, and in-circuit emulators. Visit Web site http://design-net.com/csic for a listing of available products.

Second sources:

There are no second sources for the 68HC08.

Motorola 68HC11

The 308-instruction 68HC11 has two 8-bit accumulators, an 8-bit condition-code register, two 16-bit index registers, a 16-bit stack pointer, and a 16-bit program counter. The CPU can address the two accumulators as a 16-bit accumulator.

The 68HC11 restricts addressing to a 64-kbyte unified address space. Some versions have a memory-extension unit that expands addressing to 1 Mbyte using bank-switched paging. Two memory windows in the 64-kbyte address space map into a 1-Mbyte space. The CPU can directly access memory-mapped I/O (on-chip peripherals).

The 68HC11s run in single-chip mode using only on-chip memory resources or in expanded mode. Expanded mode replaces some I/O ports with an address/data bus to access external memory. Both multiplexed and nonmultiplexed external-bus versions are available. Some versions have programmable chip selects.

Power management:

Wait mode discontinues CPU processing but leaves the clock, timer, serial-peripheral-interface, and serial-communications-interface systems enabled. Stop mode stops the clock and all internal processing. Both modes maintain RAM and enable interrupt to wake the CPU. You can program and selectively turn off most peripherals.

Special instructions:

The 68HC11's bit-manipulation instructions are bit set, clear, test, and jump if bit is set or clear. Math functions include add, subtract, increment, decrement, divide, and multiply. Instructions also swap accumulators, exchange an accumulator and an index register, transfer stack pointer+1 to an index register, and set the stack pointer from an index register. A wait-for-interrupt instruction increments the program counter, puts all registers on the stack, halts, and waits for an interrupt.

Development tools:

Many tools, including assemblers, compilers, and debuggers from 14 third-party vendors, support the HC11 family. Nine vendors offer RTOSs for the HC11, 23 offer emulators, six offer evaluation boards, and 15 supply programmers.

Second sources:

Toshiba (Irvine, CA) acts as a second source for some A and E series devices.

National Semiconductor COP8

The COP8's accumulator-based architecture includes six to eight control and data registers, one of which is an 8-bit program-status register. The CPU also includes two 8-bit address registers, a 16-bit stack pointer, and a 15-bit program counter, which the CPU can access as upper and lower 8-bit registers.

The COP8 executes an add, shift, or load in one internal clock (1-µsec period). The compact and relatively simple instruction set executes 77% of the operations in one clock and takes only 1 byte. One reason for the compact instructions is that the architecture, except for the accumulator, is memory-mapped. Also, National based the COP8 on a modified Harvard architecture. COP8 chips can run with external memory for debugging and prototyping code. An 8-bit port serially reads from and writes to external memory and provides emulation control.

Power management:

You can slow the COP8's clocks to minimize power dissipation. Idle mode restricts peripheral operations; halt stops the clock. Both modes maintain RAM and enable an interrupt to wake the CPU. You can program and selectively turn off most special peripherals.

Special instructions:

The COP8's bit-manipulation instructions include set, clear, various logic instructions, and bit test and skip to next instruction. Math functions include add, subtract, increment, decrement, decimal correct, and complement. Instructions also swap accumulator nibbles and exchange accumulator and memory. Other special COP8 instructions include decrement register and skip if zero, return from subroutine and skip, and software-trap interrupt.

Special on-chip peripherals:

National divides the COP8 family into several products lines, including the ACC, 888xG, 888FH, and 888EB products. The COP8ACC incorporates a user-programmable 16-bit ADC achieving 410-µsec conversion at 12-bit resolution ±1 LSB. The COP888xG family comprises nine compatible devices with a common feature set of three multifunction timers, a full-duplex UART, and two analog comparators. The company based the COP888FH on the COP888xG family. The COP888FH integrates a hardware multiply/divide block. The COP888EB targets communications and includes UART, controller-area-network (CAN), serial-peripheral, and Microwire/Plus interfaces and an 8-bit, eight-channel ADC.

The standard COP8 timer comprises a 16-bit counter with two capture/autoreload registers. You can use the timer for external-event capture and counting, internal timekeeping, and processor-independent PWM signal generation. The COP888CF, COP888GD, and COP888EB contain 8 bit, eight-channel, successive-approximation ADCs. For higher resolution A/D conversion of as much as 16 bits, the COP888EK and COP8ACC have an analog function block with a constant current source and a voltage reference. The COP8ACC has a high-speed capture timer that operates at the oscillator frequency. You can tie the output of the analog comparator in the block to the capture input of a timer for integrating single-slope A/D conversion. The COP888EB and COP888BC support passive CAN 2.0B communication. Most COP8s contain full-duplex USARTs with a flexible internal baud-rate generator that generates the UART clock from the oscillator frequency. The COP8s also support ESD protection as high as 5 kV and reduce EMI by as much as 20 dB.

Development tools:

National Semiconductor offers a free assembler/linker/librarian via the company's Web site, www.national.com/cop8. KKD (Denmark) provides a Windows-based IDE and project manager. Aisys (Israel) provides DriveWay COP8, which lets users specify and configure which peripherals they want to use for an application. DriveWay assembles the shell of the program with the peripheral drivers and interrupt support for either National's assembler or ByteCraft's (Waterloo, ON, Canada) C compiler. MetaLink (Chandler, AZ) provides three levels of in-circuit emulation and evaluation with a common windowed user interface. The IceMASTER-400 runs at full speed with source-level debugging and 32 kbytes of available breakpoints. Trace capability is as large as 4000 frames, and software-performance analysis is available.

National offers a low-cost debugging module that also operates at full speed but with fewer available breakpoints, a smaller trace memory, and no software-performance analysis. The debugging module also contains a programmer that programs all available EPROM-based devices. National provides an evaluation-and-programming unit for entry-level evaluation and simple in-system development and debugging as well as programming of EPROM-based COP8 µCs. The company also offers low-cost evaluation boards.

Second sources:

There are no second sources for the COP8.

Oki nX 65K

Oki's 65K series chips combine an 8-bit core with an 8-bit bus. Although these µCs with 83 instructions are code-incompatible with the 8051, a translator package and some handiwork can translate code from one to another. Oki also sells an nX 66K series, an extension of the 65K core with a 16-bit core and an 8-bit bus. The nX 65K has four sets of 16 local registers mapped into data memory. One set acts as the current set for processing; switching to a new set makes for a fast context switch because no registers have to be saved. Four of the 8-bit registers in each set can function as two 16-bit registers for addressing. The 65K core also has two accumulators, a stack pointer, a program-status word (PSW), and a 16-bit program counter.

The 65K series chips have a 64-kbyte address space for instructions and data. Memory-mapped special-function registers control the peripherals. The 65K series lacks specialized data-memory segments that require special addressing or logically overlap other segments. The 65K blocks local memory into 256-byte pages; a field in the PSW enables reference to these pages. Code can address paged memory using 8-bit registers. Main-memory accesses require 16-bit addresses. The 65K distinguishes between local, 8-bit, addressable paged memory and general, 16-bit, addressable memory.

Power management:

Halt mode discontinues the CPU function with peripherals still functioning. Stop mode stops the clock and all functions other than interrupt. New devices have a dual clock. Improved throughput, which allows for lower clock frequencies, saves power under normal operation.

Special instructions:

The nX 65K's bit-manipulation instructions are set, clear, transfer to carry, jump on bit set, and jump on bit clear. Math functions include add, subtract, increment, decrement, multiply, divide, and decimal adjustment after add or subtract. The CPU also has a parity-check instruction.

Special on-chip peripherals:

Every 8-bit nX 65K is available in masked-ROM, ROMless, and one-time-programmable versions. The MSM65355 has a special input module to capture and decode remote-control signals, such as those that TV remote controllers use.

Development tools:

A variety of hardware and software tools is available for Oki's nX 65K. A program-development system, the OMFICE in-circuit emulator, works with evaluation models. Software includes a relocatable assembler, a linker, a librarian, a symbolic debugger, an object converter, and an 80C51 translator. In addition to Oki's OMFICE, third-party emulators are available from MetaLink (Chandler, AZ) and Yokogawa Digital (Tokyo). IAR (San Francisco) offers a C compiler to support the 65K series.

Second sources:

There are no second sources for the nX 65K.

SGS-Thomson ST9

The nucleus of the ST9 comprises a core that includes the CPU, register file, interrupt and DMA controllers, and the memory-management unit (MMU). The MMU lets you address as much as 4 Mbytes of program and data memory mapped into one linear space. The ST9 has a 22-bit memory bus, an 8-bit register-addressing bus, and a 6-bit interrupt/DMA bus. The interrupt/DMA bus connects the interrupt and DMA controllers in the on-chip peripherals to the core.

The CPU, with 94 instruction types, manages the 256-byte register file as 14 sets of 16 8-bit gene ral-purpose registers. (The 15th set is the system page, and the 16th set is addressed as peripheral registers.) Switching from one set of registers to another allows fast context switching because the CPU need not save or restore registers. The CPU also contains an 8-bit program-status register. You can use the general-purpose registers as accumulators, index registers, or address pointers. Adjacent register pairs constitute 16-bit registers for addressing or 16-bit processing. Although the ST9 has an 8-bit ALU, the chip handles 16-bit operations, including arithmetic, loads/stores, and memory-to-register and memory-to-memory exchanges. Many operation codes specify byte or word operations; the hardware automatically handles 16-bit operations and accesses. A 2-byte opcode+displacement instruction usually requires two memory fetches; a 16-bit instruction takes only one fetch.

For interrupts or subroutine calls, the CPU uses a system stack with the stack pointer. A separate user stack has its own stack pointer. The separate stacks without size limitations can be in the on-chip RAM, register file, or off-chip memory.

Power management:

ST9 implements three modes: slow, wait-for-interrupt, and halt. In slow mode, a CPU prescaler and clock-control unit reduce the clock frequency to the CPU and peripherals. See the Web-site version at www.ednmag.com for more details. In halt mode, the CPU and its peripherals stop operation, and the I/O ports enter high-impedance mode if the watchdog timer is disabled. The system must assert a reset for the CPU to exit halt mode.

Special instructions:

The ST9 instruction set includes instructions for bit handling, 8-bit byte data, and 16-bit word data, as well as BCD and Boolean formats. Other instructions facilitate large program and data handling through the MMU, as well as improve the code density of C function calls. The ST9's bit-manipulation instructions are set, clear, complement, test and set, and load, and the ST9 can perform AND, OR, and XOR logic instructions on any register. Math functions include add, subtract, increment, decrement, decimal adjust, multiply, and divide. The ST9 has 14 addressing modes, including indirect-addressing capabilities.

Special on-chip peripherals:

The 16-bit multifunction timers of the ST90158 and ST90135 each have an 8-bit prescaler and 13 operating modes. This functionality allows you to use complex-waveform generation and measurements, PWM functions, and other system-timing functions. Two DMA channels support each timer. In addition, these devices contain an eight-channel ADC with sample and hold and 8-bit resolution. Two of the input channels feature automatic voltage monitoring. The devices also contain a full-duplex se-rial communications interface with an integral generator, programmable asynchronous and synchronous capability, an associated address/wake-up option, plus two DMA channels. A programmable PLL clock generator lets you use 3- to 5-MHz crystals to obtain a range of internal frequencies as high as 16 MHz.

Development tools:

Development-tool support for the ST9 family includes emulators, programmers, assembler/linkers, debuggers, archivers, and a C-compiler chain with source-level debugging capability from Cygnus (Mountain View, CA).

Second sources:

There are no second sources for the ST9.

Toshiba TLCS-90

Toshiba's TLCS-90 incorporates the basic Z80 instruction set in an 8-bit µC with various peripherals. Unlike the Z80, which is a µP, the TLCS-90 can execute code from on-chip ROM and RAM. The µCs feature a Z80-like dual set of eight 8-bit general-purpose registers. You can pair the registers for 16-bit loads, stores, and arithmetic operations. The dual set of registers allows the programs to perform fast context switching and register storage. Two 16-bit index registers, a stack pointer, and a program counter supplement the general-purpose registers. These index registers, as well as 16-bit loads, exchanges, and arithmetic operations, make 16-bit addressing simple. Two 8-bit bank registers extend addressing from 16 to 24 bits, and a memory-management unit extends addressing to 8 Mbytes of data.

The TLCS-90's core uses a two-stage, pseudopipeline architecture to speed operations. In the first stage, the CPU fetches and decodes instructions; in the second stage, the decoded instructions are executed. Instructions have 1 or 2 op-code bytes. Immediate and address data can take as many as 3 bytes; the maximum instruction length is 5 bytes (2 op-code and 3 data bytes). The first op-code byte specifies the position of the second op-code byte in the instruction stream.

Power management:

Idle mode shuts down the CPU, leaving all integrated peripherals active. Power-down (stop) disables the oscillator. A reset or interrupt request can terminate idle mode; only hardware reset (nonmaskable interrupt and Interrupt 0) can terminate power-down.

Special instructions:

Bit-manipulation instructions include bit set, clear, test, and various logical operations. Math instructions include multiply-accumulate, add, subtract, decimal adjust, signed 8×8-bit multiply, and signed 16×8-bit divide. The TLCS-90 can also perform block moves and pattern searches in memory.

Development tools:

Toshiba provides a C-compiler, an assembler, a source-level debugger, a DOS-based controller, and a real-time emulator for each derivative. The controller is common for all derivatives.

Second sources:

There are no second sources for the TLCS90.

Toshiba TLCS-870 and TLCS-870X

The register-based architecture of the TLCS-870 and 870X Series uses memory mapping to access the devices' general-purpose registers. Each of the 16 register banks contains eight 8-bit registers, which you access in 8-bit or paired 16-bit units. You can also use each of the registers as an 8-bit accumulator or paired as a 16-bit accumulator using an 8-bit ALU and datapaths. The multiple register banks allow you to perform fast task switching and interrupt service. The µC also contains a 16-bit program counter, a hardware stack, and a 16-bit stack pointer.

The TLCS-870 Series has a simple instruction set with 1- to 4-byte-long instructions. Common instructions have short object codes. In addition to the basic machine instructions, a relocatable macro-assembler prepares expansion machine instructions to upgrade coding efficiency. Although there are only 41 types of mnemonics, the architecture supports 20 types of addressing modes. The TLCS-870 can address as much as 64 kbytes of internal memory, and the TLCS-870X can linearly address as much as 1 Mbyte of internal or external memory. To support this extended addressing, the TLCS-870X adds more memory-addressing modes. The TLCS-870X also uses a nonmultiplexed bus with bus request/acknowledge and wait request.

TLCS-870 Series peripherals use a memory-mapped I/O system. You use special-function and data-buffer registers to perform peripheral control and data transfers.

Power management:

Stop mode stops clock oscillation and puts the output ports in high impedance. Slow mode reduces power consumption by using the low-frequency clock. Idle and sleep modes stop the CPU clock but allow the peripherals to operate at various speeds. Software or external interrupts cause the device to come out of idle and sleep modes. Some derivatives can also divide their internal clock by two, four, or eight.

Special instructions:

Bit-manipulation instructions include bit set, clear, complement, move, test, and exclusive. Math instructions include add; subtract; decimal adjust; signed and unsigned 8×8-bit multiply; and signed and unsigned 16×8-bit divide. Nibble manipulation includes swap and nibble rotation. The TLCS-870 also has 1-byte jump or subroutine call for short relative jumps and vector calls.

Development tools:

Toshiba provides a C compiler, a C-like compiler, an assembler, a source-level debugger, a DOS-based controller, and a real-time emulator for each derivative. The controller is common for all derivatives.

Second sources:

There are no second sources for the 20TLCS-870.

SGS-Thomson ST6

The accumulator-based ST6 with only 40 instructions is a low-end µC with two 8-bit index registers; two 8-bit, general-purpose registers; an 8-bit accumulator register; and a 12-bit program counter. All basic arithmetic operations involve the accumulator as one parameter and end by placing a result into the accumulator. However, the ST6 is not a classic accumulator-based CPU. Loads are a bit more flexible; the accumulator can be the source or destination. Also, the ST6 can directly increment and decrement both memory and registers without passing through the accumulator.

Registers and peripherals are memory-mapped in the chip's address space. To configure a peripheral or send or receive data to or from a peripheral, a program simply writes to or reads from the peripheral's memory registers.

The ST6 has a six-level fixed stack to hold the program counter on subroutine calls or interrupts. The stack is not user-accessible, and, therefore, the CPU has no stack-pointer register. If the stack is full and a call or interrupt occurs, the CPU pushes the current program-counter value onto the stack, moves all stack entries down one, and loses the last (first-in) entry.

The program counter directly addresses as much as 4 kbytes of program memory. A banking scheme that uses a dedicated memory-mapped banking register can expand the program memory. The device can bank the lower 2 kbytes of ROM, which provides access to higher 2-kbyte pages in program memory, which ranges to 20 kbytes. Program memory can also hold constants or tables, which the CPU accesses via a 64-byte, memory-mapped window in RAM that maps into ROM.

Power management:

Wait mode discontinues CPU processing but leaves the peripherals enabled. After disabling the watchdog timer, the CPU enters stop mode and stops the clock, peripherals, and all internal processing. Both modes maintain RAM and enable interrupt to wake the CPU. You can program and selectively turn off most peripherals.

Special instructions:

The ST6's bit-manipulation instructions are set and clear. Math functions include add, subtract, increment, and decrement. Relative jumps are restrained to ­15 to +16 locations.

Special on-chip peripherals:

The ST6 family offers multifunction I/O pins with programmable input and output modes, programmable pullups, analog multiplexing, and automatic switching between alternate peripheral resource functions and general-purpose I/O pins. Data, data-direction and pullup registers allow you to configure each pin to meet an application's requirements. High-current I/O pins are also available. An autoreload timer is available on the ST623X, 5X, and 6X families. You can also use this timer for waveform generation and analysis. Some ST6 devices support a se-rial peripheral interface (SPI) with programmable transmission modes and master/slave capabilities. You may also use the SPI to implement asynchronous serial communications, such as RS-232C links, with limited processor overhead. The ST624X has an LCD driver with control logic, a programmable prescaler, and dedicated LCD RAM.

Development tools:

SGS offers development tools including starter kits, in-circuit emulators, and programming boards. Software tools include the ST6-Realizer automatic code generator, which allows you to generate code without knowledge of the ST6. The company also offers a Windows-based development-tool environment and the Fuzzytech fuzzy-logic product.

Second sources:

There are no second sources for the ST6.

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