October 9, 1997

Remystifying ADCs

BILL TRAVIS, SENIOR TECHNICAL EDITOR

In an earlier article, "Demystifying ADCs," we explored the ins and outs of high-speed ADCs. Here, we revisit the topic, only to learn that ADCs are as mystifying as they were before.

In EDN's Hands-On project "Demystifying ADCs," we highlighted some of the difficulties you might encounter when testing high-speed ADCs (Reference 1). In doing so, we ran into difficulties of our own--principally, trying to get the devices to perform according to their published specs. Despite our best intentions and the use of high-quality test equipment, many converters provided seemingly subpar performance. Subsequent dialogue with and retests by several converter manufacturers show that most ADCs can indeed meet and surpass their spec-sheet limits.

The main problem in our Hands-On project was time. What we judged to be ample time to perform the tests and confer with the manufacturers turned out to be insufficient to iron out the discrepancies and difficulties. We had time for some dialogue, but clearly not enough. Perhaps our time-constraint problem can be a lesson for those who contemplate evaluating and designing these touchy devices.

Rebuttals and retests

Several converter manufacturers graciously retested the evaluation boards we used in the project. Some provided in-depth analyses of the possible causes of some of the "subpar" performance we encountered during testing by Muneeb Khalid, founder and president of Gage Applied Sciences (Montreal, PQ, Canada). A notable example is Analog Devices (Norwood, MA), whose converter-product applications engineer Paul Hendriks furnished a comprehensive and detailed analysis of various testing aspects. Hendriks made several points that contain a great deal of valuable advice for aspiring ADC users.

His first point might seem a truism, but it's an important one to keep in mind: "One of the fundamental objectives in evaluating and characterizing the performance of any device is to ensure that the measured test results represent only those of the device under measurement. In other words, the measurements should not reflect any deficiencies in the test equipment, test setup, or procedure used in the evaluation process, as these will only obscure the true performance of the device."

Hendriks attributes our results to a nonideal setup: "Unfortunately, due to what I believe were deficiencies in his test setup, Khalid was unable to obtain any of the manufacturer's rated performance and thus ascertain the actual sensitivities the various ADCs may have in a real-world environment. In particular, based on both the article contents and information submitted by Khalid, I believe his test setup suffered from both external noise coupling and excessive clock jitter."

Analog Devices' test setup for its high-speed ADCs uses a pair of phase-locked synthesizers (Figure 1), whereas the Gage setup uses nonsynchronized Marconi (Allendale, NJ) and Hewlett-Packard (Santa Clara, CA) generators. The Analog Devices arrangement yields coherent, nonwindowed sampling; the Gage setup uses noncoherent sampling that requires a windowing function. Khalid chose noncoherent sampling because of his contention that synchronizing the clock and linear-input sources could give rise to phase noise, or jitter. Hendriks takes issue with this stand:

"I was confused by the statement that 'just synchronizing the analog input and clock wouldn't work in this case, because it would give rise to jitter, or phase noise.' Many of the high-quality signal generators I am aware of typically provide a 10-MHz, 10-dBm Ref_out output as well as a Ref_in input, which conveniently allow the phase locking of the two signal sources. ... The test setup with the HP clock divider has less than 3-psec rms jitter, which is sufficient for testing 12- and 14-bit, high-speed ADCs." In Khalid's experience, Gage's generators are not as amenable to jitter-free synchronization as are Analog Devices' HP synthesizers.

Hendriks contends that coherent, nonwindowed sampling yields the best possible test results. He says, "Since the spectral energy of the original data record is inherently spread over several bins by the windowing function, one can never theoretically achieve the same absolute accuracy as a nonwindowed ADC." He concedes, however, that proper windowing can produce high-quality results: "A properly chosen window function and data record of sufficient length (that is, greater than 16k words) will typically yield accurate results." Note that EDN's tests used a 2k-word, a possible contributing factor in some of the subpar results.

Khalid responds to the coherent-vs-noncoherent issue: "I do not believe I ever suggested that coherent sampling causes jitter. The reason that noncoherent sampling is preferable for ADC testing is that this method operates the ADC in a worst-case environment. It can bring to the forefront errors due to nonlinearity, as well as harmonic distortion, that can potentially be hidden if the signal is coherent. Noncoherent sampling is also the way many users operate their ADCs. For example, it is absolutely impossible to guarantee a CCD or ultrasonic image to be 'coherent' with the sampling frequency. The same thing applies to instrumentation applications. You cannot ask the user to adapt his or her inputs to your requirements. For such applications, it is simply not enough to say, 'We tested the device with coherent sampling.'"

Hendriks attributes some of the results on static noise (variation in output codes with input grounded) and SNR to the physical layout of Gage's test setup: "First, it appears that Khalid used an excessively long and unnecessary ribbon cable to connect the ADC evaluation boards to his CompuScope 8012/DIM located on his PC backplane. This appears to fold back toward the evaluation board before it enters what appears to be an 'open' (unshielded?) PC, which itself probably generates excessive digital noise.

"With regard to the length of the ribbon cable, it places an unnecessarily large capacitive load on the buffers/drivers used on the evaluation boards to isolate the ADC from the cable. This large capacitive load will induce large current transients to appear in the buffer/driver supplies that can possibly couple over to the analog section of the board. Furthermore, the quality of the digital signals passing down such a long ribbon cable (if proper termination is not used) is highly suspicious, since it would cause a large degree of ringing and possibly radiate digital noise like an antenna.

"In the case of the AD9240, which was configured for a differential-mode 5V span, using a transformer, I suspect that the transformer was picking up a lot of the radiated noise from the test setup. In fact, when I laid a long ribbon cable next to the transformer in my test setup, the SNR of the AD9240 at 1.9 MHz dropped from 79.4 to 73 dB. I suspect that those ADC evaluation boards in which transformer coupling was not used would probably show less susceptibility to the radiated noise and thus exhibit improved SNR."

Khalid responds: "This 'fold' in the cable was made at the time of taking the photograph (as a means of beautifying the system). During our tests, all cables were kept straight and away from the boards themselves. The input cable used was a twist-n-flat type; in other words, a twisted-pair flat ribbon cable. Twisted pairs help keep the characteristic impedance within a controlled range--thereby minimizing any loading due to cable length--and minimize radiation. The CompuScope 8012/DIM board features properly terminated input stages (127 ohms) for each of the pairs. A comparator is used to re-create the signal on the CompuScope 8012/DIM board. In any case, the evaluation board shown in the picture [on pg 28 of the Hands-On story] is that of the AD9042, which fared very well in our tests. It used the same 74ACT574 buffers that Hendriks' board uses, so the question of noise feedback due to the load from the cable is questionable itself. Similarly, the AD9042 evaluation board also used a transformer for its clock input, but the supposed radiated noise did not seem to affect that test."

Hendriks continues, "Figure 2 shows Analog Devices' results of a 4k-word nonwindowed FFT using the same AD9240 evaluation board used by Gage. The same test conditions using a lowpass-filtered, 1.914-MHz, full-scale sine-wave input and a 10M-sample/sec sample rate were used. Note, the results in SNR/THD [total harmonic distortion]/SFDR [spurious-free dynamic range] performance are similar to those shown in the AD9240 data sheet." Note that this screen grab corresponds to the one in Figure 6 in the Hands-On article. The Gage setup yielded respective SNR, THD, SNR and distortion (SINAD), and SFDR figures of 69, 84, 83, and 77 dB; Analog Devices' retest figures are 79, 81, 83, and 83.5 dB. Gage's 77-dB SFDR improved to 82 dB (similar to Analog Devices' result) when Khalid used a square-wave clock source rather than a sine wave.

Next, Hendriks attempted to duplicate some aspects of the Gage test setup. He used a long ribbon cable to connect the AD9240 evaluation board to the interface board. He also set the driver supply on the evaluation board to 5V to maximize the digital-output swing and transient supply currents. He then placed the digital-output cable on top of the transformer used on the board to perform a single-ended-to-differential conversion for the analog-input signal. The measured results indicate that the transformer is susceptible to noise coupling and may provide a partial explanation of Gage's problems (Figure 3). With this test setup, the SNR drops from 79 to 73 dB.

Hendriks concedes that the cost of Analog Devices' test setup is high (each HP generator costs more than $40,000) and may be beyond the means of many ADC customers. However, he maintains that expensive, high-quality signal generators combined with solid test-setup procedures are often necessary to determine the true performance of an ADC, especially as the resolution, dynamic range, and speed of these high-performance ADCs increase.

He offers a means to reduce the test-equipment outlay: "In many cases, a single, high-quality signal generator can be used to evaluate the ac performance of an ADC. For any 10M-sample/sec ADC, such as the AD9240, you can use the 10-MHz Ref_out provided on most high-quality generators to generate a 10M-sample/sec clock and still perform a coherent, nonwindowed FFT. You would be required to 'square up' the sine wave for the target ADC, using a high-speed comparator. Figure 4 shows the performance of the AD9240 using a single HP8644A signal generator. For ADCs having sample rates other than 10M samples/sec, I would suggest performing a windowed FFT using a four-term Blackman-Harris (similar to Khalid's) function, using a high-quality signal generator and a low-jitter crystal clock oscillator."

In his report, Hendriks comments on several statements in EDN's Hands-On report, including "Performance parameters specified by manufacturers often are valid only under ideal conditions--if then." Hendriks rebuts, "The specifications and characterization data shown on a manufacturer's ADC data sheet are representative of the ADC's true performance and not necessarily under the most ideal test conditions. While there may be a few disreputable vendors that exaggerate specs, most are honest representations under the stated conditions."

Hendriks also takes issue with the statement, "A single-frequency test is less stressful to converters than is a multiple-frequency test. If a converter can't pass a single-frequency test, imagine what would happen with dual or multitone inputs." He maintains, "In fact, an ADC's performance when sampling a full-scale single frequency at the highest frequency of a band-limited signal is typically a good measure of its worst performance for that waveform, since the internal S/H amplifier of the ADC will often experience the most stress."

The Hands-On article revealed some mysterious behavior with Edge Technology's (Lynnfield, MA) 14-bit ET2473 ADC. With a full-scale input, the SFDR varied by approximately 4 dB from one measurement to another under identical test conditions. With an input signal 20 dB below full scale, the FFT screen grab showed significant spurs at the third, fourth, fifth, and sixth harmonics. In light of Hendriks' comments about the test setup's cabling, it's probably a safe wager that the mysterious results stemmed from cabling-induced noise coupling.

Edge's retests of the ET2473 evaluation board showed better performance than we were able to achieve. In particular, the ­20-dB test showed no spurs at the third, fourth, fifth, and sixth harmonics (Figure 5). Edge applications manager Lot Khani comments, "As shown (and expected), these results exceed those of Khalid's. We do believe that his evaluation was a fair one, and we are not questioning his capability or his equipment. From experience with enough experienced and well-equipped customers, we found Gage's results within our expectations, though we were hoping for better."

We experienced more mysterious behavior with the MN6255, a 40M-sample/sec, 12-bit ADC (not reported in the Hands-On article) from Micro Networks Corp (MNC) (Worcester, MA). With a 40-MHz clock generator, both MNC and Gage recorded respectable SNR, THD, SINAD, and SFDR figures with a 2-MHz analog input. Gage's measured SNR and SINAD, however, dropped from 52 dB to the mid-40-dB range with a 10-MHz analog input. MNC's figures remained high. With a 20-MHz clock, the results became even more bizarre. Gage's SNR and SINAD dropped to 36.1 and 35.9 dB, respectively, with a 2-MHz analog input. MNC's figures improved over those obtained with a 40-MHz clock. The reasons for these discrepancies remain a mystery.

Specification discrepancies were not the only gremlins we encountered in the Hands-On effort. Some devices were simply inoperative. Two devices from Harris (Melbourne, FL) provide an example. Gage's report for the HI5766EVAL1, a 10-bit, 60M-sample/sec ADC, reads, "Input seems to be saturated; no SNR measurements can be made, as they will not be meaningful." You should note that, under tight deadline pressure, our tendency was to pass over devices that posed major problems and proceed to operational devices. Again, more time would have permitted troubleshooting and conferences with manufacturers.

Harris application engineer Davin Yuknis reports: "U4, a voltage-reference op amp, was blown out, thus affecting the performance of the converter. We were not able to replicate how the op amp was destroyed." Gage's report for another Harris ADC, the 10-bit, 40M-sample/sec HI5703-EV, says, "No activity on the ADC output. Most likely a wrong bias (no calibration info)."

Yuknis responds, "Instead of in-stalling an input transformer to convert single-ended [signals] to differential, Gage soldered a wire in its place. However, a jumper pin was left disconnected, thus giving no signal to the input of the ADC. Various evaluation implementations using different input methods are discussed in the application note. It appears that Gage chose an alternative input and did not change the jumper settings. As standard practice, all evaluation boards follow the same outgoing test procedures as ICs before they leave Harris. They get 100% tested, boxed, sealed, and put into inventory. These boards were no exception. Our conclusion is that they were user-damaged."

Yuknis continues, "The volume of evaluation boards Gage was evaluating was rather large and included many vendors. The layout of company A's board is not the same as that of company B's board, so some confusion was probably present. The difficulty that a high-speed-converter expert like Gage had with setting up the boards only substantiates the complexity of these devices, which are best handled with factory engineering support.

"We have slated the damaged evaluation boards for repair. In the interest of time, we've run an FFT plot on an existing HI5703-EV from stock." (See Figure 6). "As you will see, the device is within the data-sheet guarantees and tracks the typical performance as expected. We understand through [the Hands-On] article and customer feedback that not all converters perform as per data sheet. Harris has acknowledged this as an issue, and in fact has authored two articles (References 2 and 3) that decipher high-speed-converter specifications and illustrate how 'games' can be played to make certain numbers appear better."

Despite the mysterious things that happened during our Hands-On effort and the ensuing manufacturers' retests, certain points emerged that may serve as lessons for those who aspire to evaluate high-speed ADCs:

• Give yourself enough time. If you think the evaluation will take x time, allow for at least 2x for troubleshooting the problems that will inevitably arise. Much of the time will involve back-and-forth communications with ADC vendors.
• Avail yourself, to the fullest extent possible, of manufacturers' engineering aids. These aids include fully wired evaluation boards, as well as complete evaluation systems. In his report, for example, Hendriks describes a complete Analog Devices evaluation platform that includes all the necessary hardware and software to capture a data record and perform an FFT or a histogram analysis. To attempt to roll your own evaluation system (or even ADC board) is penny-wise and pound-foolish.
• Keep all lines short and all systems shielded. It's evident that our Hands-On testing suffered from noise coupling. If you use ribbon cable for the digital outputs, make it as short as possible and keep it well away from analog lines.
• Don't jump to conclusions. If the manufacturer's data sheet specifies 65-dB SNR and you obtain 57 dB, don't automatically assume that the converter is faulty. Conferring with the vendor might reveal some shortcoming in your test methodology or equipment. In the worst case, you can return the evaluation board to the manufacturer, which will be willing and happy to test it and supply correlation data.

References

1. Travis, Bill, "Demystifying ADCs," EDN, March 27, 1997, pg 26.
2. "Deciphering specs for high-speed D/A converters," Electronic Products, May 1995.
3. "A guide to evaluating competing analog-to-digital converters," Wireless Systems Design, September 1997.

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